FI843759A0 - FOERFARANDE FOER DRIFT AV EN MULTIPROCESSOR-STYRRAEKNARE, SAERSKILT FOER CENTRALSTYRENHETEN VID ETT TELEFONFOERMEDLINGSSYSTEM. - Google Patents

FOERFARANDE FOER DRIFT AV EN MULTIPROCESSOR-STYRRAEKNARE, SAERSKILT FOER CENTRALSTYRENHETEN VID ETT TELEFONFOERMEDLINGSSYSTEM.

Info

Publication number
FI843759A0
FI843759A0 FI843759A FI843759A FI843759A0 FI 843759 A0 FI843759 A0 FI 843759A0 FI 843759 A FI843759 A FI 843759A FI 843759 A FI843759 A FI 843759A FI 843759 A0 FI843759 A0 FI 843759A0
Authority
FI
Finland
Prior art keywords
special
cmy
processor
foer
inherently
Prior art date
Application number
FI843759A
Other languages
Finnish (fi)
Other versions
FI88219B (en
FI88219C (en
FI843759L (en
Inventor
Rudolf Bitzinger
Walter Engl
Siegfried Humml
Klaus Schreier
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of FI843759A0 publication Critical patent/FI843759A0/en
Publication of FI843759L publication Critical patent/FI843759L/en
Publication of FI88219B publication Critical patent/FI88219B/en
Application granted granted Critical
Publication of FI88219C publication Critical patent/FI88219C/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54508—Configuration, initialisation
    • H04Q3/54516—Initialization, software or data downloading
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/1305—Software aspects
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13109—Initializing, personal profile
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
    • H04Q2213/13376—Information service, downloading of information, 0800/0900 services

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Storage Device Security (AREA)
  • Executing Machine-Instructions (AREA)
  • Pyridine Compounds (AREA)
  • Multi Processors (AREA)
  • Memory System (AREA)

Abstract

Method for the operation of a multiprocessor controller, at least some of the processors (BP, CP, IOC, IOP) having access via first switches (S) and thus via each half (B:CMY0, B:CMY1) of a central inherently duplicated bus system (B:CMY) and second switches (SW) connected thereto to each half of an inherently duplicated main memory (CMY), or to each half (e.g. MB3a or MB3b) of one or more inherently duplicated memory banks (MB) of the main memory (CMY). In a special operating time, a redundant part of the controller is separated and interconnected to form a small, discrete, independently operating special processor by interconnecting individual redundant processors of this group (e.g. CP9 and/or IOC1) to one half (e.g. B:CMY1) of the bus system (B:CMY) and to a part of the main memory (CMY) or the memory banks (MB) in order to form an independent special processor for a special program, and continuing to run the so far normally operating program in the remaining parts of the controller, that is to say in the residual processor. The special processor later interrupts its special program. The components of the special processor are reconnected to the residual processor in such a way that only the normal operating program or a newly input modification thereof runs. <IMAGE>
FI843759A 1983-09-26 1984-09-25 Method of operating a multiprocessor controller, especially for the central controller of a telephone switching system FI88219C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19833334796 DE3334796A1 (en) 1983-09-26 1983-09-26 METHOD FOR OPERATING A MULTIPROCESSOR CONTROLLER, ESPECIALLY FOR THE CENTRAL CONTROL UNIT OF A TELECOMMUNICATION SWITCHING SYSTEM
DE3334796 1983-09-26

Publications (4)

Publication Number Publication Date
FI843759A0 true FI843759A0 (en) 1984-09-25
FI843759L FI843759L (en) 1985-03-27
FI88219B FI88219B (en) 1992-12-31
FI88219C FI88219C (en) 1993-04-13

Family

ID=6210097

Family Applications (1)

Application Number Title Priority Date Filing Date
FI843759A FI88219C (en) 1983-09-26 1984-09-25 Method of operating a multiprocessor controller, especially for the central controller of a telephone switching system

Country Status (6)

Country Link
EP (1) EP0141246B1 (en)
JP (1) JPH0666985B2 (en)
AT (1) ATE63029T1 (en)
DE (2) DE3334796A1 (en)
FI (1) FI88219C (en)
ZA (1) ZA847567B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3334796A1 (en) * 1983-09-26 1984-11-08 Siemens AG, 1000 Berlin und 8000 München METHOD FOR OPERATING A MULTIPROCESSOR CONTROLLER, ESPECIALLY FOR THE CENTRAL CONTROL UNIT OF A TELECOMMUNICATION SWITCHING SYSTEM
DE3629399A1 (en) * 1986-08-29 1988-03-03 Siemens Ag Method for operating the central memory of a multiprocessor-type common control unit of a switching system
WO1988007314A1 (en) * 1987-03-19 1988-09-22 Siemens Aktiengesellschaft Process for operating a multiprocessor central control unit of a relay system
CA2003338A1 (en) * 1987-11-09 1990-06-09 Richard W. Cutts, Jr. Synchronization of fault-tolerant computer system having multiple processors
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5295258A (en) 1989-12-22 1994-03-15 Tandem Computers Incorporated Fault-tolerant computer system with online recovery and reintegration of redundant components
US6950893B2 (en) * 2001-03-22 2005-09-27 I-Bus Corporation Hybrid switching architecture
KR101131306B1 (en) 2004-06-30 2012-03-30 엘지디스플레이 주식회사 Back light unit of liquid crystal display device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2232256A5 (en) * 1973-05-29 1974-12-27 Labo Cent Telecommunicat
US4363094A (en) * 1977-12-29 1982-12-07 M/A-COM DDC, Inc. Communications processor
DE3334773A1 (en) * 1983-09-26 1984-11-08 Siemens AG, 1000 Berlin und 8000 München METHOD FOR OPERATING A PAIR OF MEMORY BLOCKS OPERATING IN NORMAL OPERATING TIME
DE3334796A1 (en) * 1983-09-26 1984-11-08 Siemens AG, 1000 Berlin und 8000 München METHOD FOR OPERATING A MULTIPROCESSOR CONTROLLER, ESPECIALLY FOR THE CENTRAL CONTROL UNIT OF A TELECOMMUNICATION SWITCHING SYSTEM

Also Published As

Publication number Publication date
ATE63029T1 (en) 1991-05-15
DE3334796A1 (en) 1984-11-08
ZA847567B (en) 1985-05-29
EP0141246B1 (en) 1991-04-24
JPH0666985B2 (en) 1994-08-24
FI88219B (en) 1992-12-31
DE3484496D1 (en) 1991-05-29
EP0141246A2 (en) 1985-05-15
JPS60102089A (en) 1985-06-06
FI88219C (en) 1993-04-13
EP0141246A3 (en) 1988-02-10
FI843759L (en) 1985-03-27

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MM Patent lapsed

Owner name: SIEMENS AKTIENGESELLSCHAFT