JPS60138652A - Memory bank switching system - Google Patents

Abstract

PURPOSE:To transfer the control between to plural banks without changing a program so far produced by providing an address decoder and a calculating circuit which outputs the bank data and the entry data. CONSTITUTION:An address bus 12 supplies the address signal produced by a CPU11 to an address decoder 13. This decoder 13 is provided to discriminate a specific address range, and this address range is prescribed by a decoder control circuit 14 at 100-400 for example. The decoder 13 produces an interruption signal INT with input of an address signal set within said address range. This address signal is also supplied to a calculating circuit 15. The circuit 15 calculates from the input address and outputs the bank data BKD showing the difference between memory banks A and B at the switching destinations and the entry data ETD related to an entry address of the switching bank.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory bank switching system when a plurality of memory banks are provided in order to expand the memory space of a computer.

[Prior art]

The memory bank switching method that makes it possible to effectively expand the memory space by switching and using multiple memory spaces that have the same address when viewed from the cp'u (central processing unit) has been around for a long time. It is used.

However, when attempting to utilize such a memory space, there are various troubles in creating software. That is, since programs located in different memory banks cannot be directly accessed, it is necessary to prepare in advance a means for transferring control of the memory bank k in the program.

This means that the arrangement of each program to be loaded on a plurality of memory banks must be determined in advance, which has been an obstacle in program development.

〔the purpose〕

The present invention was made in order to eliminate such drawbacks of the conventional technology, and by using hardware innovations, bank switching is not considered at all when creating a program, and it is possible to program in the same way as programming within the same bank. Programs can be placed in multiple banks after programming is completed, and in this case, control can be transferred between different banks without changing the programs created up to that point. The purpose is to provide a memory bank switching method.

[Structure of the invention]

The memory bank switching method according to the present invention includes an address decoder that issues an interrupt signal when a preset address is given, and bank data and a switching destination that specify the switching destination bank when the address is given. a calculation circuit that outputs entry data related to the entry address of the bank; when bank switching is required, the address is given to an address decoder; and a switching destination bank is determined according to the bank data obtained by the calculation circuit; Furthermore, the present invention is characterized in that the entry address of the switching bank is accessed based on the entry data.

〔Example〕

Hereinafter, the present invention will be described based on drawings showing an embodiment of the case where the number of memory banks to be switched is 2 (μm).

Reference numeral 12 denotes an address bus which supplies address signals issued by the CPU IT to the address decoder 13. This address decoder 13 is provided to identify a specific address range, and the address range is defined by a decoder control circuit 14. For example, this address range is 10
It is defined as a range from 0 to 400, and when an address signal within the range is manually input to the address decoder 13, an interrupt signal INT is generated.

Further, when an address signal in this range is input, it is applied to the calculation circuit 15. From this input address, the calculation circuit 15 calculates and outputs bank data BKD and entry data ETD related to the En1-Rear address of the switching destination bank, without indicating whether the switching destination memory banks A or H are selected. For example, when the address signal is 100 to 300, the bank data BKD is the content "A" representing memory bank A, 301 to 4.
If it is 00, the content is "B" representing memory bank B. For example, when the address signal is 102, the entry data ETD is "'2", which is 102 minus the minimum value 100 on the switching destination bank A side, and when the address signal is 3.
If it is 11, it becomes "lO", which is obtained by subtracting the minimum value 301 on the switching destination bank B side. Bank data BKD like this
, the conditions for calculating the entry data ETD are defined by the calculation circuit control section 16. These interrupt signal INT, bank data BKII, and entry data ETD are sent to the CPU.
given to 11.

Reference numeral 18 denotes an instruction decoder, which decodes and outputs program control instructions such as "CALL" and "JUMP" applied via the data bus 17.The address range 100 to 400 defined as described above is This is set as an area for bank switching, and "CALL" JU
When this area is accessed by a key command, an interrupt signal INT is generated and the memory bank is switched.

Next, an overview of the operation of the software in the present invention will be explained. When branching to another memory bank, the address decoder 13. The calculation circuit 15 branches to the area identified. Immediately, this area becomes an entry when branching to a program in another memory bank. When branching to this area, the interrupt signal INT is generated, but in the interrupt processing for this, the output of the instruction decoder 18 is checked, and if the instruction is "CALL", the return is made to the original bank after this branch. Since it is a command, data specifying the current memory bank is stored, and then bank data BK of the calculation circuit 15 is stored.
Switch the memory bank according to the contents of I).

For example, if the command "CALL" is given while memory bank A is being accessed and the address signal is 311, the data specifying memory bank A is stored;
Switch to memory bank B.

The same interrupt processing is configured in software for each of memory banks A and B, and a correspondence table between entry data (ETI) and entry addresses is prepared in software. Then, as described above, switching to memory bank B is performed, and the entry data ETD (in this case,
) and branches to the corresponding entry address.

〔effect〕

As described above, according to the present invention, there is no need for special coding for switching memory banks in terms of programming, and a program can be created in exactly the same way as a program that operates within the same memory bank. After the entire program is completed, it is distributed appropriately to each memory bank, the range of the address decoder 13 is defined by the decoder control circuit I4, and the calculation circuit 15 is controlled by the calculation circuit control section 16.
It is only necessary to define the conditions and add a correspondence table between entry data ETD and entry addresses. This makes it possible to easily create a program that spans multiple memory banks, so this advantage can be enjoyed not only during program coding but also during debugging during program development.

[Brief explanation of drawings]

The drawing is a block diagram schematically showing the main parts of a circuit for implementing the memory bank switching method of the present invention. A, B...Memory bank 11...CPIJ 13
...Address decoder 15...Calculation circuit 18.
...Instruction decoder agent Patent attorney Noboru Kono

Claims (1)

[Claims] 1. In a computer that switches between multiple memory banks, an address decoder that issues an interrupt signal when a preset address is given, and a bank that identifies the hang destination to switch to when the address is given. data and a calculation circuit that outputs entry data related to the entry address of the switching destination bank, and when bank switching is required, the address is given to the address decoder, and the switching destination is provided according to the bank data obtained by the calculation circuit. A memory bank switching method characterized by determining a bank and further accessing an entry address of a switching bank based on entry data.