JPS56108161A - Operation control system for multiprocessor - Google Patents

Operation control system for multiprocessor

Info

Publication number
JPS56108161A
JPS56108161A JP1033780A JP1033780A JPS56108161A JP S56108161 A JPS56108161 A JP S56108161A JP 1033780 A JP1033780 A JP 1033780A JP 1033780 A JP1033780 A JP 1033780A JP S56108161 A JPS56108161 A JP S56108161A
Authority
JP
Japan
Prior art keywords
processor
monitor
processors
fault
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1033780A
Other languages
Japanese (ja)
Other versions
JPS619660B2 (en
Inventor
Tsuneo Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1033780A priority Critical patent/JPS56108161A/en
Publication of JPS56108161A publication Critical patent/JPS56108161A/en
Publication of JPS619660B2 publication Critical patent/JPS619660B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To prevent the effect of misinformation from extending to a normal processor, by providing a memory having the information showing the fault and its state plus the artifical block request information to each processor and then monitoring periodically the state of operation by the monitor processor. CONSTITUTION:The monitor processors SP0 and SP1 give a periodical monitor to all processors PR0-PRn. When detecting a faulty flag of the state memory SM0, the monitor processor decides whether the fault is temporary or steady and then gives a halfway fault or processor blocking. The processor control memories BCM0 and BCM1 are driven by the blocking, and at the same time the fault information is typed out through the typewriter TYP. The monitor processor monitors the common bus in addition to the monitor bus and thus controls the memory BCM0 or BCM1. Thus all processors or a specified processor are/is blocked partially to reduce the effect to other processors on the line.
JP1033780A 1980-01-31 1980-01-31 Operation control system for multiprocessor Granted JPS56108161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1033780A JPS56108161A (en) 1980-01-31 1980-01-31 Operation control system for multiprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1033780A JPS56108161A (en) 1980-01-31 1980-01-31 Operation control system for multiprocessor

Publications (2)

Publication Number Publication Date
JPS56108161A true JPS56108161A (en) 1981-08-27
JPS619660B2 JPS619660B2 (en) 1986-03-25

Family

ID=11747373

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1033780A Granted JPS56108161A (en) 1980-01-31 1980-01-31 Operation control system for multiprocessor

Country Status (1)

Country Link
JP (1) JPS56108161A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139138A (en) * 1984-07-31 1986-02-25 Nec Corp Multiplexing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6139138A (en) * 1984-07-31 1986-02-25 Nec Corp Multiplexing system

Also Published As

Publication number Publication date
JPS619660B2 (en) 1986-03-25

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