FI80533C - Kontroll av datamaskinhierarki. - Google Patents

Kontroll av datamaskinhierarki. Download PDF

Info

Publication number
FI80533C
FI80533C FI842384A FI842384A FI80533C FI 80533 C FI80533 C FI 80533C FI 842384 A FI842384 A FI 842384A FI 842384 A FI842384 A FI 842384A FI 80533 C FI80533 C FI 80533C
Authority
FI
Finland
Prior art keywords
unit
cache
data
input
dpu
Prior art date
Application number
FI842384A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI842384A0 (fi
FI842384L (fi
FI80533B (fi
Inventor
Lane K Hooker
Thomas H Howell
Charles W Ferrell
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of FI842384A0 publication Critical patent/FI842384A0/fi
Publication of FI842384L publication Critical patent/FI842384L/fi
Publication of FI80533B publication Critical patent/FI80533B/fi
Application granted granted Critical
Publication of FI80533C publication Critical patent/FI80533C/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Small-Scale Networks (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Multi Processors (AREA)
FI842384A 1983-07-07 1984-06-13 Kontroll av datamaskinhierarki. FI80533C (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US51161683 1983-07-07
US06/511,616 US4695951A (en) 1983-07-07 1983-07-07 Computer hierarchy control

Publications (4)

Publication Number Publication Date
FI842384A0 FI842384A0 (fi) 1984-06-13
FI842384L FI842384L (fi) 1985-01-08
FI80533B FI80533B (fi) 1990-02-28
FI80533C true FI80533C (fi) 1990-06-11

Family

ID=24035680

Family Applications (1)

Application Number Title Priority Date Filing Date
FI842384A FI80533C (fi) 1983-07-07 1984-06-13 Kontroll av datamaskinhierarki.

Country Status (10)

Country Link
US (1) US4695951A (OSRAM)
EP (1) EP0131277B1 (OSRAM)
JP (1) JPS6039259A (OSRAM)
KR (1) KR930002337B1 (OSRAM)
AU (1) AU578420B2 (OSRAM)
CA (1) CA1214884A (OSRAM)
DE (1) DE3478519D1 (OSRAM)
FI (1) FI80533C (OSRAM)
NO (1) NO167831C (OSRAM)
YU (1) YU45633B (OSRAM)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0198574A3 (en) * 1985-02-05 1989-11-29 Digital Equipment Corporation Apparatus and method for data copy consistency in a multi-cache data processing system
JP2539357B2 (ja) * 1985-03-15 1996-10-02 株式会社日立製作所 デ−タ処理装置
US5349672A (en) * 1986-03-17 1994-09-20 Hitachi, Ltd. Data processor having logical address memories and purge capabilities
US5113510A (en) * 1987-12-22 1992-05-12 Thinking Machines Corporation Method and apparatus for operating a cache memory in a multi-processor
US5226146A (en) * 1988-10-28 1993-07-06 Hewlett-Packard Company Duplicate tag store purge queue
US5185875A (en) * 1989-01-27 1993-02-09 Digital Equipment Corporation Method and apparatus for reducing memory read latency in a shared memory system with multiple processors
US5206941A (en) * 1990-01-22 1993-04-27 International Business Machines Corporation Fast store-through cache memory
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5263144A (en) * 1990-06-29 1993-11-16 Digital Equipment Corporation Method and apparatus for sharing data between processors in a computer system
JPH0827755B2 (ja) * 1991-02-15 1996-03-21 インターナショナル・ビジネス・マシーンズ・コーポレイション データの単位を高速度でアクセスする方法
US5185861A (en) * 1991-08-19 1993-02-09 Sequent Computer Systems, Inc. Cache affinity scheduler
US5428761A (en) * 1992-03-12 1995-06-27 Digital Equipment Corporation System for achieving atomic non-sequential multi-word operations in shared memory
JPH0797352B2 (ja) * 1992-07-02 1995-10-18 インターナショナル・ビジネス・マシーンズ・コーポレイション コンピュータ・システム及び入出力コントローラ
US5684977A (en) * 1995-03-31 1997-11-04 Sun Microsystems, Inc. Writeback cancellation processing system for use in a packet switched cache coherent multiprocessor system
US5655100A (en) * 1995-03-31 1997-08-05 Sun Microsystems, Inc. Transaction activation processor for controlling memory transaction execution in a packet switched cache coherent multiprocessor system
US6018791A (en) * 1997-04-14 2000-01-25 International Business Machines Corporation Apparatus and method of maintaining cache coherency in a multi-processor computer system with global and local recently read states
US6477620B1 (en) * 1999-12-20 2002-11-05 Unisys Corporation Cache-level return data by-pass system for a hierarchical memory

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1124017A (en) * 1964-12-17 1968-08-14 English Electric Computers Ltd Data storage apparatus
US3510844A (en) * 1966-07-27 1970-05-05 Gen Electric Interprocessing multicomputer systems
US3735360A (en) * 1971-08-25 1973-05-22 Ibm High speed buffer operation in a multi-processing system
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
US3771137A (en) * 1971-09-10 1973-11-06 Ibm Memory control in a multipurpose system utilizing a broadcast
US3967247A (en) * 1974-11-11 1976-06-29 Sperry Rand Corporation Storage interface unit
US4471429A (en) * 1979-12-14 1984-09-11 Honeywell Information Systems, Inc. Apparatus for cache clearing
DE3176632D1 (en) * 1980-11-10 1988-03-03 Ibm Cache storage hierarchy for a multiprocessor system
US4394731A (en) * 1980-11-10 1983-07-19 International Business Machines Corporation Cache storage line shareability control for a multiprocessor system
US4394727A (en) * 1981-05-04 1983-07-19 International Business Machines Corporation Multi-processor task dispatching apparatus
US4503497A (en) * 1982-05-27 1985-03-05 International Business Machines Corporation System for independent cache-to-cache transfer
US4551799A (en) * 1983-02-28 1985-11-05 Honeywell Information Systems Inc. Verification of real page numbers of stack stored prefetched instructions from instruction cache
US4527238A (en) * 1983-02-28 1985-07-02 Honeywell Information Systems Inc. Cache with independent addressable data and directory arrays

Also Published As

Publication number Publication date
JPS6039259A (ja) 1985-03-01
YU119284A (en) 1986-12-31
NO167831C (no) 1991-12-11
US4695951A (en) 1987-09-22
EP0131277A2 (en) 1985-01-16
AU3024984A (en) 1985-01-10
KR930002337B1 (ko) 1993-03-29
YU45633B (sh) 1992-07-20
FI842384A0 (fi) 1984-06-13
CA1214884A (en) 1986-12-02
EP0131277B1 (en) 1989-05-31
NO167831B (no) 1991-09-02
JPH0457026B2 (OSRAM) 1992-09-10
DE3478519D1 (en) 1989-07-06
KR850001572A (ko) 1985-03-30
FI842384L (fi) 1985-01-08
EP0131277A3 (en) 1986-06-11
FI80533B (fi) 1990-02-28
NO842747L (no) 1985-01-08
AU578420B2 (en) 1988-10-27

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Legal Events

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MM Patent lapsed
MM Patent lapsed

Owner name: HONEYWELL INFORMATION SYSTEMS INC.