FI74166C - SKYDDSKRETS FOER INTEGRERADE KRETSANORDNINGAR. - Google Patents

Description

1 74166

Protection circuit for integrated circuit devices

The present invention relates to integrated circuit (IC) protection devices.

5 Many types of electrical equipment include ICs that are susceptible to damage from high-voltage transients.

For example, in a television receiver that includes integrated circuits for processing video and audio signals, the anode of the image-generating picture tube is typically preset to a high potential, about 25,000 volts. High-voltage transients are generated by the formation of arcs in the picture tube, which occurs when the high-voltage anode of the picture tube rapidly discharges. Arc formation in the picture tube-15 may also occur unpredictably between the anode and one or more other lower voltage electrodes of the picture tube while the television is in normal operation. In either case, the formation of photocells in the picture tube at the terminals of the integrated circuit results in high voltage transients, the positive and negative peaks of which often exceed 100 volts and which last from one microsecond to several microseconds.

Another cause of high voltage transients in the tclevi-25 filter receiver is electrostatic discharge. The user can discharge the electrostatic charge through the controllers of the television receiver, thus creating a high voltage transient that can damage the integrated circuits in the television receiver.

The present invention is implemented in an integrated circuit semiconductor shield circuit comprising a semiconductor substrate, a first conductivity type semiconductor layer disposed on a semiconductor substrate, a first and a second semiconductor region of a second conductivity region, wherein both semiconductor regions are matched to a semiconductor region. formed in the second 2 74166 semiconductor region / wherein the emitter region is contacted by the first connecting conductor. The semiconductor circuit according to the invention is in turn characterized in that the first connecting conductor is connected to the terminal of the supply voltage source 5, the first semiconductor region is contacted by the second connecting conductor and connected to the utility circuit protected is connected to the supply voltage source connector by means of the first connection cable.

The protection circuit is thus connected at one terminal to the circuit terminal of the circuit to be protected and at the other terminal to the operating voltage source. When the voltage acting on the circuit terminal 15 of the circuit to be protected exceeds the operating voltage by an amount equal to a predetermined threshold value, the protection circuit becomes conductive, thus protecting the integrated circuit from damage.

In the following, the invention will be explained in more detail with reference to the examples according to the accompanying drawings, in which: Fig. 1 is a cross-sectional view of one embodiment of a semiconductor structure implementing a protection circuit according to the present invention; Fig. 2 is a diagram of an embodiment of the semiconductor protection circuit of Fig. 1; Fig. 3 is a cross-sectional view of a second embodiment of a semiconductor structure implementing a protection circuit in accordance with the present invention; and Fig. 4 is a diagram of an embodiment of the semiconductor protection circuit of Fig. 3.

As shown in Fig. 1, the semiconductor circuit is made of a substrate 10 which may be formed of a P-type silicon material. An epitaxial layer 12, which may be of the N-conductivity type, is disposed on the substrate 35. The P-type region 14 is formed of N -type epitaxial layer 12, forming a PN connection with the N-type layer 12. A second P-type region 16 3 74166 is formed in the N-type epitaxial layer 12, forming a PN connection with the epitaxial layer 12. The N + region 18 is formed in the P-type region 16 and forms a PN connection with the P-type region 16. A second N + -type region 20 is formed in the N-type epitaxial layer 12. The embedded N + region 11 is located below the P-regions 14 and 16.

The insulating layer 22, which may be silica, coats the surface of the N-epitaxial layer 12. Apertures are formed in the insulating layer 10 at the regions 14, 18 and 20 to form corresponding electrical contacts therein. The conductive layer 26, which may be, for example, aluminum, is located on top of the insulating layer 22 and makes contact with the regions 18 and 20. The conductive layer 26 is further connected to a terminal 30 which receives a positive operating voltage V + of the supply source. The conductive layer 24, which may also be aluminum, extends through an opening in the insulating layer 22 to make contact with the region 14. The contact 28 is connected to the region 14 via the conductive layer 20 24. Contact 28 is further connected to the input or output terminal of a utility circuit (not shown) elsewhere in the integrated circuit. The P + region 32 extends from the surface of the epitaxial layer 12 to the substrate 10. The region 32 surrounds the epitaxial layer 12, isolating the protective circuit from the other circuits 12 of the substrate account.

Figure 2 is a diagram of the structure shown in Figure 2 with the resistive element being linear. The protection circuit comprises an NPN transistor Q1, a PNP transistor Q2 and a linear resistive element marked as a resistor 30. The emitter electrode 118, the base electrode 116 and the collector electrode 112 of the transistor Q1 correspond to the regions 18, 16 and 12, respectively, in Fig. 1. The emitter electrode 114, the base electrode of the transistor Q2 112 and collector electrode 116 correspond to regions 14, 12 and 16 in Figure 1, respectively.

A resistor R, indicated by reference numeral 120, is connected between the base electrode 112 of the transistor Q2 and the emitter electrode 118 of the transistor Q1 and corresponds to the area of the N-type epi-4 74166 taxonomic layer 12 between the P region 16 and the N + region 20 in the figure. 1- The conductor 126 between the emitter electrode of the transistor Q1 and the resistor R corresponds to the conductive layer 26 in Fig. 1.

5 The value of the resistor R is determined by the resistivity of the N-epitaxial layer 12 and the geometry of the N-epitaxial layer between the P-region 16 and the N + region 20 (Fig. 1). For example, the resistance of the resistor R can be increased by locating the N + region 20 further away from the P region 16.

The embedded N + region 11 also significantly reduces the resistivity of the N-epitaxial layer 12. Thus, the embedded N + region, located directly below the P-regions 14 and 16, does not extend below the portion of the N-epitaxial layer 12 between the P-region 16 and the N + region 20.

In Figure 2, transistors Q1 and Q2 are connected together to form a controllable silicon rectifier (SCR). More specifically, the base electrode of the transistor Q1 is connected to the collector electrode of the transistor Q2, and the base electrode of the transistor Q2 is connected to the collector electrode of the transistor Q1. Resistor R is effectively connected in series with the collector-emitter paths of transistor Q1.

Referring now to Figure 3, there is shown a semiconductor circuit made on a substrate 10, which may typically consist of a P-type silicon material and have an embedded region 11 having N + -type-25 conductivity. An epitaxial layer 12 having N-type conductivity is disposed on the substrate 10. The P-type region 14 is formed in the N-type epitaxial layer 12, forming a PN connection with the N-type layer 12. A second P-type region 30 is formed in the N-type epitaxial layer 12, forming a PN connection with the epitaxial layer 12. An N + -type region 18 is formed in the P-type region 16 to form a PN connection with the P-type region 16. The combination 35 of regions 12, 16 and 18 represents the collector, base and emitter of transistor Q1, respectively. In this embodiment, the P-type region 38 is formed in the N-type epitaxial layer 12 and the N + region 20 is formed in the P-type region 38. The regions 20 and 38 together form the N + region formed in the N-epitaxial layer 12 adjacent to the P-type region 38. 36 preferably represent the emitter, base and collector of transistor Q3. The embedded N + region 11 is located below the P regions 14, 16, and 38.

The insulating layer 22, which may be silica, coats the surface of the N-epitaxial layer 12. Apertures are formed in the insulator layer 10 at the regions 14, 18, 36, 38 and 20 to form corresponding electrical contacts therein. The conductive layer 26, which may be, for example, aluminum, extends through the insulating layer 22 and provides an ohmic contact to the region 18. The conductive contact 34, 15, which may be aluminum, provides an ohmic contact to the regions 36 and 38 to short-circuit the base and collector regions of the transistor Q3. The conductive contact 26 is further connected, by means of a conductor 42, to the terminal 30 which receives the positive operating voltage-V of the supply source-20. The conductive layer 24, which may also be aluminum, extends through an opening in the insulating layer 22 to provide contact with the region 14. The contact 28 is connected to the region 14 through the conductive layer 24. Contact 28 is further connected to the input or output terminal of a utility circuit (not shown) elsewhere in the integrated circuit. The P + isolation region 32 extends from the surface of the epitaxial layer 12 to the substrate 10 and also surrounds the epitaxial layer 12 to isolate the protective circuit from other circuits on the substrate 12. In this connection, it should be noted 30 that once the insulator region 32 has been formed, a P + region 40 may also be formed in the region 14. This added region 40 tends to improve the emitter injection efficiency and reduce the contact resistance or the "on" resistance of transistor Q2.

Fig. 4 is a schematic circuit diagram of the structure shown in Fig. 3 with the resistive element being a non-linear resistive element in the form of a diode. The protection circuit comprises an NPN transistor Q1, a PNP transistor Q2 and a non-linear resistive element formed by a diode-connected NPN transistor Q3. The emitter electrode 118, base electrode 116, and collector electrode 112 of transistor 5 Q1 correspond to regions 18, 16, and 12 in Fig. 3, respectively. dio-10 is connected between the base electrode of transistor Q2 and the operating voltage source 30. The base area 138 and collector area 136 of transistor Q3 are short-circuited by contact 34 (Fig. 3) to form a diode, while the emitter area 120 (area 20, Fig. 3) is connected to the operating voltage source 30 by conductor 144 (line 44, Fig. 3). To complete the device, conductor 142 connects transistor Q3 to emitter 120 and transistor Q1 to emitter 118 (via contact 126) to source 30.

The value of the resistor R (Fig. 1) was determined solely by the resistivity of the N20 epitaxial layer 21 and the geometry of the N-epitaxial layer 12 located between the P region 16 and the N + region 20. For example, the resistance of resistor R can be increased by placing the N + region farther from the P region 16. As in the circuit of Figure 2, the base current is needed to ignite Q2 to allow regenerative operation, causing the transistor combination Q1 / Q2 to remain in its state. In the circuit diagram of Figure 4, the presence of transistor Q3 (non-linear resistive element) while biased in the discharge direction adds an additional voltage drop of about 0.6 volts that must be overcome before ignition operation can occur. However, the presence of transistor Q3 increases the blocking bias voltage by about 7 volts, which is characteristic of a diode, along with a blocking bias voltage of 8 volts due to the presence of a deep diffusion region 40 in contact with the N + region. Thus, a total blocking breakdown voltage of about 15 volts I: 7 74166 is required, which is necessary when using a power supply of about 12 volts.

As shown in Fig. 2, the transistors Q1 and Q2 of Fig. 4 are connected to form a controllable silicon rectifier (SCR) 5. More specifically, the base electrode of transistor Q1 is connected to the collector electrode of transistor Q2 and the base electrode of transistor Q2 is connected to the collector electrode of transistor Q1. The transistor Q3 connected as a diode is effectively connected in series with the collector-emitter paths of the transistor Q1.

The resulting protection circuit differs from a conventional SCR device in that a resistive element (the linear resistor R in Fig. 2 or the diode-coupled transistor in Fig. 4) converts a conventional three-pole SCR device into a two-pole device that becomes conductive when its voltage across the terminals exceeds the threshold value. Furthermore, unlike a conventional SCR, the present invention does not require a resistor between the base and emitter electrodes of either transistor Q1 or Q2.

The protection circuit according to both embodiments (Figures 2 and 4) is connected to the terminal 30 via a conductor 126 which receives the positive operating voltage V + of the supply source. The protection circuit is also connected to the contact 28 via the emitter electrode of the transistor 252, to which the useful circuit to be protected is connected.

In the operating situation, a signal below voltage V + varies at contact 28. As long as the voltage at the contact 28 is below the voltage V +, the base-emitter junction of the tran-30 resistor Q2 is biased in the blocking direction, and the transistors Q1 and Q2 are non-conductive.

The high voltage transient that appears at contact 28 causes the voltage at contact 28 to become more positive than V +. When the voltage difference between the contact 28 and the power supply terminal 35 is greater than the combined forward biased emitter voltages (VDT-) of the transistors Q2 and Q3, the transistor Q2 begins to conduct current to the collector. Conduction through the collector electrode of transistor Q2 provides conduction of the base current of transistor Q2. The conduction through the collector electrode of the transistor Q1, in turn, provides the carrier current of the transistor Q2, thus causing a high conductivity of the transistor Q2 and the transistor Q1. When the current supplied by the high voltage transient contact 28 to the power supply terminal 30 falls below the mini-holding current, the transistor switches to the inhibit state, which prevents the base current of the transistor Q1 and the protective silicon 10 becomes non-conductive. In this way, the energy of the high voltage transient that generates a positive voltage at the contact 28 is dissipated by conducting transistors Q1 and Q2 to the power supply terminal 30, thus protecting the utility circuit from damage.

Claims (6)

9 74166 A semiconductor protection circuit comprising - a semiconductor substrate (10), a semiconductor layer (12) of a first conductivity type (N) disposed on a semiconductor substrate (10), - a first (14) and a second (16) semiconductor region , which are of the second conductivity type (P), wherein both semiconductor regions (14, 16) are arranged in the semiconductor layer (12), - an emitter region (18) of the first conductivity type (N) formed in the second semiconductor region (16) ), the emitter region (18) being contacted by the first connecting conductor (26), characterized in that - the first connecting conductor (26) is connected to the operating voltage source connector (30), - the first semiconductor region (14) is contacted by the second connecting conductor (20). 24) and connected to a utility circuit to be protected by a connector (28), - a contact region (20) of the first conductivity type (N) spaced from the second semiconductor region (16) is arranged in the semiconductor layer (12), and 25 that - the contact area (20) is connected to the supply voltage source connector (30) by means of a first connection conductor (26). A semiconductor protection circuit according to claim 1, characterized in that it has a buried semiconductor region (11) of the first conductivity type, which has a low resistivity compared to the semiconductor layer (12) and is located below the first and second semiconductor regions (14, 16). 35 (12) and the semiconductor substrate (10). A semiconductor protection circuit according to claim 1 or 2, characterized in that it has a second region (32) of a conductivity type extending from the main surface opposite the semiconductor substrate (10) to the semiconductor substrate (10) and which surrounds the semiconductor layer (12). Semiconductor protection circuit according to one of Claims 1 to 3, characterized in that the semiconductor substrate (10) is silicon having P-type conductivity. Semiconductor protection circuit according to one of Claims 1 to 4, characterized in that the semiconductor layer (12) is an epitaxial layer with N-type conductivity. Semiconductor protection circuit according to one of Claims 1 to 5, characterized in that the contact region (20) is completely surrounded by a base region (38) of a second conductivity type which extends opposite the semiconductor substrate (10) of the semiconductor layer (12). from the main surface inside the semiconductor substrate that from the surface opposite the semiconductor substrate (10) of the semiconductor layer (12) extends into the semiconductor layer (12) 20 a first conductivity type collector region (36) bounding the base region (38) and (20,38,36) together with the connecting conductor (34) connecting the base (38) and collector regions (36) form a diode-connected transistor (Q3). 11,741 66