FI68489B - COPYING INSTRUCTIONS FOR AVAILABILITY AND INFORMATION FOR SIGNALING DATA VID AND PROGRAMSTYRD FOERMEDLINGSCENTRAL - Google Patents

Description

U ^ -1 Γα1 _ ANNOUNCEMENT 68489

patent application Offenlegungsschrift

c ^ 45) Patent filed 10 09 1935 PatGnt icoddcXfc ^ ^ '' (51) Kv.ik. "/ Int.a. * H 04 L 11/20 FINLAND —FINLAND (21) Patent application - Patentansökning 7923 ^ + 3 (22 ) Date of application - Ansökningsdag 26.07.79 (23) Starting date - Giltighetsdag 26.07.79 (• 41) Has become public - Blivit offentlig 23 01 80

National Board of Patents and Registration / 44 ^ Date of publication and publication on display— -,. QC gc

Patent and registration authorities Ansökan utlagd och utl.skriften publicerad j · o · o (32) (33) (31) Pyydetty etuoikeus — Begärd priority 27.07.78

Republic of Germany-Förbundsrepubl iken

Germany (DE) P 2833048.5 (71) Siemens Aktiengese11schaft, Berlin und Munchen, DE; Witte1sbacherp1atz 2, D-8000 Munchen 2, Federal Republic of Germany1ta-Förbundsrepub 1iken Tyskland (DE) (72) Eckhard Haensel, Munich, Vera-Marie Huttner, Munich, Robert Naessl, Kottgeisering, Peter Weidner, Munich, Derich

Germany-Förbundsrepubliken Tyskland (DE) (74) Berggren Oy Ab (54) Interconnection arrangement for the reception and transmission of information and signaling data in a program-controlled transmission center

The invention relates to a switching arrangement for transmitting multi-bit data between the supply lines supplying this data and the supply lines supplying this data via program-controlled communication devices, in which the signaling signals signal information to be transmitted.

A system is already known for transmitting and transmitting binary information signals transmitted by feeders to recipients in a data selection device with a central control device (DE patent publication 1 297 133) with a location-assigned central memory including the order between the feeders and the recipients. The central control device in question controls the transmission of state changes of the binary signals from the inputs to the recipients marked with binary codewords, wherein the central memory also contains all the information necessary for controlling the exchange. All the inputs are then connected to the central control device and the central memory via an input code transformer representing the first control device. In addition, all receivers are connected to the central control device and the central memory via an output code converter representing the second control device. In this known system, all information signals transmitted from the feeder, consisting of control signals and / or message signals, for the separation between control signals and message signals and for triggering the necessary control events are stored in a part of the main memory arranged for the feeder in question. The information signal obtained as a control signal is then input to an internal processing device, the input signal formed on the basis of the input of the control signal to the receiver in question is stored in a part of the main memory arranged for the feeder in question. All the information signals read from the main memory are then transmitted via the output code converter according to the codewords denoting the respective receiver in each case. This means a considerable strain on the central control device as a whole, since it has to carry out a corresponding number of editing cycles for the interpretation operations to be performed in each case, during the execution of which it is not normally available to perform other control functions.

It is now an object of the invention to provide a way in which, in a switching system of the type mentioned at the outset, the transmission center corresponding to the central control device of the known system described above can be effectively relieved of the load of signaling data determination and modification.

The above task is solved in such a switching order according to the invention, and the invention is characterized in that special monitoring circuits containing microprocessors receive all signaling information imported via 68489 supply lines certain bit combinations appearing in the signaling information received in the respective control circuit give the communication signals characteristic of these bit combinations to the communication device, which on this basis performs the necessary control events, and that the control connections only receive

The invention has the advantage over the known system under consideration that, in a relatively simple manner, the transmission center is effectively relieved of load by means of the distributed modification of the signaling data in question. Namely, the separation of the incoming data according to the information data representing the signaling data and the message data takes place under the control of the microprocessors in the individual monitoring circuits, whereby only the corresponding notification signal needs to be input to the switching center. In contrast, for the transmission of signaling information, the switching center only needs to transmit the corresponding operating signal to the respective control circuit in question, which microprocessor then causes the necessary control events and thus the transmission of the necessary signaling information. In this case, the use of a microprocessor in the respective monitoring circuit makes it possible to edit the incoming data very efficiently and to easily adapt to different conditions and to trigger the respective control events.

According to the purpose, I do not have a separate microprocessor for each monitoring circuit, by means of which the reception and transmission of all data transmitted or to be transmitted via the transmission lines of the monitoring circuit in question can be controlled. In this way, the monitoring circuit in question can be implemented with very little switching technical input.

A highly efficient switching arrangement is otherwise obtained when each microprocessor includes, in addition to the program memory, a data memory for receiving data input to the person concerned via data transmission lines transmitting data 4 68489 in the incoming transmission direction and a data memory capable of storing operation signals and data transmitted by the relay center. , via transmission lines transmitting data in the outgoing transmission direction. This results in a very efficient editing of the data transmitted or to be transmitted in different transmission directions.

A very simple organization of the control flow in the respective monitoring circuit is achieved when the microprocessor of the respective monitoring circuit can efficiently control the data on the incoming transmission lines at the pace of through transmission lines. Thus, in an advantageous manner, it is practically possible to compile the data or command signals present at any time for modification in the respective monitoring circuit in question. In this case, however, it is required that the operating speed of the microprocessor of the respective monitoring circuit in question is sufficiently high in relation to the data transmission speed of the data to be transmitted or to be transmitted.

It is further advantageous when each monitoring circuit includes a data processing circuit through which the data in question is transferred to or from the monitoring circuit in question and in which the data transmitted in the incoming transmission direction is released together with additional symbols transmitted with them (such as status bit, synchronization bit). Thus, only those data bits that contain the actual signaling information or message information can be input to the knockout connection and possibly to the relay center.

Suitably, in the data processing circuits, additional characters (such as, for example, sj nxronization bits) can be appended to the data transmitted from the respective monitoring circuit in question. Thus, the control circuits are free of additional signals that may interfere with their operation, which are not required for the actual signaling or message information, but which are nevertheless required for transmission control tasks.

5 68489

A very simple and reliable switching sequence is still achieved when all monitoring circuits are synchronously controlled via a common synchronous generator, as will be explained in more detail later. Thus, it is advantageously possible to use all the connections of the switching sequence according to the invention synchronously.

The invention is explained in more detail below with the aid of drawings by way of an exemplary embodiment.

Figure 1 shows a possible embodiment of a switching sequence according to the invention.

Figure 2 shows a closer structure of a monitoring circuit in the switching sequence of Figure 1.

The switching sequence shown in Fig. 1 consists mainly of a plurality of monitoring circuits formed by microcomputers MCI-MCn, which are practically connected between the data transmission lines transmitting data on the one hand and the data transmission lines EDS on the other hand. In this case, the EDS is, for example, the already known electronic data transmission system EDS, as already described in various sections (see, for example, "NTZ", 1973, booklet 7, pages 297-304, in particular p. 302).

Accordingly, in connection with the program-controlled relay center EDS illustrated in Fig. 1, it is accordingly assumed in the following that in this relay center information data comprising several bits, which are also called shells, are modified in each case. Each shell can then contain, for example, six or eight information bits and two additional bits, which, however, are not routed in the connection sequence shown in Fig. 1 with the information bits to the switching center EDS. These additional bits are the status bit and the synchronization bit. The information bits are stored - as is known from the EDS connection of the already described data transmission system - in a central memory belonging to this transmission system to be routed to a specific transmission line transmitting data in the outgoing transmission direction. In order to fulfill these relay instructions, the relay center or the data transmission system EDS needs the corresponding signaling information. Signaling information of this type is obtained from 6,648,889 signaling data, which, like word or information data, are derived via transmission lines transmitting data in the incoming transmission direction.

The transmission lines transmitting data in the incoming transmission direction and the data in the outgoing transmission direction are assembled into transmission line groups according to Fig. 1. Such an array of transmission lines includes, for example, transmission lines Z11 to Z1x transmitting data in the incoming transmission direction and transmission lines Al1 to Alx transmitting data in the outgoing transmission direction. The second group of transmission lines illustrated in Fig. 1 includes data transmission lines Zn1 -Znx transmitting data in the incoming transmission direction and transmission lines Ani - Anx transmitting data in the outgoing transmission direction. The arrangement can then be carried out in such a way that the transmission line group in question always includes the transmission lines connected to the signal transmission / signal reception device.

The already mentioned monitoring connections MCI-MCn are connected to the respective transmission lines via the connection connection SSA1-SSA and the data processing point EB1-EB. The connection connections SSA1 to SSA can then function in each case. The data processing points EB1 to EBn can then in each case act to release the data entered for them from the transmission lines transmitting data in the incoming transmission direction from the additional characters transmitted with this data. As additional symbols, this means additional bits and synchronization bits which, together with the information bits, are routed in the form of so-called shells to the data processing connections in question via transmission lines carrying data in the incoming transmission direction. The data processing connections EB1 to EBn in question are otherwise structured in such a way that they also allow the addition of additional characters, such as synchronization bits, to the data to be transmitted in each case. For this purpose, the data processing connections could, for example, be established with corresponding transfer registers. In this case, it is possible to proceed in such a way that, for the purpose of forwarding the bits of the respective transport register which receives the data transmitted in the incoming transmission direction, those additional bits are ignored, which include said additional bits. The transmission registers for the transmission of data in the outgoing transmission direction can be arranged in such a way that they contain additional characters or additional bits to be transmitted in each case in additional register stages.

68489 7

The monitoring connections MCI to MCn for each use of the array of transmission lines each include a microprocessor CPU which actually monitors the incoming data. We will return to this later. As shown in principle in Figure 1, the microprocessor CPU of the control circuit MCI is connected to a number of switching devices. These switching devices include a memory PROM, which acts mainly as a program memory for the microprocessor CPU. The switching devices in question further comprise a memory block RAM, which acts as a data and instruction memory of the microprocessor CPU. As will be seen, the data transferred between the relay center EDS and the transmission lines is routed through the RAM of this block of memory. Said switching devices further include the transmit / receive switches USART1 to USARTm. These transmission / reception connections are used to communicate with the transmission lines of the respective monitoring connection and, in particular, to the respective data processing connection and the associated connection connection. Said switching devices further include a so-called instruction buffer AP and a so-called notification buffer MP. The instruction buffer AP then receives the operating instructions issued by the relay center and notifies them to the relevant monitoring circuit. The notification buffer MP, on the other hand, then transmits the notification signals transmitted from the respective monitoring match to the switching center EDS, which can then carry out the necessary control operations.

This, too, will be explained in more detail at a later stage.

Fig. 1 further shows that the switching center or data transmission system EDS is connected to the control circuits MCI to the command flow control circuit BSt of the MC. This command flow control field can basically correspond to the throughput control in the communication system described above. This connection thus controls the transmission of data and instructions between the control connections and the relay center in time.

In connection with the switching sequence shown in Fig. 1, it should also be noted that the monitoring circuits MCI to MCn and the data processing circuits EB1 to EBn are in each case controlled from a common synchronous generator Tg.

This synchronous generator Tg can then transmit synchronous pulses at a repetition frequency corresponding to the repetition frequency at which the data occurs on the 8 68489 transmission lines. In this section, it should also be noted that the synchronous generator Tg can transmit synchronous pulses with possibly different synchronous pulse periods to the various monitoring circuits and their associated data processing circuits. This is especially the case when, as in practice, different control connections use transmission lines with different transmission speeds. In this case, the procedure is such that the transmission lines used by the monitoring circuit in question all belong to the same transmission speed class. Thus, for example, all transmission lines Z11 - Zlx and Ali - Alx may belong to the class of 2.4 kbit / s, and all transmission lines Znl - Znx and Ani - Anx may belong to the class of 9.6 kbit / s, for example. In this case, clock pulses at a pulse repetition frequency corresponding to four times the number of pulse repetition frequencies of the clock pulses applied to the control circuit MCI and the associated data processing circuit EB1 would be applied to the control circuit MCn and the associated data processing circuit EBn.

Fig. 2 shows in more detail the structure of the respective monitoring circuit according to Fig. 1. When it is only schematically illustrated for the MCI of the monitoring circuit shown in Fig. 1 that the microprocessor CPU of this monitoring circuit is connected to various switching devices of this monitoring device via a common line control system, it is shown in Fig. 2 that this common line system consists of three common line lines. In this case, on the other hand, it is an address common line AB, through which address signals are transmitted. On the other hand, it is a data link DB through which data is transmitted. In addition, a common control line SB is provided, through which control signals or control commands are transmitted. The microprocessor CPU is connected to the three common line lines by respective outputs, as shown in Fig. 2, the arrows marked on the respective terminals of the microprocessor CPU indicating possible transmission directions of addresses or data or control signals.

On the other hand, the transmission / reception connections USART1 to USARTm and their respective connections shown in Fig. 1 are now also connected to the above-mentioned common line lines. In addition, a control circuit marked DMA is connected to these three common line lines, which is connected on the input side to the output of the respective operating buffer AP.

68489 9 This control circuit DMA enables direct memory access to the data memory RAMI, which is connected via the address input Ael to the address common line AB and via the data interface Deal to the data connections DB. This memory RAMI together with the second data memory RAM2 forms a data block marked with RAM in Fig. 1. Both the data memories RAMI, RAM2 and the memory block RAM according to Fig. 1 are formed in each case by memories with non-selective access. The data memory RAM2 just mentioned is connected to the address common line AB by the address input Ae2, and the data memory RAM2 is connected to the data common line DB by the data connection De2. As indicated by the arrows marked in the respective connections of the data memory RAMI and RAM2, only addresses are entered in these memories at a time, while data is in each case entered and / or output. The data memory DAM2 is connected via the data output to the input of the notification buffer MP.

In addition to the switching points discussed above, the monitoring circuit MCI shown in more detail in Fig. 2 also has the program memory PROM already illustrated in Fig. 1, which may be a programmable or non-programmable read-only memory. This program memory PROM is connected by the address input Ae3 to the address common line AB, and by the data output interface Da3 the program memory PROM is connected to the data common line DB. With regard to the program memory PROM and both data memories RAMI and RAM2, it should also be mentioned that these are represented at each time by only one address input and data interface or data output interface; however, it should be noted that the memories in question are connected with the necessary number of connections to the common line lines in question.

In order for the respective monitoring circuit in question, such as the monitoring circuit MCI according to Fig. 2, to be able to operate, it is necessary to route control signals corresponding to the respective microprocessor CPU to separate control inputs. Figure 2 refers to two control inputs of this type; the second control input is labeled INT, and the second control input is labeled Reset. The control input INT - which in microprocessor terminology acts as an interrupt input - receives clock pulses from the clock generator Tg or a corresponding control circuit indicated in Fig. 1. These synchronous pulses then occur at the same repetition frequency at which the respective transmission lines have data signals or shells which must be modified by the switching sequence in question. If necessary, a trip signal “H” can be applied to the second input Reset of the microprocessor 10 68489 via the manual switch indicated in Fig. 2. Applying this signal causes the microprocessor to return to its starting position, from where it starts performing control operations again according to the included instruction counter.

The operation of the switching sequence according to the invention will be explained in more detail below. For this purpose, only events occurring in the MCI field are monitored. If it is now assumed that the microprocessor CPU has served exactly all the transmission lines connected to its respective control circuit MCI, then when the next synchronous pulse occurs at the input of the microprocessor CPU, the following events occur. As a result of the control just mentioned, the microprocessor CPU controls the program memory PROM, which then sets up the data for the microprocessor CPU indicating the individual switching devices to be queried. Based on this information, the microprocessor CPU can now, in a predetermined order, query the transmission lines transmitting information in the incoming transmission direction or the transmission / reception connections belonging to these transmission lines USART1 to USARTm for the existence of bit combinations that match the specified bit combination. In this case, signaling information may occur with bit combinations of this nature. Furthermore, the CPU of the microprocessor must, on the basis of its already mentioned control, query the control circuit for the existence of DMA information signals concerning the transmission of data in the outgoing transmission direction via transmission lines. In this case, it is possible to check in such a way that the data transmission lines transmitting data in the incoming transmission direction and in each case the respective operating instructions corresponding to the transmission lines transmitting data in the outgoing transmission direction are checked in the control circuit DMA. These monitoring or inspection operations must then be carried out at such a speed that all the wires connected to the relevant monitoring circuit MCI are used with certainty at the input INT of the microprocessor CPU until the next pulse occurs. In other words, during the occurrence of all the bits forming the shell, one of the transmission lines has to collect the data present on all the transmission lines or they form the shells, and specifically in both transmission directions.

68489 11

Since, as described above, a certain pre-processing of the signaling information takes place by means of the monitoring connections, separate control events are performed on the incoming transmission lines in order to identify the shells representing the signaling information. For example, if the microprocessor CPU determines that the data stored in the data memory RAM2 input from the incoming transmission line is signaling information, then it can pass through this memory a notification signal to the notification buffer MP, which characterizes the existence of a certain signaling state. To further illustrate the related events, assume, for example, that the presence of signaling information characterizing a particular signaling state exists when, for example, all signal bits of two or more consecutive shells are formed by a particular combination of bits. As a result of the transmission of this type of signaling information, the microprocessor CPU can then cause a short notification command to be sent to the relay center via said notification buffer MP.

In the second transmission direction, the microprocessor CPU may control the transmission of the necessary signaling information due to the corresponding input of the operation commands transmitted through the operation buffer AP from the relay center. However, in connection with this control, the microprocessor CPU is inefficiently controlled mainly via the control circuit DMa, so that this transmits a stop signal of the microprocessor CPU via the control common line SB. In this mode, the control circuit DMA transfers the necessary data to the RAMI, which is then taken by the microprocessor CPU - which is then restarted - to then control the transmission of the necessary signaling data via the outgoing transmission lines in question and the memory RAHI.

It has been explained above that by means of control connections in the connection sequence according to the invention remote signal pre-processing takes place to a certain extent, so that the relay center does not have to perform modification of signaling data - it is reception, evaluation and transmission. In this case, the relay center in question only needs to receive the data signals supplied to it from the incoming transmission lines and to pass such data signals to the outgoing transmission lines. However, these data signals then also arrive via the relevant monitoring circuit, without being subjected to processing, as was previously announced in connection with the signaling data.

12 68489

Finally, it should be further noted that in the drawings, the individual coupling parts are shown only in their functional interaction; no necessary power distribution devices or conventional separate synchronous control of the microprocessor are shown. As the microprocessor in the described case, practically every commercial microprocessor can be used, such as the Siemens microprocessors SAB8080 and SAB8085. The memories can likewise be formed from commercially available memory modules. The USART1 to USARTm transmitting / receiving switches are particularly suitable for modules sold under the designation SAB8251. The control circuit DMA can be formed from one or more modules, such as those sold under the designation SAB8257. The operation buffer AP and the notification buffer MP can in each case be formed from a number of modules sold under the designation MM67401.

Claims (5)

13 68489 1. A switching arrangement for transmitting multi-bit data in each case between the supply lines supplying this data and the supply lines supplying this data via program-controlled communication devices, in which signaling signals for program control , characterized in that special monitoring circuits (MC-MCs) containing microprocessors (CPUs) via the control of microprocessors (CPUs) receive all signaling data imported via supply lines (Z11-Z1x; Zn1-Znx) and monitor them in advance without forwarding them to the communication device (EDS) the presence of certain bit combinations that microprocessors (CPUs) when certain predetermined bit combinations occur in the respective control circuit (MC1-MCn) received in the signaling information, provide communication signals specific to these bit combinations to the communication device (EDS), which performs the necessary control operations based thereon, and that the monitoring circuits (MC1-MCn) provide input lines (All-Alx) exclusively when input task signals from the communication device (EDS); Anl-Anx). A switching arrangement according to claim 1, characterized in that each monitoring circuit (MC1-MCn) comprises only a single microprocessor (CPU), and that each microprocessor (CPU) comprises program memory (ROM), data memory (RAM2) for supply lines (Z11-Z1x); Zn1-Znx), and a data memory (RAMI) for task signals from the relay center (EDS) and data transmitted via receive lines (All-Alx; Anl-Anx). 14 68489 Switching arrangement according to Claim 1 or 2, characterized in that each microprocessor (CPU) senses all the supply lines (Z11-Z1x; Zn1-Znx) and generates task signals at the transmission rate determined by the supply lines (Z11-Z1x; Zn1-Znx). Coupling arrangement according to Claim 3, characterized in that all the monitoring circuits (MC1-MCn) are controlled by a common synchronization generator (Tg). Switching arrangement according to one of Claims 1 to 4, characterized in that each monitoring circuit (MC1-MCn) comprises a data processing circuit (EB1-EBn) which transfers the respective data to and from the respective monitoring circuit (MC1-MCn) and which releases the incoming data from the additional signals transmitted together with these (presence-status bit, synchronization bit) and appends additional symbols (e.g. synchronization bits) to the data given from the respective monitoring circuit (MC1-MCn).