JPH0455015B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to communication between exchanges, that is, an interface section between an exchange and a digital inter-office data line (hereinafter referred to as PCM link) in inter-office communication. In particular, the present invention relates to a control information detection method for sending control information to an exchange via a PCM link.

In a PCM switching network, in order to properly send and receive signals between exchanges via PCM links, control information for this needs to be provided to the exchanges via the PCM links. In order to ensure the normal transmission and reception of signals, it is important that the control information is supplied to the exchange without being influenced by disturbance factors that occur in the PCM link or the like that serves as the system for transmitting and receiving the control information. As a means to meet such demands, there is a circuit that protects received information and makes it useful for normal transmission and reception of signals.

[Conventional technology]

As a circuit for sending the above-mentioned control information to the exchange, there is a bit change detection processing circuit as shown in FIG. This circuit is a detection processing circuit 32 in an exchange as shown in FIG. In FIG. 3, 30 is a digital trunk (DT) [incoming trunk (ICT)], 31 is a network (NW), and 33 is a main controller (CC). The control information supplied bit-parallel to the detection processing circuit 32 is inserted into frames on PCM links #0, #1, etc. formed between stations, as shown in FIG. In the PCM30 system (a known system), a frame consists of 32 time slots (TS) as shown in FIG. 4, and each time slot is 8-bit serial. And the time slot
Different control information is inserted in TS0 and time slot TS16 in the same frame, respectively.
A control method is adopted in which the same control information is sent in consecutive frames.

And, with such a frame transmission method,
The digital trunk 32 that receives frames via the PCM link is configured as follows.
That is, for each frame, the control information of the time slot TS0 and the control information of the time slot TS16 are separated, and the above-mentioned information in successive frames (or frames spaced apart by a required number of frames, that is, frames giving the number of protections) is separated. The configuration is such that the same control information is output bit-parallel at the same time.

In this way, the 8-bit control information output from the digital trunk 32 in bit parallel is divided into two corresponding bits (for example, the first bit of time slot TS0 of the previous frame and the first bit of time slot TS0 of the subsequent frame). A predetermined number of exclusive OR circuits 1 ₁ , 1 ₂ , . . .
1 _N (N is 16 if the time slot has an 8-bit configuration), an OR circuit 2 whose inputs are connected to the outputs of these exclusive OR circuits,
It consists of a selector 3 which receives the output of this OR circuit as a selection control input and also receives as an input a predetermined input among the inputs to the exclusive OR circuits 1 ₁ , 1 ₂ , . . . _1N . A circuit configured in this manner is provided for each PCM link.

This bit change detection processing circuit detects a bit change in control information by comparing two bits of corresponding control information in successive frames (or frames separated by a predetermined number of frames that provide protection), and detects a bit change in control information according to the detection result. The control information of the previous frame or the control information of the subsequent frame is sent to the exchange. This makes it possible to avoid the influence of disturbances caused by PCM links, etc., and to reliably identify control information.

[Problem that the invention seeks to solve]

This conventional bit change detection processing circuit performs parallel bit processing as described above, and control information for multiple PCM links can only be sent to the exchange if a circuit with the same configuration is provided for each link. , it has become inevitable that the circuit scale and complexity required for arithmetic processing to generate the control information will increase.

For this reason, there is a need for technical means that can effectively solve this problem.

[Means for solving problems]

The present invention provides a control information detection method that is relatively simple and can generate control information for multiple links with a single means, and that means repeatedly transmits the same frame. In a signal transmission system that uses the above-mentioned signals, the system includes a separating means that sequentially separates and outputs only corresponding predetermined information units in each frame, and a separating means that holds the information units separated by the separating means and separates each information unit. an output means for sequentially outputting information to the output means; a detection means for detecting a discrepancy between successive information units in response to the information units output from the output means; and a selection output in response to the output of the detection means. a selection signal generating means that stops sending out the selected output in response to the completion of the detection process; and a selection means for outputting the selected input state, and the output of the selection means is sent out as normal information.

[Effect]

According to the method of the present invention, mismatches at the bit ends of data read out bit serially are sequentially detected, and depending on the detection output, the selection means selects the input state before the mismatch or the input state after the mismatch. Since the selected output is outputted as control information, the circuit scale can be reduced and simplified, and the method can be easily incorporated into time-sharing, so the control information processing of multiple PCM link frames can be simplified. It is possible to make do with one method.

〔Example〕

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the invention. This embodiment is also an example implemented in an exchange that receives frames bit-serially from the plurality of PCM links mentioned above, as described in the ``Prior Art'' section. In this figure, line 11 indicates [prior art]
Digital trunk 3 of each PCM explained in section
This line transmits bit-parallel control information separated by 0 in a time division manner. Sending control information to the line 11 in this time-sharing manner may be accomplished by providing a buffer in each digital trunk 30, or by providing a similar buffer to the input shown in FIG. 1 to produce the same operation. Good too. Bit-serial control information (hereinafter referred to as data) input via line 11 is sequentially stored in memory 11.
Read out bit serially and output. The output of the memory 10 is directly connected to one input of the exclusive OR circuit 13 and one input of the selector 14, and is also connected to the other input of the exclusive OR circuit 13 via a 1-bit delay circuit 15. It is connected to the other input of the selector 14 via a 1-bit delay circuit 16.

The output of the exclusive OR circuit 13 is connected to the set input S of the flip-flop circuit 17. The reset input R of the circuit 17 is arranged in such a way that a signal generated at the end of data processing is supplied via a line 18.

The output of the flip-flop circuit 17 is the selector 1
4 selection control inputs.

Next, the manner in which control signals are generated under the above configuration will be explained.

For convenience of explanation, it is assumed that the processing of the preceding data has been completed, a signal is generated on the line 18, and the flip-flop circuit 17 is in a reset state.

The bit-serial data from each PCM link is written bit-serially into the memory 10 via line 11, and the data bits read out bit-serially from the memory 10 are immediately sent to the exclusive OR circuit 13. It is supplied to one input, and after being delayed by 1 bit time by the 1-bit delay circuit 15, it is supplied to the other input of the exclusive OR circuit 13. Through such bit processing, a signal indicating whether or not there is a mismatch between successive bits is outputted from the circuit 13. That is, when there is a mismatch, there is an output from the circuit 13 and the flip-flop circuit 1
7 is set, and the set output is supplied to the selector 14.

In parallel with this, the data bits sequentially read out from the memory 10 are immediately supplied to one input of the selector 14 and also to the 1-bit delay circuit 16.
The signal is supplied to the other input of the selector 14 via.

Therefore, the bit input to the selector 14, that is, the input bit before the mismatch or the input bit after the mismatch, is selected and outputted by the selection signal from the flip-flop circuit 17 supplied to the selection control input of the selector 14. The selected output signal is supplied to an exchange (not shown) as control information.

By constructing such a circuit configuration, data from multiple PCM links is supplied to the input of the circuit configuration in a time-sharing manner, and a single PCM change detection processing circuit is shared by the multiple PCM links. It is also easy to configure it to do so.

Note that the circuit in the above embodiment is merely an example, and other circuit configurations may be adopted. For example, the exclusive OR circuit 13 may be configured to look up a table using the output from the memory 10 and the output from the 1-bit delay circuit and output the result.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to simplify the bit change detection processing circuit, and this simplification results in a configuration that can be easily shared for control information detection processing of multiple PCM links. You can get effects such as being tailored.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an embodiment of the present invention, Fig. 2 is a conventional bit change detection circuit diagram, Fig. 3 is a diagram showing the configuration of a conventional switch, and Fig. 4 is used in the switch shown in Fig. 3. FIG. 3 is a diagram showing the structure of a frame. In the figure, 10 is a memory, 13 is an exclusive OR circuit, 14 is a selector, 15 and 16 are 1-bit delay circuits, and 17 is a flip-flop circuit.

Claims (1)

[Scope of Claims] 1. In a signal transmission system that repeatedly transmits the same frame, there is provided a separating means for sequentially separating and outputting only corresponding predetermined information units in each frame; an output means for holding the separated information units and sequentially outputting each information unit; and a detection means for detecting a mismatch between successive information units in response to the information units output from the output means; selection signal generating means for generating a selection output in response to the output of the detection means and stopping sending out the selection output in response to the end of the detection process; and inputting the input state before the mismatch and the input state after the mismatch. an information detection method, comprising a selection means for outputting an input state corresponding to a selection output of the selection signal generation means, and transmitting the output of the selection means as normal information.