GB2072999A

GB2072999A - Controlling transfer of data into and out of a programme-controlled data switching centre

Info

Publication number: GB2072999A
Application number: GB8109618A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1980-03-28
Filing date: 1981-03-27
Publication date: 1981-10-07
Also published as: DE3012133C2; GB2072999B; ZA812069B; ATE9526T1; BR8101860A; EP0037074B1; DE3012133A1; EP0037074A1

Abstract

Data is transferred between transmission lines A11 to A1x, Z11 to Z1x and a switching centre EDS via a monitoring circuit MC1 which is one of a plurality MC1 to MCn utilised for handling respective transmission rates. Each monitoring circuit has a microprocessor CPU controlling emission to the switching centre of message signals MP determined by the signalling data received from the incoming lines Z11 to Z1x. This latter signalling data can be in any one of a plurality of formats X20, X70 but each message signal stored in store RAM corresponds to an item of signalling data in each of the formats. Emission of signalling data to the outgoing lines A11 to A1x is dependent on job commands AP from the switching centre, the monitoring circuit being arranged to emit the data in the appropriate format for the outgoing line. <IMAGE>

Description

1 GB 2 072 999 A 1

SPECIFICATION

Apparatus for, and method of, controlling transfer of data into and out of a programmecontrolled data switching centre This invention relates to apparatus for, and a method of, controlling transfer of data into and out of a programme-controlled data switching centre.

German specification No. 28 33 048 relates to a system employing such a method and apparatus in which corn m u ni cation data (i.e. data providing useful communication) and signalling data is transferred from incoming lines to the data switching centre using message signals and from the centre to outgoing lines using job commands.

In this known system all the items of signalling 80 data conveyed via the incoming (feeder) lines are received in monitoring circuits under the control of microprocessors forming parts of the respective monitoring circuits. Without being forwarded to the data switching centre the signalling data is 85 checked for specific predetermined data bit combinations. As a result of the establishment of specific predetermined bit combinations in the items of signalling data received in one of the monitoring circuits, message signals characteristic 90 of these bit combinations are then emitted by the microprocessors to the data switching centre so that, in the data switching centre, the requisite control procedures can be executed. Items of signalling data to be output via the outgoing 95 (trunk) lines are emitted from the monitoring circuits only in response to a supply of job commands from the data switching centre.

Although the above described measures do result in a reduction in the load on the data 100 switching centre as regards providing processing cycles which would otherwise be needed for determining and processing the items of signalling data, the effective reduction in load on the data switching centre is dependent upon the individual 105 monitoring circuits always being supplied with items of signalling data in one and the same signalling format. However this is not always possible, particularly in those cases in which, in the course of the development of the switching 110 services, such a data switching centre is connected to data transmitters/data receivers which must operate with different data transmission rates and signalling formats.

Although data transmitters/data receivers of 115 the same type (for example as regards the signalling format which is to be handled) could be restricted to being connected to a monitoring circuit which was designed only to detect items of signalling data in this signalling format this would 120 involve the emission of different forms of signalling data from the respective monitoring circuits which would result in the need for different operating programmes in the data switching centre in order to be able to run the control procedures needed as a result of the occurrence of the different message signals. This would again result in an undesirably high load on the data switching centre.

It is an aim of the invention to avoid at least to some extent such an increase in load on the data switching centre as regards the provision of data processing cycles in the event that the items of signalling data supplied to one and the same monitoring circuit or to various ones of the monitoring ci rcu its are in different signalling formats.

According to a first aspect of this invention there is provided apparatus for controlling transfer of data into and out of a program me-control led data switching centre serving incoming and outgoing lines, said apparatus including a plurality of monitoring circuits for connection to the incoming lines and outgoing lines and to a data switching centre, each monitoring circuit being arranged for receiving, from the data switching centre connection, job commands which cause the monitoring circuit to emit signalling data to the outgoing line connections, each monitoring circuit also being arranged for receiving, from the incoming line connections, signalling data in a plurality of signalling formats and being arranged for storing a plurality of different message signals each of which corresponds to a respective plurality of signalling data combinations in the respective signalling formats, the monitoring circuit being arranged to check signalling data from the incoming line connections for said signalling data combinations and to emit, to the data switching centre connection, the appropriate message signal on receiving one of the plurality of signalling data combinations corresponding to the message signal.

Preferably means are provided for emitting said message signals in response to signalling data combinations in only one signalling format and means are provided for converting signalling data received in other signalling formats into signalling data in said one signalling format.

Regardless of the signalling formats used, it seems to the data switching centre as if only one single signalling format is being used. Thus, for example, items of signalling data emitted in signalling formats X.20 and X.70 recommended by the CCITT can be handled by the data switching centre in the same manner as items of signalling data in signalling format X.2 1. In spite of the occurrence of items of signalling data in different signalling formats, the data switching centre is always supplied with predetermined message signals which are always processed by the data switching centre in the same manner.

Advantageously each monitoring circuit includes a respective microprocessor arranged, for controlling the input of all the signalling data and job commands into a store and for controlling the output of message signals characteristic of bit combinations of the incoming signalling data and of bit combinations of the outgoing signalling data 125 determined by the job commands.

In one embodiment the store is an allocation store which, when operated by incoming signalling data in various signalling formats or by job commands emits, in the first case, message signals assigned to the bit combinations of the relevant incoming signalling data and, in the second case, signalling data characteristic of the job commands and in a selected signalling format.

Conveniently the microprocessor of each of the 70 monitoring circuits is arranged to control, as regards the timing of data transmission rates which prevail on the incoming lines and on the outgoing lines, the interrogation of all the incoming lines and the analysis of job commands for the emission of data via the outgoing lines.

For this purpose a common clock pulse generator is provided for all the monitoring circuits and is arranged to emit clock pulses with a clock pulse frequency corresponding to the highest data 80 transmission rate to be used on the incoming and outgoing lines.

Storage space may be provided in each monitoring circuit for the reception and forwarding of items of communication data.

According to a second aspect of this invention there is provided a method of controlling transfer of data into and out of a program m e-control led data switching centre serving incoming and outgoing lines, said method including the steps of 90 receiving, from the data switching centre, job commands and, in dependence on the latter, emitting signalling data to the outgoing lines, receiving, from the incoming lines, signalling data in a plurality of signalling formats, storing a plurality of different message signals, each of which corresponds to a respective plurality of signalling data combinations in the respective signalling formats, checking the signalling data from the incoming lines for said signalling data combinations and emitting, to the data switching centre, the appropriate message signal on receiving one of the plurality of signalling data combinations corresponding to the message signal.

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which- Fig. 1 is a schematic block circuit diagram of a data switching system embodying the invention; 110 Fig. 2 is a block circuit diagram of a first specific embodiment of a monitoring circuit provided in the system shown in Fig. 11; and Fig. 3 is a block circuit diagram of a second specific embodiment of a monitoring circuit provided in the system shown in Fig. 1.

The system illustrated in Fig. 1 essentially consists of a number of rnv)nitoring circuits MC 1 to MCn which will be assumed to be formed by micro-computers which in practice are connected between on the one hand transmission lines some of which transmit data in the incoming transmission direction (referred to below as feeder lines) and some of which transmit data in the outgoing transmission direction (referred to below 125 as trunk lines), and on the other hand a programme-controlled data switching centre EDS.

This data switching centre EDS will be assumed to consist of a known electronic data switching centre EDS which is disclosed in various 130 GB 2 072 999 A 2 publications (see e.g. -Nachrichtentechnische Zeitschrift" 1973, Vol. 7, pages 297 to 304, especially page 302).

As regards the programme-controlled data switching centre EDS illustrated in Fig. 1, it will be assumed that in this switching centre data is to be processed both in the form of polarity changes and in the form of a plurality of bits which are also referred to as envelopes. Each envelope can contain, for example, six or eight communication bits and two additional bits; these additional bits are status bit and a synchronising bit. In so-called storage operation the communication bits can be stored in a central store assigned to the data switching centre EDS whereupon they are supplied to a specific trunk line. In order to be able to fulfil switching functions, and in fact both for switch-through operation and for storage operation, the data switching centre EDS requires items of signalling information. This sign?Iling information is obtained from signalling data which, in the same way as the communication data is supplied via feeder lines.

The feeder (incoming) lines and trunk (outgoing) lines are assembled to form groups of transmission lines. For example such a group of transmission lines comprises the feeder lines Z1 1 to Z1 x and the trunk lines A1 1 to A1 x. A further group of transmission lines illustrated in Fig. 1 comprises the feeder lines Zn 1 to Znx and the trunk lines An 'I to Anx. The arrangement could instead be such that the group of transmission lines in question contains transmission lines permanently connected to a signal transmitter/signal receiver arrangement. Otherwise the arrangement is assumed to be such that data signals are transmitted at one and the same data transmission rate via the transmission lines of a group of transmission lines. However items of signalling data can be transmitted at a different data transmission rate from that used for items of communication data.

The monitoring circuits MC1 to MCn are connected to their assigned transmission lines via interface circuits SSA1 to SSAn and data handling circuits EB 1 to EBn. The interface circuits SSA 1 to SSAn serve for signal level matching purposes. The data handling circuits EB1 to EBn each serve to remove from the data with which they are supplied via the feeder lines, additional signals which may be transmitted with said data. However, expediently this measure (i.e. removal of additional signals) is implemented only when. there is synchronous data transmission in which it is known at which points the additional signals occur. If, on the other hand, the data transmission is asynchronous in which case the positions of the additional signals within the transmitted data signals are unknown, expediently, within the data handling circuits, no signals are removed from the supplied signals. The additional signals will be assumed to represent additional bits and synchronising bits which are supplied together with the communication bits in the form of socalled envelopes via-the feeder lines to the data 3 handling circuits.

The data handling circuits EB 'I to EBn are assumed to be designed in such a manner that they permit the attachment of additional signals, buch as synchronising bits, to the data which is to be sent.

The monitoring circuits MC1 to MCn each provided for the control of a respective group of transmission lines each contain a microprocessor CPU which controls the actual monitoring of the incoming data. As illustrated in Fig. 1, the microprocessor CPU of the monitoring circuit MC1 is connected to a series of circuit units. These circuit units include a store PROM which serves as programme store for the microprocessor CPU. They also include a storage block RAM which serves as data and command store for the microprocessor CPU. The items of data to be transmitted between the data switching centre EDS and the transmission lines pass via this storage block RAM. The circuit units also include transmitting/receiving circuits USART1 to USARTm which will be assumed to be formed by commercially available, universally serviceable synchronously/asynchronously operable transmitting/receiving modules. In the present example these USART modules serve for the serial-to-parallel conversion of the data signals between the transmission line side and the data switching centre EDS.

In addition to the circuit unit the monitoring circuit MC1 also comprises a so-called job buffer AP and a message buffer M P. The job buffer AP serves to receive job commands emitted from the data switching centre EDS and to report these to the associated monitoring circuit. The message buffer MP serves to send message signals made available by the associated monitoring circuit to the data switching centre EDS which substantially executes requisite control procedures.

Fig. 1 indicates that the data switching centre EDS is connected to the monitoring circuits MC1 to MCn via a command sequence control circuit BSt. This command sequence control circuit will be assumed, in principle, to correspond to the switch-through control unit provided in the above considered known data switching centre. The function of this circuit is to control the timing of the transmission of data and commands between the monitoring circuits and the switching centre EDS.

In the system illustrated in Fig. 1 the monitoring circuits MC1 to MCn and the data handling circuits EB 'I to EBn are connected to a common clock pulse generator Tg. This clock pulse generator Tg emits clock pulses with a clock pulse frequency which is governed by the highest data transmission rate employed on the transmission lines. As the respective monitoring circuits are to be provided for the control of transmission lines assigned to various transmission speed classes, the transmission speed classes stand in a predetermined ratio to one another. Thus for example all the transmission lines Z1 1 to Z1x and A1 1 to Alx are assumed to belong to the speed130 GB 2 072 999 A 3 class of 2.4 kbit/sec, whereas all the transmission lines Znl to Znx and An'I to Anx are assumed to belong to the transmission speed class of for - example 9.6 kbit/sec. Thus in the monitoring circuit MC1 each data signal would be able to be determined four times since the clock pulses which codetermine the processing speed in the monitoring circuit MC 1 occur at four times the data transmission rate of 2.4 kbit/sec. At this point it should be additionally noted that conditions exist which correspond in full to the above mentioned conditions when a lower transmission rate is used for the transmission of items of signalling data than for the transmission of items of communication data. Thus it is readily possible to detect items of signalling data which occur at 200 bit/sec in the monitoring circuit. In this case each signalling data signal would be able to be sampled several times in order to be available for processing. Furthermore in this way it is relatively easy to synchronise the monitoring circuit to the data signals with which it is supplied, as will become more apparent below.

- Fig. 2 illustrates the possible construction of a first embodiment of one of the monitoring circuits to be used in the system shown in Fig. 1. This is a more detailed construction of the monitoring circuit MC1 already shown in Fig. 1. In accordance with Fig. 2 the microprocessor CPU of the 95, monitoring circuit MC1 is connected via a bus line arrangement to the various circuit units of this - monitoring circuit. In accordance with Fig. 2 this bus line arrangement comprises three bus lines, namely an address bus line AB, a data bus line D13, and a control bus line C13. Each of these bus lines comprises a plurality of individual lines, for example in each case eight individual lines.

The bus lines AB, DB, CB are connected on the one hand by means of appropriate terminals to the transmitting/receiving circuits USART1 to USARTm also shown in Fig. 1. Moreover the three bus lines are also connected to a direct memory access control circuit DMA. At its input this control circuit DMA is connected to the output of the associated job buffer AP and enables direct storage access to a data store RAM which is connected by means of an access control circuit Zst to the three bus lines AB, D13, C13. The data store RAM is a random access store.

In addition to the previously considered circuit components, the monitoring circuit MC1 illustrated in Fig. 2, also comprises the programme store PROM which has already been indicated in Fig. 1 and which will be assumed to be a programmable or non-prog ram m able read-only memory. This programme store PROM is connected by means of input and output terminals to the three bus lines. Under certain circumstances it may be adequate to connect the programme store PROM merely by one control input to a control line of the control bus line C13. This also applies to the store control circuit Zst of the data store RAM.

The three bus lines are also connected to the input of the message buffer MP already indicated 4 GB 2 072 999 A 4 in Fig. 1. This message buffer MP can likewise be connected via one single control input to one single control line of the control bus line C13.

To enable the monitoring circuit MC 1 to operate it is necessary to supply control inputs of the microprocessor CPU in question with control signals. Fig. 2 indicates two such control inputs; one control input consists of an interrupt input INT, whereas the other consists of a reset input Reset. The control input INT receives clock pulses 75 from the clock pulse generator Tg indicated in Fig. 1 so that these clock pulses occur with a repetition frequency which is determined by the highest data transmission rate employed on the transmission lines (e.g. 9.6 kbit/sec). The other control input Reset of the microprocessor CPU can be supplied as and when required with a trigger signal---1 - via a manually operable switch indicated in Fig. 2. The supply of this signal causes the microprocessor CPU to return to its starting 85 state from which it recommences the execution of control processes in accordance with a command counter which it contains.

The mode of operation of the data switching system will now be explained by reference to the processes which take place in the monitoring circuit MC1. If it is assumed that the microprocessor CPU has operated all the transmission lines connected to its associated monitoring circuit MC1, on the occurrence of the next clock pulse at the control input INT of the microprocessor CPU, the following procedures take place. When thus triggered, the microprocessor CPU selects the programme store PROM which in turn makes available to the microprocessor CPU the data indicating the individual circuit units which are to be interrogated. On the basis of this data the microprocessor CPU now interrogrates, in a predetermined sequence, the assigned transmitting/receiving circuits USART1 to USARTM connected to feeder lines, in order to determine (during signalling format conversion as described below) the occurrence of predetermined bit combinations. In the present example it is assumed that items of signalling data occur as these predetermined bit combinations.

Furthermore when triggered as described above, the microprocessor CPU interrogates the control circuit DMA for the presence of communication signals which relate to the transmission of data via the associated trunk lines. In this case it is possible to proceed in such manner that interrogation processes relating to a feeder line and relating to a trunk line are executed 120 alternately, and, in the latter case, for each trunk line the existence of job commands in the control circuit DMA is checked. The monitoring or checking processes are carried out at a speed such as to ensure that by the time of the occurrence of the next pulse at the control input 1 NT of the microprocessor CPU all those transmission lines connected to the monitoring circuit MC1 have been serviced. Thus during the occurrence of each of the bits which form an envelope on one of the transmission lines, the data occurring on all the transmission lines (or the envelopes forming the data) is detected in both transmission directions.

In contrast to the arrangement described in German specification No. 28 33 048, the monitoring circuits used in this embodiment now permit a preliminary processing of the items of signalling data received in different signalling formats. In the course of different data transmissions via the data switching centre EDS it is possible to use different signalling formats, as recommended by the CCITT. One such signalling format will be assumed to be that corresponding to X.20, and another such will be assumed to be the signalling format corresponding to X.70. These signalling formats differ in respect of the sequence and length of the individual items of signalling data, which are to trigger specific switching processes. Since description of the structures of the items of signalling data of the various signalling formats does not appear to be necessary as regards the explanation of the present invention, the various signalling formats will not be discussed further. However, it should be noted that the various signalling formats may also include the use of different transmission rates for the signalling data in question.

When the monitoring circuit MC1 indicated in Fig. 2 is used, the items of signalling data in the various signalling formats are input into the data store RAM and in fact into respective storage zones of that store assigned to the signalling formats in question. Thus the items of signalling data in signalling format X.20 are input into zone X.20 of the data store RAM, and the items of signalling data in signalling format X.70 are input into zone X.70 of the data store RAM. For this purpose the access control circuit Zst of the data store RAM is supplied both with addresses which facilitate the input of the signalling data into the storage zone in question and with control signals from the associated microprocessor CPU. For this purpose the microprocessor CPU must have previously acquired items of information indicating the signalling format in which the items of signalling data occur. These items of information which are only needed when signalling data can occur in different signalling formats - can be emitted for example at the beginning of each data signal transmission by a data signal transmitter connected to one of the feeder lines.

As a result of the input of the items of signalling data in the relevant signalling format into a predetermined zone of the data store RAM, under the control of the associated microprocessqr CPU a conversion is effected resulting in the acquisition of items of signalling data (in a format X.2 1) which correspond to the relevant signalling data and which can be used in the further operation of the data store RAM. The associations between the items of signalling data in the various signalling formats can be stored for example in internal registers of the microprocessor CPU or in the programme store PROM. Here one can proceed in 1 such manner that following. the read-out of the items of signalling data (in signalling format X.20 or X.70) which have been stored in the data store RAM, the data store RAM is supplied with items of signalling data in the signalling format X.21 on the occurrence of which message signals are emitted from the data store RAM to the message buffer MP. For this purpose it will be necessary to address, in the data store RAM, a storage zone M/A which stores bit combinations which represent message signals and which are assigned to the items of signalling data in signalling format X.2 1.

The circuit shown in Fig. 2 is not only able to emit message signals in response to the occurrence of items of signalling data with which it is supplied, but it is also able to emit items of signalling data in response to job commands with which it is supplied. If, in the course of the interrogation of the control circuit DMA, it is 85 established that a job command for the emission of items of signalling data is present, as a result of the readout of this job command from the control circuit DMA, with the co-operation of the microprocessor CPU, the zone M/A of the data 90 store RAM is operated. As a result of this operation the items of signalling data in signalling format X.21 and which are assigned to the job command in question can be read out from the data store RAM. Then, with the co-operation of the microprocessor CPU and the programme store PROM, these items of signalling data are converted into signalling data in the signalling format (X.20 or X.70) in which the items of signalling data are to be transmitted via a trunk line. For this purpose, when the signalling data in the signalling format X.21 is available, the associated microprocessor CPU actuates that storage zone of the data store RAM which contains the items of signalling data which 105 correspond to the X.21 signalling data and which are assigned to the desired other signalling format (X.20 or X.70). These items of signalling data in the desired other signalling format are then read out from the data store RAM and emitted via the appropriate addressed transmitting/receiving circuit USART1 or USARTm.

In the course of the procedures described above, for each signal transmission, the microprocessor CPU will make available the address of the unit emitting a signal and of the unit receiving the signal in question. As known in association with microprocessors, here the procedure is such that the actuation or addressing of a unit from which signals may need to be obtained, results in the production of an item of address and control information which indicates where the signals in question are to be transmitted to.

As regards the monitoring circuit illustrated in 125 Fig. 2, a brief reference will again be made to the data store RAM. In addition to the aforementioned storage zones, this data store RAM also comprises a storage zone D. This storage zone D serves to provide intermediate storage for signals which are 130 GB 2 072 999 A 5 not subject to processing in the relevant monitoring circuit. This data consists in particular of items of communication data which are to be transmitted from a feeder line to a trunk line. This transmission can be effected in accordance with the switch-through principle or in accordance with the storage principle by means of which the data in question are intermediately stored in the data switching centre EDS indicated in Fig. 1. In the case of the monitoring circuit illustrated in Fig. 2 the data in question is likewise emitted via the associated message buffer MP and in fact either to the job buffer AP of the same monitoring circuit or to the job buffer of another of the monitoring circuits (depending upon which of the monitoring circuits is connected to the desired trunk line). Now the data transmission in question is carried out only during storage operation via the central store of the data switching centre EDS, whereas in the case of switch-through operation the message buffer in question and the job buffer in question are, as it were, directly connected to one another.

Now the construction and the mode of operation of the circuit illustratedin Fig. 3 will be considered in detail. This circuit represents a further embodiment of the monitoring circuit MC l shown in Fig. 1. In contrast to the embodiment illustrated in Fig. 2, the monitoring circuit illustrated in Fig. 3 comprises two data stores RAM 1 and RAM2. The data store RAM 1 possesses three different storage zones X.20, X.70 and M/A. These storage zones of the data store RAM 1 can be selectively operated at the input side and in fact via AND-gates, only one of which has been indicated in respect of each storage zone. These are the AND-gates G 1, G2 and G3. Of these AND-gates, the two AND-gates G1 and G2 each have one input connected to a respective output of bistable trigger elements FF 'I and FF2 which have their setting inputs S connected to separate outputs of a decoder DEC1 and which have their resetting inputs R connected to a common output of this decoder DEC1. A further output ' of the decoder DEC 1 is connected to an input of the AND-gate G3. The AND-gate G3 has a further input connected to the control bus line C13. The AND-gates G 1 and G2 have their other inputs connected in common to the data bus line D13.

At the output side the two storage zones X.20 and X.70 of the data store RAM are connected to the data bus line DB via selectively operable ANDgates. In the present example only two of these AND-gates have been shown, namely AND-gates G4 and G5 which have first inputs relatively connected to outputs of the two storage zones X.70 and X.20 of the data store RAM 1, and which have other inputs connected to respective outputs of two bistable trigger elements FF3, FF4. These bistable trigger elements FF3, FF4 have their setting inputs S connected to separate outputs of a decoder DEC2 and have their resetting inputs R connected to a common output of this decoder DEC2. This decoder DEC2 is connected, in the same way as the decoder DEC1, to the control bus 6 GB 2 072 999 A 6 line CB and to the address bus line AB. The decoders in question could also be formed by a single decoder.

The storage zone M/A of the data store RAM 1 has its output connected to the input side of the message buffer MP. The input side of this message buffer MP is also connected to separate outputs of the second data store RAM2 which is also connected to the three bus lines AB, DB and C13.

With the exception of the circuit portion described above, the circuit illustrated in Fig. 3 is fully identical to that shown in Fig. 2. This relates to the connection of the job buffer AP to the control circuit DMA and to the connection between the microprocessor CPU, the programme store PROM, the transmitting/receiving circuits USART1 to USARTm and the control circuit DMA.

In contrast to the circuit illustrated in Fig. 2, the circuit illustrated in Fig. 3 operates in a somewhat different manner. This is mainly connected with the organisation of the data store RAM 1. If it is assumed, for example, that the items of signalling data which are to be processed and which are supplied to the monitoring circuit via any one of the associated feeder lines are in signalling format X.20, the following processes take place. Firstly the decoder DEC1 is addressed from the microprocessor CPU in order to set the bistable trigger element FF1. In this way the items of signalling data in question can be input into the storage zone X.20 of the data store RAM 1 via the input AND-gates (which are represented by the AN D-gate G 1). This data store RAM 1 is a so called allocation store which, in response to the reception of items of signalling data in the predetermined signalling format, is able to emit the message signals associated with these items of signalling data from the output side of its storage zone M/A. Thus in response to the 105 reception of items of signalling data A in signalling format X.20, the data store RAM 1 will be assumed to emit from its output a message signal S 'I which is supplied to the message buffer MP. If, on the other hand. the signalling format X.70 has been selected, the message signal S1 in question is emitted in response to the reception of items of signalling data a + b. Further associations between the signalling data and the message signals are indicated in the data store RAM 1 shown in Fig. 3. In accordance with these associations, message signals S2, S3, Sn are emitted as a result of the occurrence of data signals B, C + D, Z in signalling format X.20 or in response to the occurrence of signalling data c, d + e and z in signalling format X.70.

The data store RAM 'I is also used to emit desired items of signalling data in response to the detection of job commands. For this purpose the job commands are fed to the storage zone M/A of the data store RAM l via the input AND-gates which are arranged to be in the transmitting state (and which are represented by the AND-gate G3).

Following the supply of these job commands - which will be assumed to conform with the signals S 1 to Sn entered in the storage zone M/A -the data store RAM 1 makes available at its output the items of signalling data in signalling formats X.20 and X.70 at respective outputs. Depending upon.

the signalling format in which the items of signalling data are to be emitted, the output ANDgates represented by AND-gate G4 or AND-gate G5 are transmissive in order to emit the appropriate items of signalling data via the data bus line DB to the relevant transmitting/receiving circuit USART1 to USARTm.

Those data signals which are not to be subjected to evaluation or processing in the monitoring circuit MC1 shown in Fig. 3 are intermediately stored in the data store RAM2 which thus fulfils the function of the storage zone D in the circuit arrangement illustrated in Fig. 2.

As regards the circuits illustrated in Fig. 2 and 3, it is again pointed out that where operated by the associated microprocessor CPU, thezcontrol circuits DMA provided for direct store access become operative in order to input the signals which represent job commands (supplied via the associated job buffer AP) into the appropriate data store, and at the same time to bring the associated microprocessor into the inactive state for the duration of this input procedure. The microprocessor then reassumes the control functions following the execution of the input storage procedure. The associated control procedures need not be discussed in detail as these correspond in full to the control procedures which take place in the normal operation of DMA modules and microprocessors.

As already mentioned above it is possible to synchronise the operation of the individual monitoring circuits as it were to the data signals supplied to the latter, with regard to which it is initially unknown in which phase state occur the bit groups or envelopes containing the data signals relative to the time of processing of these signals in the monitoring circuit. As the provided clock pulse generator Tg emits clock pulses with a clock pulse frequency determined by the highest data transmission rate used on the transmission lines, each of the items of signalling data which occur with a co.rnparatively lower clock pulse frequency can be detected several times in the relevant monitoring circuit under clock pulse control. If it is assumed for example that each such signalling data signal can be detected twenty times under clock pulse control, expediently the tenth sampling of each such signalling data signal is detected. This process which can be considered as a synchronisation process merely requires to be effected in respect of the first occurring signalling data signal as the following signal being data signals can be precisely detected as a result of the predetermined transmission frequency. If, for example, the first signalling data signal occurs as a binary signal---1--which is followed by a binary signal -0-, on the basis of the number of determined " 1---sampling pulses for the first signalling data signal, it is possible to accurately determine the sampling pulse with which all the 7 following data signals are to be sampled. This function can also be undertaken by the microprocessor CPU of the monitoring circuit.

Finally it should also be noted that in the drawings the individual circuit units have been represented merely as regards their functional co70 operation; the required current supply devices and the normally provided separate clock pulse control unit of the individual circuit units have not been shown. In the present example the microprocessor can in practice consist of any commercially 75 available microprocessor, such as for example microprocessors bearing the designation 8085 manufactured by Intel. The stores can likewise consist of commercially available storage modules. The transmitting/receiving circuits 80 USART1 to USARTm which fundamentally serve for parallel-series conversion can be formed by USART modules bearing the designation 8251 manufactured by Intel. Preferably a DMA module bearing the designation 8257 manufactured by 85 Intel is suitable as control circuit DMA. The job buffers can be formed by storage modules bearing designation MM67401. The AND-gates used in the embodiment shown in Fig. 3 can be formed by so-called tristate logic-linking elements which are 90 readily commercially available as are the bistable trigger elements and the decoders used in this embodiment.

The arrangements described above involve the advantage that it is ensured, in a relatively simple manner, that in spite of the occurrence of items of signalling data in different signalling formats, the data switching centre requires only one operating programme in order to be able to process message signals emitted by the monitoring 100 circuits in response to reception of the signalling data.

Claims

1. Apparatus for controlling transfer of data into 105 and out of a programme-controiled data switching centre serving incoming and outgoing lines, said apparatus including a plurality of monitoring circuits for connection to the incoming lines and outgoing lines and to a data switching centre, 110 each monitoring circuit being arranged for receiving from the data switching centre connection, job commands which cause the monitoring circuit to emit signalling data to the outgoing line connections, each monitoring circuit 115 also being arranged for receiving, from the - incoming line connections, signalling data in a plurality of signalling formats and being arranged for storing a plurality of different message signals each of which corresponds to a respective plurality 120 of signalling data combinations in the respective signalling formats, the monitoring circuit being arranged to check signalling data from the incoming line connections for said signalling data combinations and to emit, to the data switching 125 centre connection, the appropriate message signal on receiving one of the plurality of signalling data combinations corresponding to the message signal.

GB

2 072 999 A 7 2. Apparatus according to claim 1 wherein means are provided for emitting said message signals in response to signalling data combinations in only one signalling format and means are provided for converting signalling data received in other signalling formats into signalling data in said one signalling format.

3. Apparatus according to claim 1 or claim 2 wherein each monitoring circuit includes a respective microprocessor arranged for controlling the input of all the signalling data and job commands into a store and for controlling the output of message signals characteristic of bit combinations of the incoming signalling data and of bit combinations of the outgoing signalling data determined by the job commands.

4. Apparatus according to claim 3 wherein the store is an allocation store which, when operated by incoming signalling data in various signalling formats or by job command emits, in the first case, message signals assigned to the bit combinations of the relevant incoming signalling data and, in the second case, signalling data characteristic of the job commands and in a selected signalling format.

5. Apparatus according to claim 3 or claim 4 wherein the microprocessor of each of the monitoring circuits is arranged to control, as regards the timing of data transmission rates which prevail on the incoming lines and on the outgoing lines, the interrogation of all the incoming lines and the analysis of job commands for the emission of data via the outgoing lines.

6. Apparatus according to claim 5 wherein a common clock pulse generator is provided for all the monitoring circuits and is arranged to emit clock pulses with a clock pulse frequency corresponding to the highest data transmission rate to be used on the incoming and outgoing lines.

7. Apparatus according to any one of the preceding claims wherein in each monitoring circuit storage space is provided for the reception and forwarding of items of communication data.

8. Apparatus for controlling transfer of data into and out of a program me-control led data switching centre serving incoming and outgoing lines, said apparatus being substantially as described herein with reference to Fig. 2 or Fig. 3 of the accompanying drawings.

9. A data switching system including apparatus according to any one of the preceding claims connected to incoming and outgoing lines and a data switching centre.

10. A data switching system substantially as described herein with reference to Figs. 1 and 2 or Figs. 1 and 3 of the accompanying drawings.

11. A method of controlling transfer of data into and out of a programmecontrolled data switching centre serving incoming and outgoing lines, said method including the steps of receiving, from the data switching centre, job commands and, in dependence on the latter, emitting signalling data to the outgoing lines, receiving, from the incoming lines, signalling data in a plurality of signalling formats, storing a plurality of different message 8 GB 2 072 999 A 8 signals, each of which corresponds to a respective plurality of signalling data combinations in the respective signalling formats, checking the signalling data from the incoming lines for said signalling data combinations and emitting, to the data switching centre, the appropriate message signal on receiving one of the plurality of signalling data combinations corresponding to the message signal.

12. A method according to claim 11 wherein message signals are emitted in response to signalling data combinations in only one signalling format and signalling data received in other signalling formats is converted into signalling data in said one signalling format.

13. A method of controlling transfer of data into and out of a programmecontrolled data switching centre serving incoming and outgoing lines, said method being substantially as described heFein with reference to Figs. 1 and 2 or to Figs. 1 and 3 of the accompanying drawings.

Printed for Her Majesty's Stationery Office by the Courier Press, Leamington Spa, 1981. Published by the Patent Office, 25 Southampton Buildings. London, WC2A lAY, from which copies may be obtained.