FI59189C - ANORDINATION FOR THE CONSTRUCTION OF THE CONNECTION OF OVERCOMES AND PROGRAMSTYRD DATAFOERMEDLINGSANORDNING - Google Patents

Description

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Patent · och ragitterstyralMn '' AmMcm utiagd och utUkrHtwi pubUcund 27.02.81 (32) (33) (31) Pyydttty ttuoiktu * - «tgird priority 29.08.73

Federal Republic of Germany-Förbundsrepubliken Tyskland (DE) P 23 ^ 3586.1 (71) Siemens Aktiengesellschaft, Berlin / Munchen, DE; Wittelsbacherplatz 2, D-8000 Miinchen 2, Federal Republic of Germany-Förbundsrepubliken Tyskland (DE) (72) Gerhard Jaskulke, Dachau, Alois Schwarz, Munich, Annin Rutter, Unter-Pfaffenhofen, Germany Federal Republic of Germany (Förbiiyskep) The present invention relates to an apparatus for monitoring and error diagnosis in the field with verification programs for error diagnosis.

In a program-controlled communication device, incoming and outgoing connections, for example wires, are connected to the processing unit. This processing unit, hereinafter referred to as the line interface unit, enables cyclic communication with the central units of the plant. An integral part of the central unit is the central memory unit, which contains all the information necessary for the execution of relay tasks and backup transactions.

The line interface unit, as a connecting element between the incoming and outgoing interfaces and the central parts of the relay device, comprises the respective connection connections for the interfaces, these identify input and output transducers and at least one transmission function control element through which data communication is transmitted between the line interface and the central interface.

The structure of the cable interface unit is described in detail in German application publication 19 9 6 389 with regard to interface connections and input and output code converters. Therefore, only the essential features of the mode of operation are repeated here.

When information appears in one of the connected lines, e.g. in the form of a polarity reversal, a period requirement is generated in the connection circuit arranged for this line. At the same time, the requesting interface circuit is identified by means of an input transducer. The transfer of the cycle requirement to the central memory unit is performed in the transfer function control member. The interface connection addresses indicated in the input code converter and coded accordingly are used to achieve an input cell defined in the central memory unit and permanently arranged for this interface connection. This includes all other information necessary to process the information present. Thus, for example, the address of a particular interface connection is available by reading the input cell, with which this interface circuit is identified via the output code converter. Information, such as a new polarity reversal, is then applied to the line connected to this connection.

However, in the case of a connection that is not yet switched through, then the information present in one of the interfaces initiates a series of functions which result in the present information being evaluated as an invitation criterion and corresponding mediation reactions (switching reactions) being provided. This is controlled by certain programs, the costs of which lead to the timely generation and transmission of information and the correct evaluation of the information received in time.

It is known from German patent publication 2,109,318 to write in the input cells, in a program-controlled manner, criteria which are read by the control element of the transmission functions of the line interface unit during one period of the input cell and which are identified for processing the information present. In this way, it can be determined very quickly whether the incoming information must be passed on to the outgoing connection line or placed in a specific memory area of the central memory unit. Such a memory area is, for example, the so-called notepad memory, which is emptied by the program control unit 3 59189 at certain intervals.

It is also known from this patent publication, under the control of a program control unit, to place instructions in another memory area of the central memory unit. This memory area, the so-called notepad memory, is emptied at regular intervals by the function controller.

In this context, the second measure is described in German application 2 131 ^^ 9. This is based on the fact that at least the information provided for the address of the central memory unit is cached in the control function of the transfer operations. This purpose is served by the so-called section buffer memory. After the information obtained from the assigned memory area is extracted, these are tested in the evaluation circuit. Depending on the evaluation of the given memory data, it is then determined whether the period just completed must be followed by others, i. whether further processing is necessary or not. If it is found that the information on the basis of which this first section was clarified only needs to be provided, to the predetermined interface connection, then no further action is required. However, if it is determined that other events are required, then · provide the relevant information in the available period buffer memory. In this case, the cached data is taken to the second buffer of the control element of the transfer functions, the so-called page section in a buffer memory. From here, they are available for further processing as needed. For this purpose, a cycle request is given from the page cycle buffer memory in a manner known per se. The data in the page buffer memory is fed through the output register of the transfer operation control member to the memory and likewise again to the cycle buffer memory. This event may occur when the read memory data again requires further processing of this information.

A very essential requirement for program-controlled data transmission hardware is the requirement for continuous availability. Using a well-known principle, availability is increased by a modular structure. Another measure that improves availability is based on exporting defined function states to private units in the system. The proposal to put private plant parts 4 59189 in operation, test mode and absence is described in German application publication 2 14b 981. Private parts of the plant are equipped for this purpose, such as comparators or fault-detection circuits. The establishment of these conditions allows suitable backup programs to locate and diagnose faulty units by utilizing faultlessly functioning parts of the plant without being affected by the faulty unit.

When these principles are used in a wire interface unit, it means that there are at least two control elements for the transmission functions and that they both operate in parallel and synchronously. Thus, the reference switches can be used to identify malfunctions, so that in the event of a malfunction of one transmission function control element, it becomes possible to maintain operation with another, functional transmission function control element unrestricted.

Figure 1 illustrates a plant in which the line interface unit LE includes two identically constructed and parallel transmission function control elements UEAS1 and UEAS2, which co-operate with two identically constructed memory units SEI and SE2.

Each of the control elements UEAS1 and UEAS2 of the transmission functions includes data input and output devices DE and DA, to which input and output code converters ECW and ACW are connected. In the direction of the memory units are the registers SSAR, AdAR and WAR. The SSAR register outputs the information necessary for the use of the memory units, such as information on memory selection, memory operation code, memory operation method, etc. A memory address is output via the AdAR register and a memory word via the WAR warning. To receive a read memory word, there is a word input register WER. In addition to the information lines, the plant also has several control lines, of which only the lines for the transmission of the signals PSS, PVS and PVS are shown here. Details of this are explained below.

The reference circuits VG in the memory units SEI and SE2 and in the input and output transducers ECW and ACW monitor the synchronous operation of the transmission function control elements UEAS1 and UEAS2. In addition, the transmission function control means UEAS1 and UEAS2 have error detection circuits which, in the event of an error, give an error signal PA.

5 59189

As is known per se, after the error is detected, the backup programs are activated, i.e. positioning and diagnostic programs that limit the error and determine the faulty unit, e.g., faulty connection. In this case, the relevant test function control element can take the described test mode.

The present invention addresses the problem of how to increase the usability of a cable ballast unit in such a program-controlled data transmission facility. For this purpose, the following conditions are assumed: 1. Errors that are relevant to the control functions of the transfer functions are identified by individual error detection connections; 2. A malfunctioning transmission control device can be prevented from failing to function properly with the units by providing a defined test mode.

3. The diagnosis of the control element of the malfunctioning function or of the parts inside such a body shall be made by means of verification programs; thus, guided functions locate errors quickly and accurately.

The object of the present invention is to support the execution of backup programs by means of additional connections in the control means of the transmission functions.

In this connection, it is seen as one of the objects of the invention that an accurate description of the error occurring is formed in the control element of the transfer functions.

An additional goal is that all achievable data (data) and information that is decisive for the use of the control function of the transfer functions are included in the diagnosis as widely as possible also for the periods already elucidated.

Finally, one of the objects of the invention for program-controlled error detection is to contact the essential functions in the control function of the transfer functions and to keep a record of the results.

To solve these tasks, the invention is characterized in that each transmission function control member of the line interface unit has an error collecting device for receiving individual error signals, therefore and for generating an error word describing errors and error response signals. adapted to be sent to the central memory units, that a diagnostic routine device is further adapted to receive and interpret the error response signal belonging to the second group in the central memory unit, to interpret the diagnostic command EKSI with the transfer functions of the control member is between the switched data paths from the other side of the word output register and on the other side of the sa natulorekisterin, containing the error accumulation device error word error word register and the transfer functions of the control member intermediate storing section of the buffer memory that a diagnosis routine unit comprises activating with a further first control signal of the second tulkitsemiskytkennän to sense the diagnosis command Env-Koyasan produce second control signals, and that the control connections and registers of the transfer function control element with each of these other control signals are always connectable to the word input register for receiving the diagnostic command.

An essential advantage of such a system is that not only the contents of all output registers but also the contents of the interim storage period buffer memory can be programmed into the memory unit.

By using an error register in which a separate error rate step is arranged for individual errors, it is possible to generate an error word. Thus, very accurate information about the error is available.

The error word can also be transferred to the memory unit in a program-controlled manner. It is further advantageous, in a program-controlled manner, to include data input and output devices in the diagnosis, including the registers, control means and wires belonging thereto. the information loop.

Finally, the device also offers the possibility to subject all devices of the control function of the transfer functions to functional testing, so that the error occurring on the basis of several data can be expressed very quickly and accurately by evaluating the recorded results of private functional tests.

The invention is explained below in connection with the accompanying drawings.

7 59189

Figure 2 shows, in the form of a block diagram, the most essential parts of the control element of the transmission functions inside one line connection unit.

Figures 3 and 2 show details for generating an error word.

Figure 5 shows an example of switching the input-output transducer on and off in one transmission function control element.

Figure 6 shows a diagram of a diagnostic command.

Figure 7 shows some events in the control of the transfer functions in the form of a block diagram for the diagnosis of errors.

Figure 2 shows only one transmission function control element UEAS with the details necessary for understanding the invention. In the practical implementation, it is self-evident, as shown in Figure 1, that a second, identically constructed transmission function control element is included. The transmission function control member UEAS includes data input and data output devices DE and DA to which the input code converter ECW and the output code converter ACW are connected.

In the direction of the duplicate central memory units SEI and SE2 are the output registers AdAR and WAR for address and word information and the register SSAR. The selection connections for the address and selection information regulate the transmission of the currently selected data words. These connections are denoted by AdAW and WAW. The selection signals for controlling the selection circuits are produced by the period selection control element ZAWS, to which each unit of the transfer function control element, which can transfer information to one or both memory units, indicates its period requirement. As an example, the information path between the data input DE and the main memory is mentioned here. In this case, the data input device DE transmits the period request to the period selection control element ZAWS based on the request from the input code encoder ECW not shown here. Here, the request signal ZA is further input to the memory while simultaneously preparing information paths for address and selection information between the data input device DE and the address and word output register AdAR and WAR via the selection connection AdAW and WAW. With the period divider ZQ, which is formed in the central device inside the central memory units SEI and SE2, the information paths become switched-through. In this way, the information paths between the other information transmitters and the information receivers within the control element of the transmission functions also become connected.

The transfer function control element UEAS further includes the already mentioned intermediate storage devices, namely the cycle buffer memory ZP and the side cycle buffer memory NZP. As described in detail in German application 2 131 449, this is a multi-stage transfer register. While the cycle buffer memory receives all the essential information provided to the memory, the page cycle buffer memory only takes information from the cycle buffer memory when this data is actually needed for other functions. Thus, the periodic buffer memory ZP always contains a set of current information that is necessary for performing functions in one or both of the main memory units.

The transmission function control member UEAS has other control connections, other information sources and other connection means for addressing specific memory areas. An example is the clock sensor UZG and the counters BSZ and NBZ shown here. All information sources have access to both the sequence selection control and also to the address register or word register.

In the direction of the central memory units SEI and SE2, the word processing register WER is located in the transmission function control member UEAS, through which the information read from the memory arrives at the evaluation device BW, the side division matching memory NZP and the data output device DA.

Apart from the data and control lines mentioned and shown, there are, of course, a number of other data and control lines, the presentation of which, however, is not necessary for an understanding of the invention.

The devices of the transfer function control member which, in the event of an error, support the diagnostic functions of the backup program are, for each transfer function control element UEAS, the error collection device PSS, the diagnostic routine device DSS and the connection register VR, and a number of additional data and control signals.

The error collecting devices PSS each include an error register PER, 9 591 89 with a number of error rate stages FEKO ... FEK63 corresponding to the number of errors to be processed, a priority logic circuit PRL, a register FEWR for receiving the error word FEW and an error response circuit FSG for generating error response signals. The error response signals PSS, PVS, FVS and RSA are available at the outputs of the error response circuit FSG. For the error collecting device FSS, a blocking stage SPK is further provided, through which an error response signal SP is provided. The error response signals PSS, PVS and FVS are applied to both main memory units SEI and SE2. The function of the error response signals RSA and SP is to control the data paths within the control element of the transmission functions. Therefore, they are called internal error response signals.

The diagnostic routine device DR recognizes the diagnostic command read from the memory unit. It is therefore accessible through the word register WER. It includes first and second interpretation devices OP and BF in which the private bits of the operation and instruction part of the diagnostic instruction are identified, as well as the connections which, on the basis of this identification, produce control signals. The period counter ZZ, which is set in accordance with the diagnostic command, allows the control element of the transfer functions to determine a number of periods before logging, i.e. memory is cleared in memory.

The connection register VR is arranged for the data input device DE. It makes the connection between the input and output transducers and the control function of the malfunctioning and discarded transfer functions disconnected or re-established after the end of the diagnostic functions.

The function of the control circuit DSS is to form a data loop between the DSL data output device DA and the data input device DE. Both the control switching DSS and also the connection register VR can be connected to the word register by control via the diagnostic routine device DR; they are thus controlled in a programmed manner by means of a diagnostic command.

The following describes only a few essential functions (transaction flows). These are always initiated by the identification of an error that affects the control element of the transfer functions. In this case, there may be errors in the control element of the transfer functions themselves or at the intersections through which this is connected to other units.

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The occurrence of an error is known, for example, so that no periodicity occurs after the periodic request has been sent. An example of the connection from the latter case is shown in Figure 3.

The period request signals ZA from the private data sources to the transmission function control element UEAS are arranged and evaluated in a manner not shown here in the period selection control element ZAWS in such a way that only one request at a time is forwarded to the central memory unit. The output of the required period is confirmed by the period selection control member by sending back the period acknowledgment signal ZQ. Logically connecting the period requirement signal ZA and the period acknowledgment signal ZQ via the OR gate G1 and the AND gate G2, each of which is followed by bistable. Flip-flops K1 and K2, an error signal FA is given whenever no period signal occurs after the period requirement signal ZA is transmitted. ZQ or when a period acknowledgment signal ZQ occurs without a period requirement signal having previously been output.

The error signal FA is applied to a specific input of the error collecting device FSS. In this device, the error oscillation stage arranged for this error signal in the error register FER, in this example the error oscillation stage FEK4, is set. Other error detection circuits, which are not described in detail here, also monitor other circuits involved in the selection of the cycle, which set other error rate stages with error signals, e.g. error oscillation steps FEK8 ... FEK15 · The status of the error oscillation steps in the error register thus provides sufficiently accurate information about the errors.

Since the memory word can only comprise only 32 bits at a time, a 32-bit word must be formed from the state of the error register FER comprising 64 flip-flop stages by switching the priority logic connection PRL. This word is called the error word FEW. In this case, it is possible to assign a certain part of the error word to a fixed error, however, the other part of the error word can be made variable, i.e. this section may provide more detailed information on the quality of the information contained in the other parts of the error word. For example, bits 8 to 15 in a variable part may have a different meaning in each case, depending on the specific bits within the fixed part of the error word. A summary of the errors occurring in the program-controlled data transmission plant and their arrangement in different bits in a 32-bit error word is shown in Fig. 11 59189 sa 4. The figure on the left shows a 32-bit codeword FEW. In Fig. 4, for example, the assumed error marked with bit 1 means that the intersection point output from the control function of the transfer functions under consideration is closed.

Bits 8-15 (byte 1) of the error word can be loaded with 5 error groups FGR1 ... FGR5 · The error group FGR1 is transferred in the error word FEW, e.g. when bit 4 is set. In this case, the error word FEW in bits 8-15 contains more detailed information about the quality of the error FE4. Similarly, the error groups FGR2 ... FGR5 are shifted when a specific error occurs in the fixed part of the error word FEW byte 1. The priority logic PRL then controls the selection if several errors occur at the same time, for which error groups are assigned to each.

The error word is available via the error word register FEWR and the 32-wire error response circuit FSG. Here, error response signals are generated in a predetermined order. This is the case with the error response signals PSS, PVS and FVS, which arrive at the memory units SEI and SE2 via the intersection lines. These error response signals are evaluated in a manner not shown here in the main control devices of the memory units in that the transmission function control element transmitting the error response signal PVS or, if the error response signal PSS is also transmitted, the memory units are set to test mode. This can also happen simultaneously, i. both the transfer function control element UEAS and also the memory units can take up the test mode. By sending the error response signal FVS, the error state is centrally registered and the backup program is started. Details of this are described, for example, in German Patent Application 2,148,981.

Errors that can cause information to be falsified always result in the generation of an error response signal PSS, PVS and FVS, in addition to the generation of an error response signal SP, which is not transmitted to the memory. This sets the blocking oscillation stage SPK, through the output of which the transfer event in the cycle buffer memory ZP, the valuation event in the evaluation device BW and the cycle selection in the cycle selection control element ZAWS are blocked. Thus, the essential information of the previous activities remains valid. With the error response signal RSA, all control connections in the control element of the transfer functions are finally reset.

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Suppose now that the error response signal PVS, which is sent to both memory units SEI and SE2 via the intersection point wires and is evaluated here in the function requirement register, has resulted in the transmission function control body UEAS having taken up the test mode. This takes place, as described, for example, in German application publication 0228 3 ^ 5, in such a way that information is generated in the central control element of the system about the test state of the control element of the transmission functions. This information is always taken into account when allocating requirements for the transfer function control device and for the transfer function control devices. By sending back the signal PV, this status is notified to the control element of the transmission functions.

Before and during the diagnostic event, it is necessary to separate the connection to the input and output transducers ECW and ACW. This is done by evaluating the reverse signal PV in the connection register VR of the erroneous transmission operation control element. As shown in the connection shown in Fig. 5, the connection register is in each case given to one input and output code converter connection ECW and ACW and connected to these by 3 control lines. The corresponding control signals APU, CUT and TAC signal a switched (APU = 0; CUT = 0; TAC = 0) or disconnected association (APU = 1 or CUT = 1; TAC = 1) between the transmission function control element UEAS and the respective input and output transducer connection.

For generating and evaluating these control signals, the combining register VR includes gates G3 ... G7 and a bistable flip-flop stage KV. The EACW input and output converter has port G8. Gates G3, G4, and G8 each have a plurality of control inputs StE1, StE2, StE3, StE4, and StE5, StE6. A control output StA1 is established via the gate G7, to which a signal is given only when the connection between the transmission function control element UEAS and the input and output transducer EACW is switched on.

It is found that this is the case only when there is no signal at either of the control inputs StE1 and StE2, when at the same time the flip-flop stage KV through one input St3, StE6 is set and when there is still no signal at the control inputs StE5 and StE6. Connected to the control inputs StE1 and StE2 are in each case control lines through which difference signals, e.g. the signal PV, are transmitted. The control inputs StE5 and StE6 can be activated, for example, in the input and output code converter EACW when the power supply is interrupted. The control inputs StE3 and StE4 are in each case connected to control lines through which the connection signal is transmitted.

Detection of the PVS error response signal in the central memory unit results in the activation of the backup program. During the execution of the backup program, corresponding information about the program control unit not shown here is written to the control function of the transfer functions in a fixedly arranged diagnostic start cell. This diagnostic start cell is located in a specific area of the central memory unit SEI or SE2. The control function of the transfer functions reads the diagnosis start cell, receives its contents from the word input register in the WER diagnostic chip machine and recognizes it. Reading the diagnosis boot cell clears its contents.

The content of the diagnosis start cell comprises the operation part OP (2 bits), information on the logging method (P-bit) and information on whether a cycle calculation is to take place (Z-bit). For this information, the following bits contain information ZANZ (6 bits) for allocating the period counter ZZ. Finally, the diagnostic start cell contains information about the quality and location of one or more functions to be performed. The form of the diagnostic command is illustrated in Fig. 6. Based on the contents of the diagnosis start cell, reference is made to the block diagram of Fig. 7 to determine the functions under the control of the diagnostic chip routine device DR in the transfer operation control member.

The upper left part of Fig. 7 shows that the transfer function control member is in test mode (UEAS = P), that the corresponding areas in the memory unit are likewise in test mode (SE = P) and that the transfer function control member is connected to the respective memory unit (SE-UEAS).

If these conditions are met, the diagnostic function (DR START) starts. For the sake of completeness, it should be noted here that the reset of controls in the control function of the transfer functions to be diagnosed must be initially set (RSA INITIAL PULSE) and ended (RSA ENDED?). is now brought to the output position by the signal RSA.Now, the contents of the diagnostic start cell (DSZ READING) are read and identified in the first interpreting device OP.

^ 59189 0P = 00: The contents of the diagnostics start cell are routed via the word input register WER directly to the word output register WAR (WER-WAR) of the transfer operation controller UEAS and written to the diagnostic protocol cell (WAR = DPZ) of the main memory. In the connection according to Fig. 2, this takes place with the control signal StS1.

0P = 01: Contents of the error register PER at the error collection location FSS

is output in the form of the error word PEW (error word output FEWA), allocated to the word output register WAR (FEWR = WAR) and written to the diagnostic protocol cell (WAR = DPZ). The error register is switched off (FER PAIA.UTUS). In the connection shown in Fig. 2, this takes place with the control signal StS2.

0P = 10: The inhibit tilt stage SPK in the error collecting device FSS is reset by the control signal StS3 (Fig. 2). Thus, the blocking of the valuation circuit BW and the transfer event in the cycle buffer memory is removed.

The cycle buffer itself is reset (ZP / BW is unblocked; ZP is reset).

When the function of the functions (program flows) described so far is to have a large enough amount of data in the central position to determine the error quality and location, then regarding. The results obtained in this case allow an accurate error diagnosis to be made quickly.

0P = 11: The contents of the diagnostic start cell are interpreted as so-called. as a direct command for the control function of the transfer functions, which with the control signal StS * J leads to the switching of the second interpreting device BF in the diagnostic routine device DR. In this case, both the P-bit and also the Z-bit are identified in the instruction part of the diagnostic instruction. When P = 0 the information in the word output register WAR is taken, when P = 1 the information in the register SSAR is received after the reservation in the word output register in the diagnostic protocol cell. The Z-bit = 1 means that the information ZANZ (bits ^ ... 9) is used to set the period counter ZZ. In this case, it is possible to reserve a maximum of 2 ^ = 64 memory periods before the protocol period is executed, i.e. diagnoses 15,591 89 protocol cell data is received only after a predetermined number of cycles have been determined. This flow of events corresponds to the right-hand side of the program flow diagram 7. Here, the DB is marked with a diagnostic command interpreted as a direct instruction, which must be executed after the interpretation. The cycle counter ZZ is then always reduced by 1 (ZZ: -1) until it reaches state 0 (ZZ = 0). In this case, the recording will be prepared (PRT PREPARATION). When bit P = 0, the contents of the word output register WAR are received in the next section in the diagnostic protocol cell. When P = 1, after reloading the contents of the register SSAR, the word output register WAR (SSAR = WAR) is received in the diagnostic protocol cell (WAR «DPZ).

After the contents of the word output register WAR have been received in the diagnostic protocol cell, the connections for identifying the P-bits and the Z-bits, i.e. the tipping steps in the diagnostic routine device for this purpose, are restored. The reset signal RSA to all other control means in the control function of the transfer functions is given again, so that the same output conditions exist for a possible next diagnostic command.

By recognizing the diagnostic command as a direct command to the control function of the transfer functions, all essential functions can be programmed here. Here are a few more features.

One of these functions results in the formation of data output and data input loops. This function is important because thus the connections in the data input and output devices DE and DA, which are normally used for information between the control element of the transmission functions and the input and output code converters, are drawn into the operation test.

For this purpose, the diagnostic cache, interpreted as a direct command, contains information which, together with the address of the interface connection, is provided to the data output device DA. At the same time, the control element DSS becomes activated. This is done by the control signal StS7, which is generated in the diagnostic routine device DR by interpreting the corresponding instruction part. For the data input device DE, the information received via the data loop corresponds to the information normally provided by the input transducer. All functions triggered at the request of the input transducer are thus initiated.

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Another important function in this context is the function "clear memory and cycle buffer transfer". With the error response signal SP, the cycle buffer memory became isolated in the transfer function control member, and its transfer operation became inhibited. Thus, it is ensured that the information of the last usage periods for which the transfer function controller had an extract from the key memory units is retained. The diagnostic command, which is interpreted as described as a direct command for the function "clear memory and cycle buffer memory transfer" in the diagnostic router DR, can be controlled by resetting the block buffer stage SPK in the error collecting device PSS, simultaneously performing the transfer. The data in stage 0 of the cycle buffer memory is thus transferred to the word output register WAR, and after clearing the diagnostic protocol cell, the key backup program is available as information about the last operations in the transfer operations controller for further processing.

Other diagnostic commands, which can be interpreted as direct commands, can be used to download the connection registers and all other relevant registers in a program-controlled manner and to record their contents.

Claims (7)

1. Device for monitoring and setting fault diagnosis on traffic decommissioning control means in a wiring connection unit in module-built program controlled data transmission systems with individual devices for detecting faults and for delivering fault signals in which and for setting fault diagnosis frame probes , characterized in that a fault accumulation device (PSS) for receiving the individual error signals (PA) is provided in each traffic traffic control unit (UEAS) to generate the individual error signals (FEW) and for the error descriptor thereof (FEW). forming error response signals (PSS, PVS, PVS, SP, RSA), one of which is a first and a second internal error signal comprising first group of error signals (RSA, SP) arranged to be evaluated in the traffic settlement control unit (UEAS) and a second group of error signals (PSS, PVS, FVS) is arranged to be sent to central memory units (SEI, SE2), further providing a diagnostic device. ng (DR) is arranged for evaluating a diagnostic instruction (DSI) read in the central memory unit (SEI, SE2) when receiving and evaluating an error response signal (FVS) in the second group of a central memory unit (SEI, SE2) in a security program, the diagnostic routine device (DR) includes a first decoding coupling (OP) to decode an operating portion of the diagnostic instruction and to generate first control signals (StS1 ... StS3)> by means of which in the traffic deception control (UEAS) data vios are interconnectable between the word output register (WAR) on one side and the order entry register (WER), an error word containing error word register (FEWR) in the error accumulation device (FSS) and an intermediate storage cycle buffer memory (ZP) in the traffic settlement control unit (UEAS) on the other side the diagnostic routine device (DR) contains a second decoding switch (BF) which can be activated by a further first control signal (BF), which an instruction part of the diagnostic instruction generates other control signals (StS5 ··· StSn), and that said control couplings and registers in the traffic settlement control means (UEAS) under the control of one of these other control signals (StS5 ... StSn) are switchable for transmitters. giving the diagnostic instruction to the prescription register (WER). Device according to claim 1, characterized in that the error accumulation device (FSS) contains an error register (FER) in which each individual error is assigned an error tilt step (FEKO ... FEK63), that for the formation of the error word (FEW) only the output from some of the error flip steps (FEKO ... FEK7; FEK ^ 8 ... FEK63) are directly connected to the inputs of the error word register (FEWR), while the outputs of a second part of the error flip steps (FEK8 ... FEK47) are merged into error groups (FGR1 ... FGR5) and are linked to a priority logic switch (PRL), over which only the error tilt steps of an error group (FGR1 ... FGR5) are linked to the error word register (FEWR). Device according to claims 1 and 2, characterized in that the error accumulation device (FSS) for evaluation of the error word (FEW) contains a fault response coupling (FSG) and a coordinate latching step (SPK), that the fault reaction coupling (FSG) is arranged to generate on the one hand, the fault response signals (PSS, PVS, FSV) in the second group for transmission to the central memory units (SEI, SE2), on the one hand, the traffic control control unit (UEAS) resetting first internal fault response signal (RSA) and partly on conversion of the latch step (SPK) the other internal error response signal (SP) and that this second internal error response signal (SP) is arranged to block the further function of the cycle selection control (ZAWS), the cycle buffer memory (ZP) and the evaluation coupling (BW). 4. Device according to claims 1-3, characterized in that the first decoding device (OP) for taking over the diagnostic instruction is connected to the traffic decoding control units (UEAS) prescription registers (WER) and for transmitting the first control signals (StS1 ... StS4). connected to the word-output register (WAR), the error-word register (FEWR), the latch step (SPK) and the second decoding device (BP), that by means of the first control signals (StS1 ... StS3), the acquisition of the in the order register (WER) respectively. the information contained in the error word register (PEWR) and by switching the latch step (SPK) the second internal error signal (SP) is frankable and the acquisition of the information contained in the cycle buffer memory (ZP) is controllable to the word output register (WAR). the word output register (WAR) for protocol entry is arranged to be transferred to the diagnostic area (DPZ) in the central memory unit (SEI, SE2). Device according to claims 1-3, characterized in that the second decoding device (BF) of. because a further first control signal (StS4) formed in the first decoding device is connectable to the order register (WER) and is arranged to evaluate the diagnostic instruction as an individual traffic instruction for the traffic decommissioning control (UEAS), to divert an individual execution and the registers (SSAR, AdAR, UZG, BSZ, NBZ) of the traffic settlement control (UEAS) transmit one of said second control signals (StS5 ... StSIO), and the relevant control organs and registers are connectable to the order register (WER) for taking over the settlement instruction. Device according to claim 1, characterized in that the data and data output devices (DE, DA) of the traffic decontrol control (UEAS) are connected over a further