GB2087689A - Transit exchanges of time division telecommunication systems - Google Patents

Abstract

A transit exchange 1 is controlled by a central control 2 and comprises line units 3, two transit control units 5a, 5b which interface PCM systems with the central control, a time-space switching network 4 made up of two identical and synchronous sections 4a, 4b each comprising several input time switching groups and as many output ones, between which a space switching state is interposed, and identity control units 6 which compare the data switched by the two sections. The line units and the input and output time switching groups are arranged in modules. Provision is made for fault location and indication. <IMAGE>

Description

SPECIFICATION Improvements in or relating to information management apparatuses for transit networks of time division telecommunication systems The present invention relates to information management apparatus for managing information relating to alarm and/or response signals to control and/or autocontrol commands, for use in a transit network of time division telecommunication systems. The transit network is controlled by a central control and the whole constitutes a telephone transit exchange suitable for switching digital signals.

Such a transit network (see for example the Italian patent No. 1.037.256 registered on the 14-4-1975 in the name of SOCIETA ITALIANA TELECOMUNICA ZIONI SIEMENS S.p.A.) may be of the type comprising: a plurality of line units, of equal number to that of the PCM systems, each of which constitures the interface between the transmit network and a corresponding one of the PCM systems; a switching network, connected to the line units and controlled by the central control for performing time-space switching of each PCM channel, the switching network being made up of two identical and synchronous sections, having total accessibility to the PCM systems through the corresponding line units; a group identifying circuit connected to the output groups of the switching networks for detecting any differences in the signals processed by the switching sections; and two identical transit control units which make up the interface between the central control and the switching sections.

Each of the above mentioned time-space switching sections is oftheTSTtype and includes a first time switching stage which transfers each PCM sample from the input PCM channel phase to a work phase assigned each time by the central control, a space switching stage and a second time switching stage which transfers the said PCM samples from the said work phase to that of the output PCM channel. The first time switching stage is made up of a predetermined number of input time switching groups to each of which a predetermined number of PCM systems is connected.The second time switching stage is made up of a predetermined number of output time switching groups (equal to the number of the aforesaid input time groups) to each of which a predetermined number of PCM systems is connected, (equal to number of PCM systems connected to any one of the input time switching groups). The group identifying circuit is made up of several identical circuits, each of which is interconnected between the ports of two corresponding output time switching groups belonging to both sections, i.e. two groups arranged to process the same data synchronously.

The transit network may be thought of as being made up of the two transit control units, the space switching stage and several modules connected to the transit control units and space switching stage. Each module is made up of several input time switching groups and as many output ones, (equally alloted between the switching sections), a predetermined number of the aforementioned group identifying circuits, and the line units connected to the aforesaid time switching groups.

According to one aspect of the present invention, there is provided an information management apparatus for managing information about alarm signals and/or response signals to control and/or autocontrol commands relating to a transit network for time division telecommunication systems connected to a switching junction comprising a central control and the transit network, which comprises: a plurality of line units equal in number to the number of PCM systems and each forming an interface between the transit network and a corresponding PCM system; a switching network connected to the line units and controlled by the central control for performing space-time switching of each PCM channel, the switching network comprising two identical and synchronous sections, each of which comprises a first time switching stage for transferring each PCM sample from the corresponding PCM input channel phase to a work phase allocated by the central control, a space switching stage for the PCM sample, and a second time switching stage for transferring each PCM sample from the work phase to the corresponding output channel phase, the first and second time switching stages comprising a predetermined number of input and output time switching groups and a predetermined number of line units connected to each of the groups; a plurality of group identifying circuits, equal in numbertothe number of the output time switching groups of each switching section, each of the group identifying circuits being connected to a respective output time switching groups of each of the space-time switching sections, and being arranged to detect and signal to the central control any differences between the output signals from the two groups; and at least two identical transit control units providing an interface between the central control and the transit network and arranged to preprocess alarm signals from the members of the transit network before transmission to the central control; the transit network having an equal number of the input and output time switching groups equally divided between the said sections, and a predetermined number of line units connected to the groups, arranged in a module, and further having: at least a first and a second channel for the transit of information, respectively in one direction and the other, between the central control and each transit control unit; at least a third and a fourth channel providing a connection between each transit control unit and one of the modules, for management and control commands sent to the module and for alarm signals and responses coming from the module as a consequence of the control commands; at least two transmission buses for carrying data relating to the junction channels of the transit network and providing a connection between the input time switching groups relating to the module and the space switching stage, and between the space switching stage and the output time switching groups relating to the same module; and at least one channel for carrying commands from each transit control unit to the space switching stage, the apparatus having for each of the modules, first means, connected to the third and fourth channels for receiving the alarm signals relating to the module and the responses to control commands, and, for each transit control unit, a processing network connected to the second channel and to the channels from as many modules arranged to preprocess signals supplied via the fourth channels, signals from fault controllers relating to the transit control unit, the space switching stage, and signals deriving from timing means of the transit network.

According to another aspect of the present invention, there is provided an information management apparatus for a transit network of the type controlled by a central control and comprising line units, two transit control units for interfacing PCM systems with the central control, a time-space switching network comprising two identical sections each having equal members of input and output time switching groups, a space switching network, and means for comparing and checking output data from the two sections, the line units and the input and output time switching groups being arranged as a plurality of modules, the apparatus comprising means for processing alarms and responses from the modules, alarms and replies relating to control signals from the central control for the modules, and alarms from the transit control units and the space switching stages.

It is thus possible to provide an apparatus for preprocessing, whilst taking into consideration any instructions that might come from the central control, the status transitions of the alarms relating to the modules, the alarm signals from the channels involved in the commands sent to the modules, the alarm signals from the transit control units and the space switching stage, and the responses to control and/or autocontrol commands involving predetermined network members, the whole being summed up in the formation of corresponding messages to be sent to the central control taking into consideration any predetermined priorities.

The invention will be further described, by way of example, with reference to the accompanying drawings, in which: Figure lisa block diagram of a transit network including a preferred embodiment of the present apparatus; Figure 2 illustrates schematically a preferred embodiment of the present invention in which the connections between a module and the remaining members of a transit network are shown; Figure 3 is a block diagram of a module M of Figure 2; Figure 4 is a block diagram of a means 50 of Figure 2; Figure 5 is a block diagram of a device 20 of Figure 2; and Figure 6 is a block diagram of a member 23 of Figures 2, 3, and 4.

With reference to Figure 1, a transit network 1 is controlled by a central control 2. The transit network and the central control constitute a transit telephone exchange capable of switching degital signals. Line units 3 are provided within the transit network 1, (only one unit is shown in the Figure) and form an interface with bidirectional PCM systems connecting the transit network to respective peripheral units.

Furthermore, the line units 3 detect line alarms (by means of controllers of well known type indicated generically by 3a, see Figure 3) and transferthe PCM samples from central timing to that of the lines and vice versa.

Atransit network 4 is connected to the line units 3 and carries out the space-time switching of the PCM signals. The network 4 is made up of two identical sections 4a, 4b which carry out switching in synchronism. The sections 4a, 4b are connected to corresponding transit control units 5a, Sb, which provide an interface between the transit network 1 and the central control 2. The transit control units distribute the orders of the central control 2 to the subordinate members of the switching network, and "filter" and preprocess the alarms received from the same members before sending the alarms on to the central control. The functions concerning alarm filtering and preprocessing will be further described hereinafter.In the embodiment shown in Figure 1, the central control 2 is made up of two processors A, B, which operate in parallel according to the master-slave scheme. The two transit control units 5a, Sb are connected to both the processors and dialogue with the one that is currently acting as master. The two space-time switching sections 4a, 4b also operate in parallel according to the master-slave scheme. The choice of the master section is made each time by the central control and then communicated to the line units 3 so that only those channels that are processed by the master section are transmitted along the lines.

In Figure 1, the unbroken lines indicate the PCM channel routes, whilst the broken lines indicate command and alarm routes which are physically distinct from the PCM channel routes and which will be described in greater detail hereinafter.

The switching network 4 acts on the groups of bits making up each PCM channel so as to perform a double switching, i.e. in space and time. The space switching transfers the PCM channels from one to the other of the PCM systems connected to the transit network, and the time switching transfers the channels from the phase of the input PCM system to that of the output PCM system.

As disclosed in Italian patent No. 1.037.256,the time switching takes place in two successive stages passing through an intermediate work phase in which the space switching takes place. Each switching section 4a,4h therefore includes a first time switching stage made up of a predetermined number of input time switching groups, a space switching stage made up of a space network (identified by the number 104 in Figure 2), and a second time switching stage made up of a predetermined number (equal to the number ofthe input groups) of output time switching groups. Each input time switching group is connected to a corresponding line unit 3 by means of a channel marked 118, whilst each output time switching group is connected to a corresponding line unit 3 by means of a channel marked 8.Information coming from two corresponding output switching groups, that is one belonging to section 4a and a corresponding one belonging to section 4b, is supplied to an identification circuit belonging to group 6, the function of which is to detect, bit by bit, any identity disagreements between corresponding bits.

In order to carry out the above described function, each identification circuit of the group 6 includes a comparator circuit arranged, as described previously, to compare the signals, bit by bit, making up the frame (composed of 256 channels) from the output of two corresponding output time switching groups. The comparator circuit generates a characteristic signal in the event of incorrect comparison of at least two corresponding bits relating to an octet.

The output of the comparator circuit is connected to a digital filter which provides at its output (indicated schematically in Figure 3 with the number 17a) an error signal when the characteristic signal is repeated for a predetermined number of frames. The output 1 7a of the filter is connected to the first input of a logic gate 17, whose second input is connected to a cyclic memory 18.

The memory 18 is arranged to register as many electrical signals as the number ofthe channels of the frame supplied to the aforementioned logic gate 17. Each of the electrical signals assumes two distinct electrical states, corresponding to identity or non-identity, to generate an alarm for the corresponding channel; this is decided by the central control 2, (to which the memory 18 itself is connected by means of a channel 18a), which may prevent one or more channels from generating alarm signals (the reason for this is not explained herein, as it is not of importance with regard to the present invention).

Activation of the logic gate 17 (for example two high level signals at its inputs) brings about activation of a block 19 (made up for example of a bistable), the output of which presents two distinct electrical states, (for example high and low level), of which the first indicates the presence of an alarm in one of the channels of the frame supplied to the circuit 6. This electrical state continues until the alarm signal has been accepted by the central control as will be described hereinafter.

As shown in Figure 3, the output 1 17a of the logic gate 17 is supplied to a multiplexer 16. Similarly, the output 1 18a of the memory 18 is supplied to the multiplexer. As shown in Figure 3, apart from the outputs 1 17a, 118a, other outputs 1 17b, c, d, and 118b, c, d, are also shown schematically. Thus, the outputs ofthe logic gates 17 and of the memories 18 of one module of the transit network are all supplied to the multiplexer 16. Each module comprises an equal number of input and output time switching groups (divided equally between the sections 4a, 4h), a predetermined number of group identification circuits 6, and a predetermined number of line units.In the embodiment shown in Figure 3, each module is made up of 32 line units 3,8 input time switching groups and 8 output time switching groups (4 groups for each section 4a, 4b) and 4 group identification circuits 6.

Each module is provided with 4 blocks of the type previously indicated by 19, the outputs of which are supplied to corresponding inputs (generally indicated by R) of first means indicated generically by 100, which will be further described hereinafter, provided with a data selector 110 for collection of alarms and responses.

As has been previously described, the switching sections 4a, 4b operate in parallel according to the master-slave scheme. The choice of the master section is made each separate time by the central control 2 and communicated to the units 3 so that only the channels processed by the master section will be transmitted to the lines.

In order to carry out such functions, the command to designate master-slave is supplied to each module M by means of a channel 03, and is then sent to four blocks 201,202,203,204 (one for each output time switching group with which each module is provided) made up of as many flip-flops, as well as to a centralized block 200 (this too being made up of a flip-flop) used to provide the reference signal (or bit).

The above mentioned command causes in the absence of faults in the blocks concerned), the same electrical output state from the blocks 200,201,202, 203, 204, which electrical state, high or low level, identifies the corresponding section 4a, 4b, chosen to act as master.

The output of the block 201 is connected to the eight line units 3 relating to a corresponding output time switching group in such a way as to allow the line units to handle only the channels processed by the master section. Analogues considerations apply to the blocks 202, 203, 204. The outputs of the blocks 201, 202, 203,204 are connected in an orderly manner to the first inputs of corresponding comparators 215,216,217,218. The output 200a ofthe block 200, which provides, as previously mentioned, reference bits, is supplied to the second inputs of the comparators.

The outputs 215a, 216a, 217a, 218a, of the comparators are connected to a device 220, the function of which is to activate (high level) its output 220a in the case of non identity of the electrical states (high or low level) present at the two inputs of each comparator.

Activation of the output 220a provides an alarm signal relating to the choice of the network carried out by the central control 2. The output 220a, together with the outputs 200a, 215a, 216a, 217a, 218a, are all connected to the device 110 for collection of alarms and responses (inputs Q of the device).

In the event of the module being under equipped (for example one output time switching group, and therefore one input time switching group, is not provided, the comparator associated with this output group is forced, by means of commands (not shown) to supply at its output the correct detection electrical state (in other words it does not supply any error signals). The central control 2 carries out a generic connection (to be understood in a dynamic sense) between an input channel belonging to an input time switching group and an output channel belonging to an output time switching group, the two groups possibly belonging to different modules. The central control verifies cyclically, or on a statistical basis, or as a consequence of diagnosis interventions, the space-time continuity of a generic connection.For this purpose, each input time switching group is connected to a transmitting unit (shown generally by 300) whose function is to substitute for a PCM sam ple passing through the input channel a diagnostic digital sample. The transmitting unit found a mes sage containing information about the input channel selected as well as identification information of the same channel. This information (in binary code) is loaded respectively in zones Z1, Z2 of the device 110.

Controlling ofthe space-time continuity of the con nection is complete by providing a receiving unit 400 for the diagnostic digital sample, for each output time switching group, which is arranged to receive the same diagnostic digital sample in the output channel corresponding to the aforementioned input channel. The receiving unit forms a message containing information identification for the aforesaid output channel, identification, or not, of the same output channel, and for recognition, or not, of the diagnostic digital sample. This information is loaded respectively in zones Z3, Z, Z of the above men tioned device 110.

Again with reference to Figure 3, the number 310 generally indicates supply controllers of the line units 3. The electrical terminals of the controllers are connected to a zone, marked with an S, of the device 110. The number 210 generally indicates a signal generator (zone P of device 110) for providing two bits with a characteristic value which are checked by the transit control units Sa, Sb. From the result of such a check, the continuity, or not, of the transmis sion bus (channel C4) is deduced.

15a indicates the electrical terminal of detection means 15 (connected to a channel C3 for the com mands sent to a corresponding module) whose func tion is to detect an error in the message transmitted (wrong message) or an error in an autocontrol mes sage relating to the operation of the detection means 15 itself. The signal relating to the erroneous mes sage is sent, by means of a channel Cis, to a block 14 which will be described hereinafter.

Thus, the following are all supplied to the inputs of the device 110: information about the transmission bus C3 (erroneous message), relating to incorrect operation of the detection means 15 (wrong reply to an autocontrol message), this information is all input to the electrical terminal 15a; information concern ing the chosen network's alarms (Q zone); the state of the network (R zone); the signal from which the transit control units draw information about the state ofthetransmission bus (P zone); information con cerning line unit feeding alarms (S zone); and infor mation concerning alarms deriving from the control lers 3a connected to the line units 3 (T zone).The following are also supplied to the device 110: infor mation concerning response messages of the space-time continuity controlling of a connection (zonesZ1,Z3, Z3, Z4, Z5) and information (electrical terminal 16a) ofthe frame either being output or coming from the logic gate 17, or of the frame stored in the memory 18 concerning one of the group identification circuits 6 with which the module being examined is provided, in that the device 16, in response to the commands c supplied thereto, provides at its output 16a either one or the other of the frames.

Connection of the device 110 to timing means 23 (which will be further described hereinafter) allows a frame containing both alarm signals and response information to be obtained at the output 1 lOaThe frame is supplied to a data selector 22, to which, furthermore, the output of a parity generator 21 is also supplied, so as to obtain, at output C4 of the data selector 22, the above-mentioned parity corrected message (in other words the aforesaid frame).

With reference to Figure 2, the number 150 indicates a processing network arranged to preprocess the messages from the central control 2 (by means of a channel C1) before sending them (by means of corresponding channels C3) to the modules for which they are intended. Number 50 indicates a processing network arranged to process the alarms and responses from the modules (by means of as many channels 04), the internal alarms to the transit control units (controllers indicated generally by 114and channel 14b which will be further described hereinafter) and alarms from the space network 104 (controllers indicated generally by 115). The network 50 processes the aforesaid alarm signals and the response signals so as to form messages to send, by means of a channel C2, to the central control 2.

As previously mentioned, the channel C, carries commands from the central control 2 and for the network 150. The absence of parity and order of the messages in the channel C1 is detected respectively by corresponding blocks 11, 12 (made up of common flip-flops) which activate as a consequence a block 14 whose two outputs 14a, 14b are respectively connected to the central control 2 and to the network 50. The block 14 is also activated by a block 13 which detects the absence of synchronism of one transit control unit, e.g. 5a, with the other, e.g.5b (connected to 5a by means of a channel Cs) as well as by the controller 15.The block 13 is forced, by means of commands (not shown) not to supply synch ron- ism absence signals when the two units 5a, 5b operate singly (that is to say, not in parallel according to the master-slave scheme).

The central control 2, as mentioned above, sends messages to the network 150. In a phase previous to the processing of such a message by the switching network 4 (sections 4a, 4b made up of the modules M and of the switching stage 104) the central control "reads" both a block 10 (by means of a channel 10a) which is activated when processing of the message by the transit control units is finished, and the block 14. Activation, or non-activation of the block 14 is an indication respectively of the presence or absence of an error in the message that has just been transmitted from the central control. In the event of the block 14 signalling the presence of an error (in accordance with what has just been described) the central control 2 blocks (stops) the sending of the following messages to the processing network 150.This is par ticularly advantageous because it avoids propaga tion of the error to the switching network, prevents the contents of the messages following that which contains an errorfrom being lost, and allows the central control to repeat the message that has caused the alarm signal as described above in order to verify the continuation, or not, of the cause of the error.

With reference to Fig. 4, F indicates generally all the channels C4 from the various modules (for example 16 in number). Each channel C4 is con nected to a first input of a comparator 25 whose sec ond input is connected to a state memory 26 of a cyclic type, whose contents may be "read" by the central control by means of a channel C36. In the memory 26, which is advanced by the timing means 23, the state of the alarms concerning the previous frame with respect to that in transit in the channel C4 is registered. Thus, the comparator 25 activates its output (high level) each time there is a transition of one of the alarms previously mentioned.

The output of the comparator 25 is supplied to the first input of a logic gate 28, whose other input is connected to a memory 27 of a cyclic type which is advanced by the timing means 23 and which is controlled via a channel C37 by the central control. The memory 27 contains a number of electrical signals corresponding to the number of possible alarm signals from the module. Each of the electrical sign als assumes two distinct electrical states which identify respectively enabling a non-enabling of the alarm of the corresponding member which has caused the said alarm transition.

When two high level signals are present at the two inputs of the gate 28, the gate 28 activates its output indicated by 281 which is connected to one of the inputs of a device 29. The device 29 has further inputs 283... 28,, equal in number to the number of modules with which the transit network is provided.

The output 29a of the device is activated as soon as one of the aforementioned inputs is activated.

This activation brings about the transmission of an alarm signal message also containing data identifying the module to which the alarm relates. The device 29 is furthermore provided with an output channel 31 which supplies a message for identifying the module which supplied the alarm as soon as one of the inputs of the device 29 is activated.

The output 29a is connected to a microprogrammed block 30 which is activated by the aforesaid alarm message. This activation causes the starting of an appropriate program in block 30 with transmission of commands to a channel 37. The running of the microprogram of the block 30 initially enables a first register 33 to store the information that reaches it through its input channels (for example 4 in the number) 33a, b, c, d. The output of a decoder 32 connected to the timing means 23 is connected to the input 33a. In this way an appropriate operative code to identify the type of alarm which has caused the message described above is stored in the register 33. The channel 31, affected by the information to locate the address of the module which produced the alarm, is connected to the input channel 33b.The output of a device 38 (whose inputs are connected to the channels C4 and are affected by the channel 31) whose function is to generate information to identify the type of transition under examination (from good to faulty or vice versa) is connected to the input 33c.

Other information is supplied to the input 33d, for example information for locating the channel which supplied the alarm if the above mentioned signal that caused the aforesaid alarm message is related to one of the group identification circuits with which every module is provided and which have been pre viouslydescribed herein. Enabling of the register 33 to store the information described above brings about the simultaneous activation of a block 34 (or flag, made up for example of a flip flop) whose output is connected to the block 30. Activation of the block 34 (high level of the signal present at its output) means that the block 30 cannot affect, by means of a further alarm, the register 33.

The running of the microprogram of the block 30 is subordinate to the permission of the output of a device 24 whose inputs 24i. . . 24n are connected via corresponding parity controllers 64, to corresponding channels C4. The function of the device 24, to which the channel 31 is connected, is to verify the parity of the alarm frame on the channel C4. The block 30 receives any parity error if present and in this case, by means of channel 37, cancels the information stored by the register 33 which is at the same time enabled to store a new alarm situation which obviously will require a different operative code.In either situation, a message stored in the register 33 has, according to a predetermined priority scale, a certain priority grade; this priority grade is deduced from the operative code associated with the message and sent, by means of a channel 32a, to a comparator 35 where it is compared with the priority stored in a register 36 relating to a previous alarm sent to the central control (the central control may impose a priority of its own, in particular it may bring the contents of the register 36 up to date).

If the priority relating to that operative code i.e. to the message stored in the register 33) is lowerthan the priority stored in the register 36, the comparator 35 is not activated, which causes the stopping, in the block 30, of the microprogram previously activated.

If the priority relating to the message stored in the register 33 is higher than the priority stored in the register 36, the comparator 35 is activated and, by activating the corresponding output, allows the microprogram to run. This causes the transmission to the channel 37 of an appropriate enabling command to "unload" the message stored in the register 33 to an appropriate channel H.

This message is supplied to an input of a buffer memory 39 which, by means of a parity generator 40 connected thereto, supplies the aforesaid message after parity correction (the memory 39 and the generator 40 are activated by means of commends from the channel 37). The message from the memory 39 is supplied to a register 41 forming a parallel to series converter which supplies the aforesaid message in series to the channel C2 which connects the processing network 50 to the central control.

The aforesaid message, besides being sent to the channel H, is also sent (by means of a channel 36a) to the register 36, and this causes updating of the priority stored in the register 36 and associated with the said message. Reception of the message by the central control causes the central control, by means of commands (not shown), to enable the cyclic memory 26 to auto-update itself, in as much as the alarm transition which caused the above described operation has in fact been acquired by the central control itself.

In the description of the functional blocks illustrated in Fig. 3, it was mentioned that an erroneous transmission message from the transit control unit sa, Sb to the corresponding module was detected by the detecting means 15 whose output level assumed a characteristic electrical state (high level). In such a situation the processing network illustrated in Fig. 4 forms an alarm message for the central control 2 containing the codes (or information) relating to the input module and the output module, and the erroneous message alarm relating to each module.

These functions are performed by two devices indicated in Fig. 4 by the numbers 52 and 54, which are provided with a plurality of inputs respectively connected to the channels C4 from the modules with which the transit network is provided. The Device 52 is connected to a channel 310 to which information relating to the coding of the input module is sent, whilst the device 54 is connected to a channel 310 to which information relating to the coding of the output module is sent. The outputs of the devices 52, 54 are connected to an OR gate 53, whose output provides the alarm message containing the information described above.

The output of the gate 53 is connected to the block 30, channelg, whilst the inputs of the gate 53 are connected to a register 133 to which the channels 310,310 are connected and the operative code is supplied via a channel 32b from the decoder 32). The register 133 is enabled to store the above mentioned message (upon command of the block 30 via the channel 37) and, in the same way as described above, "unloads" the message via the channel H to the memory 39. The memory 39 and the parity generator 40 connected to it load the parallel-toseries register 41 which then sends the message in series to the channel C2.

As previously described, the message (or frame) from a generic module and on the corresponding channel C4 contains both the alarm signals and the responses to particular control and/or autocontrol commands (referred to hereinafter as interrogation messages).

The processing network 50, illustrated in Fig. 4, processes the above mentioned responses. The interrogation messages cause the transit control units to carry out the following actions: selection of the processing procedure according to the operative code; selection of the corresponding response channel (channel C4 as previously described) according to the addresses of the output module and of the input module in the case of a space-time continuity control on a dynamic connection; and formation of the response messages to be sent to the central control containing the above mentioned responses.

Processing ofthe above mentioned responses, in order to form the corresponding message to be sent to the central control, may be carried out a certain number of frames later according to the reaction time of the switching network 4 relating to the type of interrogation message.

The responses, as previously described, are related to the request, by the transit control units, for the output frames of either one or the other of the logic gates 17, or from one or the other of the memories 18 that make up each module. Choice of either one or the other frame is made by the data selector 16 according to a command (indicated by c) from the same transit control units.

A second type of response, as previously described, is that supplied respectively by the transmitting and receiving units which carry out the space-time continuity control of a dynamic connection. As mentioned above, the first message relates to the transmitting unit of the input module, and the second message to the receiving unit of the output module.

In order to form the response message described above, the devices 52, 54 are used, the outputs of which, besides being connected to the gate 53, are also connected to a data selector 55 which is acti vated, by means of signals sent through the channel 37, by the commands originating from the transit control units. The output of the selector 55 is con nected to a third register 233 (to which channel 32b is also connected) which is enabled to store the said message by the microprogrammed block 30 (by means of commands supplied via the channel 37) and furthermore supplies the response message via the channel H, the memory 39 (and the parity generator 40 associated therewith), and the register 41 to the channel C2.

As regards the autocontrol function which is performed by the detector 15, which, in the absence of messages from the processing network 150, is involved with intentionally erroneous messages, the correct or incorrect response to an intentionally erroneous message is not considered as a response in the sense described above, but as an alarm signal, in the case of incorrect response to an intentionally incorrect autocontrol message, which is considered within the alarm frame the message of which is stored in the register 33.

The internal alarms at the transit control units are the following: a) master-slave alarm. The associated detectors, indicated generally by the number 114, signal incongruities (or inconsistencies) in the choice of the master processor; b) transmission alarm from the central control to the transit control units due to absence of parity.

This alarm is detected by the block 11 illustrated in Fig. 2; c) message order sequence alarm in the event of there being a violation of the sequence of messages from the central control. This alarm is detected by the block 12; d) synchronization alarm due to the nonconfirmation of the remaining transit control unit.

This alarm is detected by the block 13 illustrated in Fig. 2. As previously described, the blocks 11, 12, 13 (and the block 15) activate the block 14 which enables the output 14b associated with the space network 50; and e) supply of alarms both for the transit control units under examination and the space switching network 104. These alarms detected by correspond ing detectors indicated generally by 115 signal any abnormalities in the supply system.

As a result of one of the above listed alarms, a message is formed to be sent to the central control.

A fourth register 333 for forming this message receives both the outputs of the detectors 14, 114, 115, (whose information is also sent to the block 30 by means of channels indicated in Fig. 4 byi), and the channel 32b carrying the operative code.

The register 333 is enabled to store the information by the block 30 by means of commends from the channel 37. The alarm message thus stored, with due respect of the priorirites already described (only in the case of alarms originating from the transit control units), is supplied to the channel H from which, by means of the memory 39 (and of the associated parity generator 40) and of the register 41, it is sent to the channel C2 which is connected to the central control 2.

The timing means 23 comprise, for example (see Fig. 6), three clocks 42,43,44. Only one of the clocks is enabled to generate timing, but should this break down the second clock takes over, and in the same way if the second clock becomes faulty then the third clock takes over.

The outputs of the clocks 42,43,44 are connected to two logic networks 46a, 46b connected respec tiveiyto the switching sections 4a, 4b. The networks 46a, 43b are arranged to chosse the clock from one ofthethree clocks to supply its the switching sections on the ground of the functional or operative state of the clocks but also carry out another function, namely forming a message present at output y and sent to the microprogrammed block 30 by means of a channel 51.

This message, formed for example by the network 46b, is made up of 8 bits. The first 3 bits indicate the continuity, or the failure, of the transmission channels between the network 46b and its associated switching section 4b. The next e bits indicate the correct functioning, or not, of the associated clock.

The seventh bit indicates the existence, or not, of the same clock in the other network 46a (which corresponds to the existence, or not, of the same clock in the associated switching network 4a). The eight and last bit is a parity bit. The message, besides being sent to the block 30, is stored in a fifth register 433, to which the channel 32b carrying the operative code is also connected.

This message is sent to the first input of a comparator 84, whose second input receives a message stored in a register 85 (and relating to the absence of alarms in the timing means 23). In the event of lack of identity, the comparator 84 activates the relative output K that is connected to the microprogrammed block 30, which causes the transmission thereby of commands to channel 37, so as to enable the register 433 to supply the message stored therein to the channel H (with due respect of the predetermined priorities). From the channel H, as previously described, this message is supplied via the blocks 39,40, 41 in series, having been corrected in parity, the channel C2.

Thus, the preferred apparatus preprocesses the alar, signals from the modules, from the error detectors associated with the transmission channels, from the transit control units' internal alarm detectors, from the detectors associated with the timing means, and from the detectors associated with the space switching network. These alarm signals are processed according to appropriate instructions sent from the central control and, with respect for any predetermined priorities, permit the forming of corresponding messages to be sent to the central control. The preferred apparatus also preprocesses the responses to interrogation messages (or control and/or autocontrol commands) so as to form corresponding messages to be sent, possibly after a predetermined delay, to the central control.

Claims (12)

1. An information management apparatus for managing information about alarm signals and/or response signals to control and/or autocontrol commands relating to a transit network for time division telecommunication systems connected to a switching junction comprising a central control and the transit network, which comprises: a plurality of line units equal in number to the number of PCM systems and each forming an interlace between the transit network and a corresponding PCM system; a switching network connected to the line units and controlled by the central control for performing space-time switching of each PCM channel, the switching network comprising two identical and synchronous sections, each of which comprises a first time switching stage for transferring each PCM sample from the corresponding PCM input channel phase to a work phase allocated by the central control, a space switching stage for the PCM sample, and a second time switching stage for transferring each PCM sample from the work phase to the corresponding output channel phase, the first and second time switching stages comprising a predetermined number of input and output time switching groups and a predetermined number of line units connected to each of the groups; a plurality of group identifying circuits, equal in number to the number of the output time switching groups of each switching section, each of the group identifying circuits being connected to a respective output time switching group of each of the space-time switching sections, and being arranged to detect and signal to the central control any differences between the output signals from the two groups; and at least two identical transit control units providing an interface between the central control and the transit network and arranged to preprocess alarm signals from the members of the transit network before transmission to the central control; the transit network having an equal number of the input and output time switching groups equally divided between the said sections, and a predetermined number of line units connected to the groups, arranged in a module, and further having: at least a first and a second channel for the transit of information, respectively in one direction and the other, between the central control and each transit control unit; at least a third and a fourth channel providing a connection between each transit control unit and one of the modules, for management and control commands sent to the module and for alarm signals and responses coming from the module as a consequence of the control commands; at least two transmission buses for carrying data relating to the junction channels of the transit network and providing a connection between the input time switching groups relating to the module and the space switching stage, and between the space switching stage and the output time switching groups relating to the same module; and at least one channel for carrying commands from each transit control unit to the space switching stage; the apparatus having for each of the modules, first means connected to the third and fourth channels for receiving the alarm signals relating to the module and the responses to control commands, and for each transit control unit, a processing network connected to the second channel and to the channels from as many modules arranged to preprocess signals supplied via the fourth channels, signals from fault controllers relating to the transit control unit, the space switching stage and signals deriving from timing means of the transit network.

2. Apparatus as claimed in claim 1, in which each of the group identifying circuits is of the type com prising: a first comparator connected to two corres ponding output time switching groups belonging to the two switching sections, respectively, and for comparing, bit by bit; the output signals from the groups and for generating a characteristic signal in the event of wrong comparison of at least two corresponding bits relating to an octet; a digital filter connected to the comparator for supplying an error signal when the characteristic signal is repeated for a predetermined number of times; a logic gate whose first input is connected to the output of the digital filter, and whose second input level is connected to a cyclic memory which is connected to the transit control units and is updated by instructions originating from the central control, the cyclic memory being arranged to store as many electrical signals as there are channels in the frame supplied to the first comparator, each of the electrical signals assuming two distinct electrical states respectively enabling or not enabling the corresponding channels to send out an alarm; and a block connected to the output of the logic gate and to the transit control units and arranged to provide two distinct electrical states identifying an alarm or absence of an alarm of at least one channel of the frame, the electrical state for identifying an alarm continuing until the alarm has been acquired by the transit control units, the transit network including: at least one transmitting unit of diagnostic digital samples for each of the input timing groups arranged, under control of the central control, to substitute in an input channel relating to the same group for at least one PCM sample in the channel a diagnostic digital sample, the transmitting unit further being arranged to send a response message to the central control, corrected in parity, containing information for identifying the input channel and for identification, or not, of the same channel, at least one receiving unit for the diagnostic digital samples for each of the output timing groups arranged to be controlled by the central control and to receive, from the output channel dynamically corresponding upon command ofthe central control to the aforesaid input channel, the aforementioned diagnostic digital sample, the receiving unit further being arranged to send a message to the central control, corrected in parity, containing information for recognition, or not, of the diagnostic digital sample, for identifying the aforesaid output channel, and for identification, or not, of the same output channel, the first means comprising: an electrical device with a plurality of inputs connected to the outputs of error detectors of the messages on the third channel and of responses to autocontrol signals relating to the third channel the outputs of a device to which are supplied the outputs of the cyclic memories and of the logic gates relating to a module, the device being arranged to supply upon command of the transit control units the frame relating either to the logic gate orto a cyclic memory of either one of the other group identifying circuit relating to the aforesaid module, terminals relating to a response message of the transmitting unit of an input time switching group of which one channel is concerned with the space time continuity control of a connection, terminals relating to a response message of the receiving unit of an output time switching group of which one channel is concerned with the space-time continuity control of a connection, the output of a signal generator arranged to provide signals for checking by the transit control units for verifying the continuity, or not, of the third channel, the output of a block arranged to supply information relating to master-slave choice alarms of either of the two space-time switching sections, the outputs of supply controllers of the line units associated with the module, the outputs of controllers associated with the PCM systems connected to the line units, the electrical device being arranged with the assistance of associated timing means, to supply a message carrying, in sequence, information relating to the alarm and response signals present at its inputs levels, the apparatus including a data selector connected to the output of the device and to the output of a parity generator, the data selector and the parity generator being arranged to supply the parity corrected message to the fourth channel.

3. An apparatus as claimed in claim 2, in which the block arranged to supply information relating to master-slave choice alarms comprises: a plurality of blocks with at least one thereof for each of the output time switching groups in each module, the blocks being arranged to receive commands from the processing network and to supply at their outputs, which are respectively connected to the corresponding line units of the same module, signals having two distinct electrical states for master-slave designation of the switching sections; a further block arranged to receive the said commands and to sup ply at its output, which is connected to the electrical device, correspondingly the aforesaid two distinct electrical states used for reference; a plurality of comparators having first inputs connected to respective outputs of the plurality of blocks and second inputs connected in parallel to the output of the further block; device and a further device whose inputs are connected to the outputs of the com parators and whose output is connected to the electrical device to supply an alarm signal in the event of erroneous comparison by any of the comparators.

4. An apparatus as claimed in any one of the preceding claims, in which the processing network includes: second processing means for alarm signals from the modules of the transit network for forming, during the transition of the state of the alarms from one frame to the following one relating to one of the modules, a message to be sent to the central control 2 with the permission thereof and according to predetermined priorities; third processing means of response signals to control and/or autocontrol commands of determined members of the network, originating from the modules of the network and from the controllers of the connectors of the messages on the third channel, the third means being arranged to form a response message to be sent to the central control upon command thereof; fourth processing means for alarm signals from the controllers of the connectors of the messages for each module on the third channel, the fourth means being arranged to form a message to be sent to the central control with the permission thereof; fifth processing means for sequences relating to the timing means of the transit network arranged, in the presence of a sequence carrying alarm information, to send the sequence to the central control with the permission thereof; and sixth processing means for alarm signals from the transit control units and from the space switching stage, and arranged to form a message to be sent to the control with the permission thereof and according to any predetermined priorities.

5. An apparatus as claimed in claim 4, in which the second processing means includes: a plurality of comparators for detecting transitions in the states of the alarms, a respective one comparator being provided for each module of the transit network, each comparator having a first input connected to the output of the corresponding first means and a second input connected to a cyclic memory; the cyclic memory 26 which is arranged to store the states of the alarms relating to the alarm frame preceding the alarm frame present at the first input of the comparator, the memory being connected to the central control 2 so as to be auto-updated by the acquisition of the transition of an alarm frame by the central control; a further cyclic memory arranged to be updated by instructions from the central control, and to store a number of electrical signals equal to the number of possible alarm signals contained in a frame, each of the electrical signals assuming two distinct electrical states corresponding to enabling or non-enabling of a corresponding alarm signal; a logic gate having two inputs connected to the outputs, respectively, of the comparator and the memory; a device having a number of inputs equal to the number of the modules, each of the inputs being connected to the output of a corresponding logic gate, the device 29 being arranged, upon activation of any one of its outputs, to output a message of the transition of an alarm state with the indication of the corresponding module, this last indication being present, furthermore, in one of its output channels, a microprogrammed block 30 connected to timing means and activated by the messages from the device for supplying the consequent instructions to an output channel; a device connected to the channel and having a number of inputs equal to the number of the modules, each of the inputs being connected to a corresponding parity controller of the messages from the first means of the corresponding module, the device 24 being arranged to supply to a respective output connected to a block, upon activation of one of its inputs, a parity alarm message with the indication of the address of the corresponding module; a decoder connected to the timing means and arranged to output an operative code for each timing signal supplied by the timing means; a first register with at least four inputs respectively connected to the decoder, the channel, the output of device, and the output of means for supplying further information about the frame involved with a transition of the state of the alarms, the register 33 being arranged to store information at its inputs by means of a first command from the block corresponding to enabling thereof or by means of a second command, which cancels the information previously stored, as a consequence of the activation of the output of the device; a register controlled by the block connected to the output of the first register and arranged to store the priority of the last message sent to the central control; a comparator whose inputs are arranged to receive the priority relating to the message stored in the first register and deduced from the operative code, and the priority stored in the priority register, the comparator being arranged to activate the output connected to the block when the priority of the stored register is higher than the priority in the priority register so as to enable the first register, ordered by the block, to supply the stored message to a channel; a buffer memory activated by the block and arranged to receive from the channel the message from the first register, the memory, in combination with an associated parity generator, being arranged to output the aforesaid message, corrected in parity; and a parallel/series register connected to the memory and arranged to supply the aforementioned message to the second channel connecting the processing network to the central control.

6. An apparatus as claimed in claim 5, in which the third processing means include: at least two devices each having a plurality of inputs connected in an orderly manner to the channels associated to the modules of the transit network, the two devices being connected to respective channels which supply the information relating to the input and output modules concerned with the control and/or autocontrol commands from the processing network; an OR gate connected to the outputs of the two devices and activated by commands from the channel and arranged to output a message containing reply information relating to the control and/or autocontrol commands as well as information regarding the identification of the above-mentioned input and output modules; at least a third register connected to the output of the OR gate and arranged to receive the operative code via a channel, the third register being arranged to store the aforesaid message upon the command of the block and to send the message to the channel; a buffer memory activated by the block 30 and arranged to receive from the channel the aforesaid message from the third register, the memory, in combination with an associated parity generator, being arranged to output the aforesaid message corrected in parity; and a parallel/series register 41 connected to the memory 39 and arranged to supply the aforesaid message, in sequence, to the second channel connecting the processing network to the central control.

7. An apparatus as claimed in claim 5, in which the fourth processing means include: at least two devices each having a plurality of inputs connected in an orderly manner two the channels C4 associated with the transit network modules, the devices being connected to respective channels for supplying information relating to the input and output modules in the event of an error being detected by one of the two detectors associated with the channels C2 of the modules; an OR gate having inputs connected to the outputs of the two devices and arranged to output, with connection to the aforesaid block, a message containing the error signal, relating to an erroneous message, detected by one of the detectors and the indications relating to the input and output modules; at least a second register connected to the outputs of devices the channels and a channel carrying the operative code all flow and arranged to store the aforesaid message, upon command of the block, and to send the message into a channel H upon command of the block; a buffer memory activated by the block, enabled by commands from the central control and arranged to receive from the channel H, the aforesaid message from the second register, the memory, in combination with an associated parity generator, and to output the message, corrected in parity; and a parallel-series register connected to the memory and arranged to supply the aforesaid message, in series to the second channel connecting the processing network to the central control.

8. An apparatus as claimed in claim 6, in which the timing means include three clocks arranged to supply the timing signal, the fifth processing means including: at least two interconnected logic networks connected to the corresponding switching section, each of the networks being connected to the outputs of the clocks and being arranged to supply a sequ ence, received from the block corrected in parity and containing respectively information about the integ rity, or not, of the connection buses with the relative switching network, regarding the optimum function ing or operation of the clocks, and regarding the existence of the clock in the adjacent logic network; at least a fifth register arranged to store the sequ ence; a comparator having one input connected to the output of the fifth register and another input connected to a register for storing a correct sequence relating to the logic networks, the comparator activating the relative output K, connected to the block, in the event of erroneous comparison, the activation of the output K causing the enabling by the block of the fifth register for supplying the sequence stored therein to a channel H; a buffer memory activated by the block and arranged to receive from channel H the aforesaid message from the fifth register, the memory, in combination with an associated parity generator, being arranged to supply the aforementioned message corrected in parity; and a parallel-series register connected to the aforementioned memory and arranged to supply the aforesaid message, in series, to the second channel connecting the processing network to the central control.

9. An apparatus as claimed in claim 5, in which the sixth processing means include: the block arranged to be activated by blocks for detecting parity errors and wrong order of messages respectively on the first channel, by a block for detecting absence of synchronism between the two transit control units, and by blocks for detecting erroneous messages on the third channels connecting the processing network to the corresponding modules of the transit network; means for detecting incongruities or inconsistencies of the commands from the central control of master-slave designation of the switching sections; means for detecting absence or insufficiency of feeding to the transit control units and to the space switching network; at least a fourth register connected to a channel, the outputs of block and of the means, the outputs of which are also connected to the block, and arranged to store, upon command the block, the message of the information reaching it and to send the message to a channel H upon command of the block and with respect to any predetermined priorities; a buffer memory, activated by the block and arranged to receive from channel H the aforementioned message from the fourth register, the memory, in combination with an associated parity generator, being arranged to output the aforementioned message corrected in parity; and a parallel-series register connected to the memory 39 and arranged to supply the aforesaid message, in series to the second channel connecting the processing network to the central control.

10. An information management apparatus substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.

11. An information management apparatus for a transit network of the type controlled by a central control and comprising line units, two transit control units for interfacing PCM systems with the central control, a time-space switching network comprising two identical sections each having equal numbers of input and output time switching groups, a space switching network, and means for comparing and checking output time switching groups being arranged as a plurality of modules, the apparatus comprising means for processing alarms and responses from the modules, alarms and replies relating to control signals from the central control for the modules, and alarms from the transit control units and the space switching stages.

12. Atransit network including an apparatus as claimed in any one of the preceding claims.