GB1468947A - Programme-controlled data switching system - Google Patents

Abstract

1468947 Data exchanges; monitoring and fault diagnosis SIEMENS AG 17 July 1974 [29 Aug 1973] 31558/74 Heading H4P In a programme-controlled data switching system including an arrangement for monitoring and fault diagnosis in communication controllers (UEAS1, UEAS2, Fig. 1, not shown) of a line termination unit (LE) forming part of the sytem, individual devices (VG) detect faults and emit fault signals FA, each communication controller Fig. 2, of a line termination unit (LE) contains a fault collection device FSS which receives individual fault signals FA, forms a fault word describing the fault, and forms fault reaction signals PSS, PVS, FVS, RSA and further contains a diagnosis routine device DR which evaluates a dignosis command, reads out from a diagnosis zone of a central storage unit SE1, SE2 forming part of the system a fault diagnosis programme. The diagnosis routine device DR contains a first decoding circuit OP serving to decode an operation section of the diagnosis command and to form first control signals StS1- StS3 which make it possible to switch through, in the communication controller data channels between a word output register WAR and word input register WER, a fault word register FEWR containing a fault word and an intermediate storing cycle buffer store ZP. The diagnosis routine device DR contains a second decoding circuit BF which is activated via a further first control signal StS4 and which produces second control signals StS5-StS11 by evaluating a command section of the diagnosis command and control circuits and registers of the communication controller may be connected to the word input register WER under the control of in each case one of these second control signals StS5-StS11 for the transfer of the diagnosis command. The fault register FER has fault trigger stages (0-63, Fig. 3, not shown) assigned to individual faults. Fault reaction signals PSS, PVS, FVS and RSA from a fault reaction circuit FSG are fed to the central storage units SE1, SE2 and simultaneously to the above a first internal fault reaction signal is produced which resets the control circuits in the communication controller. A blocking trigger stage SPK may be reversed for the production of a second internal fault reaction signal which blocks cycle selector control ZAWS, the cycle buffer store ZP and an evaluator circuit BW from further activities. The communication controller further includes input and output data devices DE, DA connected to input and output code converters ECW/ACW, a connection register VR, control circuit DSS, a clock UZG and counter stages BSZ, NBZ a subsidiary cycle buffer store shift register NPZ selector circuits AdAW and WAW and registers SSAR AdAR for address information and WAR for word information. A cycle selector control unit ZAWS provides a cycle request signal ZA and receives a cycle acknowledgment signal ZQ. Specifications 1,397,274 and 1,330,040 are referred to.