FI20000292A0 - Testarrangemang och testförfarande - Google Patents
Testarrangemang och testförfarandeInfo
- Publication number
- FI20000292A0 FI20000292A0 FI20000292A FI20000292A FI20000292A0 FI 20000292 A0 FI20000292 A0 FI 20000292A0 FI 20000292 A FI20000292 A FI 20000292A FI 20000292 A FI20000292 A FI 20000292A FI 20000292 A0 FI20000292 A0 FI 20000292A0
- Authority
- FI
- Finland
- Prior art keywords
- test
- arrangement
- test method
- test arrangement
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318555—Control logic
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20000292A FI110034B (sv) | 2000-02-11 | 2000-02-11 | Testarrangemang och testförfarande |
PCT/FI2001/000125 WO2001059466A1 (en) | 2000-02-11 | 2001-02-12 | Testing arrangement and testing method |
EP01907597A EP1272859A1 (en) | 2000-02-11 | 2001-02-12 | Testing arrangement and testing method |
US10/203,183 US20030067314A1 (en) | 2000-02-11 | 2001-02-12 | Testing arrangement and testing method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20000292 | 2000-02-11 | ||
FI20000292A FI110034B (sv) | 2000-02-11 | 2000-02-11 | Testarrangemang och testförfarande |
Publications (3)
Publication Number | Publication Date |
---|---|
FI20000292A0 true FI20000292A0 (sv) | 2000-02-11 |
FI20000292A FI20000292A (sv) | 2001-08-12 |
FI110034B FI110034B (sv) | 2002-11-15 |
Family
ID=8557451
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI20000292A FI110034B (sv) | 2000-02-11 | 2000-02-11 | Testarrangemang och testförfarande |
Country Status (4)
Country | Link |
---|---|
US (1) | US20030067314A1 (sv) |
EP (1) | EP1272859A1 (sv) |
FI (1) | FI110034B (sv) |
WO (1) | WO2001059466A1 (sv) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7149514B1 (en) * | 1997-07-30 | 2006-12-12 | Bellsouth Intellectual Property Corp. | Cellular docking station |
US8554187B2 (en) * | 2002-07-15 | 2013-10-08 | At&T Intellectual Property I, L.P. | Apparatus and method for routing communications between networks and devices |
US8526466B2 (en) * | 2002-07-15 | 2013-09-03 | At&T Intellectual Property I, L.P. | Apparatus and method for prioritizing communications between devices |
US8416804B2 (en) | 2002-07-15 | 2013-04-09 | At&T Intellectual Property I, L.P. | Apparatus and method for providing a user interface for facilitating communications between devices |
US8543098B2 (en) | 2002-07-15 | 2013-09-24 | At&T Intellectual Property I, L.P. | Apparatus and method for securely providing communications between devices and networks |
US8380879B2 (en) | 2002-07-15 | 2013-02-19 | At&T Intellectual Property I, L.P. | Interface devices for facilitating communications between devices and communications networks |
US8533070B2 (en) | 2002-07-15 | 2013-09-10 | At&T Intellectual Property I, L.P. | Apparatus and method for aggregating and accessing data according to user information |
DE10252326A1 (de) * | 2002-11-11 | 2004-05-27 | Infineon Technologies Ag | Elektronisches Element mit einem zu testenden elektronischen Schaltkreis und Testsystem-Anordnung zum Testen des elektronischen Elements |
DE10335809B4 (de) * | 2003-08-05 | 2010-07-01 | Infineon Technologies Ag | Integrierte Schaltung mit einem zu testenden elektronischen Schaltkreis und Testsystem-Anordnung zum Testen der integrierten Schaltung |
WO2009122315A1 (en) * | 2008-03-31 | 2009-10-08 | Nxp B.V. | Integrated circuit with test arrangement, integrated circuit arrangement and text method |
US8558553B2 (en) * | 2008-12-16 | 2013-10-15 | Infineon Technologies Austria Ag | Methods and apparatus for selecting settings for circuits |
US8664921B2 (en) * | 2011-08-04 | 2014-03-04 | Tektronix, Inc. | Means of providing variable reactive load capability on an electronic load |
CN111679650B (zh) * | 2020-06-08 | 2021-06-18 | 中车洛阳机车有限公司 | 一种试验lkj2000型列车运行监控记录装置性能的简易方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI100829B (sv) * | 1991-10-08 | 1998-02-27 | Matti Weissenfelt | Test metod och test apparat |
US5285152A (en) * | 1992-03-23 | 1994-02-08 | Ministar Peripherals International Limited | Apparatus and methods for testing circuit board interconnect integrity |
GB2268277B (en) * | 1992-06-17 | 1995-11-08 | Siemens Plessey Electronic | Improvements in or relating to electronic circuit test apparatus |
GB2278689B (en) * | 1993-06-02 | 1997-03-19 | Ford Motor Co | Method and apparatus for testing integrated circuits |
US5887001A (en) * | 1995-12-13 | 1999-03-23 | Bull Hn Information Systems Inc. | Boundary scan architecture analog extension with direct connections |
US6199182B1 (en) * | 1997-03-27 | 2001-03-06 | Texas Instruments Incorporated | Probeless testing of pad buffers on wafer |
-
2000
- 2000-02-11 FI FI20000292A patent/FI110034B/sv not_active IP Right Cessation
-
2001
- 2001-02-12 EP EP01907597A patent/EP1272859A1/en not_active Withdrawn
- 2001-02-12 WO PCT/FI2001/000125 patent/WO2001059466A1/en not_active Application Discontinuation
- 2001-02-12 US US10/203,183 patent/US20030067314A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20030067314A1 (en) | 2003-04-10 |
EP1272859A1 (en) | 2003-01-08 |
FI110034B (sv) | 2002-11-15 |
FI20000292A (sv) | 2001-08-12 |
WO2001059466A8 (en) | 2001-10-11 |
WO2001059466A1 (en) | 2001-08-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PC | Transfer of assignment of patent |
Owner name: ELEKTROBIT TESTING OY Free format text: ELEKTROBIT TESTING OY |
|
PC | Transfer of assignment of patent |
Owner name: ELEKTROBIT SYSTEM TEST OY Free format text: ELEKTROBIT SYSTEM TEST OY |
|
MM | Patent lapsed |