FI105374B - Kellosignaalien multipleksointipiiri - Google Patents

Kellosignaalien multipleksointipiiri Download PDF

Info

Publication number
FI105374B
FI105374B FI911815A FI911815A FI105374B FI 105374 B FI105374 B FI 105374B FI 911815 A FI911815 A FI 911815A FI 911815 A FI911815 A FI 911815A FI 105374 B FI105374 B FI 105374B
Authority
FI
Finland
Prior art keywords
signal
clock
clock signal
level
circuit
Prior art date
Application number
FI911815A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI911815A0 (fi
FI911815A (fi
Inventor
Vianney Andrieu
Original Assignee
Alcatel Radiotelephone
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Radiotelephone filed Critical Alcatel Radiotelephone
Publication of FI911815A0 publication Critical patent/FI911815A0/fi
Publication of FI911815A publication Critical patent/FI911815A/fi
Application granted granted Critical
Publication of FI105374B publication Critical patent/FI105374B/fi

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Electronic Switches (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
FI911815A 1990-04-18 1991-04-15 Kellosignaalien multipleksointipiiri FI105374B (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9004926A FR2661297B1 (fr) 1990-04-18 1990-04-18 Circuit de multiplexage de signaux d'horloge.
FR9004926 1990-04-18

Publications (3)

Publication Number Publication Date
FI911815A0 FI911815A0 (fi) 1991-04-15
FI911815A FI911815A (fi) 1991-10-19
FI105374B true FI105374B (fi) 2000-07-31

Family

ID=9395837

Family Applications (1)

Application Number Title Priority Date Filing Date
FI911815A FI105374B (fi) 1990-04-18 1991-04-15 Kellosignaalien multipleksointipiiri

Country Status (12)

Country Link
US (1) US5321728A (el)
EP (1) EP0452878B1 (el)
AT (1) ATE116775T1 (el)
AU (1) AU645301B2 (el)
CA (1) CA2040650C (el)
DE (1) DE69106422T2 (el)
DK (1) DK0452878T3 (el)
ES (1) ES2068418T3 (el)
FI (1) FI105374B (el)
FR (1) FR2661297B1 (el)
GR (1) GR3015474T3 (el)
NO (1) NO302390B1 (el)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0533992A1 (de) * 1991-09-27 1993-03-31 Siemens Nixdorf Informationssysteme Aktiengesellschaft Verfahren und Schaltungsanordnung zum Bewerkstelligen synchroner Datentransfers
EP0587944B1 (en) * 1992-09-18 1998-05-20 Alcatel Cell resequencing system for a telecommunication network
EP0634849A1 (en) * 1993-07-13 1995-01-18 ALCATEL BELL Naamloze Vennootschap Signal selection device
JPH0795677A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd シェルフ間の同期用情報と同期クロックの受渡し方法
US5475322A (en) * 1993-10-12 1995-12-12 Wang Laboratories, Inc. Clock frequency multiplying and squaring circuit and method
WO1997020268A1 (en) * 1995-11-27 1997-06-05 Philips Electronics N.V. A parametrizable control module comprising first and second loadables counters, an electronic circuit comprising a plurality of such parametrized control modules, and a method for synthesizing such circuit
US6178186B1 (en) * 1998-03-27 2001-01-23 Motorola, Inc. Fractional decimator with linear interpolation and method thereof
WO2001066610A1 (en) * 2000-03-06 2001-09-13 Bp Chemicals Limited Method for reducing sheeting and agglomerates during olefin polymerisation
TWI256539B (en) * 2004-11-09 2006-06-11 Realtek Semiconductor Corp Apparatus and method for generating a clock signal
US9686762B2 (en) * 2011-03-30 2017-06-20 Tejas Networks Ltd Method and system for multiplexing low frequency clocks to reduce interface count

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538272A (en) * 1983-12-22 1985-08-27 Gte Automatic Electric Incorporated Prioritized clock selection circuit
FR2577087B1 (fr) * 1985-02-07 1987-03-06 Thomson Csf Mat Tel Dispositif de distribution d'horloge tripliquee, chaque signal d'horloge comportant un signal de synchronisation
GB8615399D0 (en) * 1986-06-24 1986-07-30 Int Computers Ltd Switching circuit
US4839907A (en) * 1988-02-26 1989-06-13 American Telephone And Telegraph Company, At&T Bell Laboratories Clock skew correction arrangement
US4899351A (en) * 1988-07-18 1990-02-06 Western Digital Corporation Transient free clock switch logic

Also Published As

Publication number Publication date
GR3015474T3 (en) 1995-06-30
FI911815A0 (fi) 1991-04-15
AU645301B2 (en) 1994-01-13
ES2068418T3 (es) 1995-04-16
US5321728A (en) 1994-06-14
FR2661297B1 (fr) 1993-02-12
FI911815A (fi) 1991-10-19
DE69106422D1 (de) 1995-02-16
DK0452878T3 (da) 1995-05-29
NO911479L (no) 1991-10-21
NO302390B1 (no) 1998-02-23
ATE116775T1 (de) 1995-01-15
DE69106422T2 (de) 1995-05-04
EP0452878B1 (fr) 1995-01-04
NO911479D0 (no) 1991-04-16
FR2661297A1 (fr) 1991-10-25
AU7503091A (en) 1991-10-24
CA2040650C (fr) 1995-07-04
EP0452878A1 (fr) 1991-10-23

Similar Documents

Publication Publication Date Title
FI105374B (fi) Kellosignaalien multipleksointipiiri
US5486783A (en) Method and apparatus for providing clock de-skewing on an integrated circuit board
FI88837B (fi) Frekvensdividering med udda tal och decimaltal
EP0831588A2 (en) Method for synchronizing signals and structures therefor
US5036529A (en) Digital auto-phase-controlled retiming circuit
JPS6161404B2 (el)
FI88567C (fi) En generell synkronisk 2N+1 -divisor
JP2963020B2 (ja) 高速データ伝送におけるデジタルデータリタイミング装置
US20140035636A1 (en) Clock synchronization circuit
EP1884057B1 (en) Data edge-to-clock edge phase detector for high speed circuits
US5103185A (en) Clock jitter suppressing circuit
GB2204467A (en) Method and apparatus for generating a data recovery window
US4698826A (en) Clock repeater for triplicated clock distributor
KR19980078161A (ko) 반도체 메모리 소자의 딜레이 루프 럭크 회로
KR880000676B1 (ko) 입력신호와 발진기의 출력신호의 위상을 동기화시키는 방법 및 장치
US4818894A (en) Method and apparatus for obtaining high frequency resolution of a low frequency signal
US7133483B1 (en) Apparatus and method for a jitter cancellation circuit
US6150861A (en) Flip-flop
JP5378765B2 (ja) データ転送システム
US4327442A (en) Clock recovery device
WO2024198645A1 (zh) 一种在数据链路中提供时钟信号的方法及装置
KR960000541B1 (ko) 폰(pon) 구조를 갖는 광가입자에 대한 데이터 전송을 위한 비트 동기 회로
US6898211B1 (en) Scheme for maintaining synchronization in an inherently asynchronous system
KR101467417B1 (ko) 디지털 동기 회로
SU922709A1 (ru) Устройство дл синхронизации вычислительной системы