AU645301B2 - Clock signal multiplexer circuit - Google Patents

Clock signal multiplexer circuit Download PDF

Info

Publication number
AU645301B2
AU645301B2 AU75030/91A AU7503091A AU645301B2 AU 645301 B2 AU645301 B2 AU 645301B2 AU 75030/91 A AU75030/91 A AU 75030/91A AU 7503091 A AU7503091 A AU 7503091A AU 645301 B2 AU645301 B2 AU 645301B2
Authority
AU
Australia
Prior art keywords
signal
clock signal
selection
circuit
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
AU75030/91A
Other languages
English (en)
Other versions
AU7503091A (en
Inventor
Vianney Andrieu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent NV
Original Assignee
Alcatel NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel NV filed Critical Alcatel NV
Publication of AU7503091A publication Critical patent/AU7503091A/en
Application granted granted Critical
Publication of AU645301B2 publication Critical patent/AU645301B2/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Electronic Switches (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
AU75030/91A 1990-04-18 1991-04-16 Clock signal multiplexer circuit Ceased AU645301B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9004926 1990-04-11
FR9004926A FR2661297B1 (fr) 1990-04-18 1990-04-18 Circuit de multiplexage de signaux d'horloge.

Publications (2)

Publication Number Publication Date
AU7503091A AU7503091A (en) 1991-10-24
AU645301B2 true AU645301B2 (en) 1994-01-13

Family

ID=9395837

Family Applications (1)

Application Number Title Priority Date Filing Date
AU75030/91A Ceased AU645301B2 (en) 1990-04-18 1991-04-16 Clock signal multiplexer circuit

Country Status (12)

Country Link
US (1) US5321728A (el)
EP (1) EP0452878B1 (el)
AT (1) ATE116775T1 (el)
AU (1) AU645301B2 (el)
CA (1) CA2040650C (el)
DE (1) DE69106422T2 (el)
DK (1) DK0452878T3 (el)
ES (1) ES2068418T3 (el)
FI (1) FI105374B (el)
FR (1) FR2661297B1 (el)
GR (1) GR3015474T3 (el)
NO (1) NO302390B1 (el)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0533992A1 (de) * 1991-09-27 1993-03-31 Siemens Nixdorf Informationssysteme Aktiengesellschaft Verfahren und Schaltungsanordnung zum Bewerkstelligen synchroner Datentransfers
DE69225592T2 (de) * 1992-09-18 1998-09-10 Alsthom Cge Alcatel System zur Wiederherstellung der Zellenreihenfolge für ein Telekommunikationsnetzwerk
EP0634849A1 (en) * 1993-07-13 1995-01-18 ALCATEL BELL Naamloze Vennootschap Signal selection device
JPH0795677A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd シェルフ間の同期用情報と同期クロックの受渡し方法
US5475322A (en) * 1993-10-12 1995-12-12 Wang Laboratories, Inc. Clock frequency multiplying and squaring circuit and method
EP0806007B1 (en) * 1995-11-27 2002-02-20 Koninklijke Philips Electronics N.V. A parametrizable control module comprising first and second loadables counters, an electronic circuit comprising a plurality of such parametrized control modules, and a method for synthesizing such circuit
US6178186B1 (en) * 1998-03-27 2001-01-23 Motorola, Inc. Fractional decimator with linear interpolation and method thereof
AU3584701A (en) * 2000-03-06 2001-09-17 Bp Chem Int Ltd Method for reducing sheeting and agglomerates during olefin polymerisation
TWI256539B (en) * 2004-11-09 2006-06-11 Realtek Semiconductor Corp Apparatus and method for generating a clock signal
US9686762B2 (en) * 2011-03-30 2017-06-20 Tejas Networks Ltd Method and system for multiplexing low frequency clocks to reduce interface count

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538272A (en) * 1983-12-22 1985-08-27 Gte Automatic Electric Incorporated Prioritized clock selection circuit
EP0254406A2 (en) * 1986-06-24 1988-01-27 Amt(Holdings) Limited Switching circuit for clock signals
US4899351A (en) * 1988-07-18 1990-02-06 Western Digital Corporation Transient free clock switch logic

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2577087B1 (fr) * 1985-02-07 1987-03-06 Thomson Csf Mat Tel Dispositif de distribution d'horloge tripliquee, chaque signal d'horloge comportant un signal de synchronisation
US4839907A (en) * 1988-02-26 1989-06-13 American Telephone And Telegraph Company, At&T Bell Laboratories Clock skew correction arrangement

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538272A (en) * 1983-12-22 1985-08-27 Gte Automatic Electric Incorporated Prioritized clock selection circuit
EP0254406A2 (en) * 1986-06-24 1988-01-27 Amt(Holdings) Limited Switching circuit for clock signals
US4899351A (en) * 1988-07-18 1990-02-06 Western Digital Corporation Transient free clock switch logic

Also Published As

Publication number Publication date
US5321728A (en) 1994-06-14
ATE116775T1 (de) 1995-01-15
FR2661297A1 (fr) 1991-10-25
DE69106422D1 (de) 1995-02-16
FR2661297B1 (fr) 1993-02-12
CA2040650C (fr) 1995-07-04
FI105374B (fi) 2000-07-31
EP0452878A1 (fr) 1991-10-23
NO911479D0 (no) 1991-04-16
ES2068418T3 (es) 1995-04-16
DE69106422T2 (de) 1995-05-04
FI911815A (fi) 1991-10-19
EP0452878B1 (fr) 1995-01-04
FI911815A0 (fi) 1991-04-15
AU7503091A (en) 1991-10-24
GR3015474T3 (en) 1995-06-30
DK0452878T3 (da) 1995-05-29
NO911479L (no) 1991-10-21
NO302390B1 (no) 1998-02-23

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