ES8602271A1 - Circuito de multiplicacion para multiplicadores de gran velocidad en el sistema de un ordenador - Google Patents

Circuito de multiplicacion para multiplicadores de gran velocidad en el sistema de un ordenador

Info

Publication number
ES8602271A1
ES8602271A1 ES539052A ES539052A ES8602271A1 ES 8602271 A1 ES8602271 A1 ES 8602271A1 ES 539052 A ES539052 A ES 539052A ES 539052 A ES539052 A ES 539052A ES 8602271 A1 ES8602271 A1 ES 8602271A1
Authority
ES
Spain
Prior art keywords
carry
function
generation
propagation
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES539052A
Other languages
English (en)
Other versions
ES539052A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP58247392A external-priority patent/JPS60136831A/ja
Priority claimed from JP25192483A external-priority patent/JPH0227686B2/ja
Priority claimed from JP59024135A external-priority patent/JPS60168235A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of ES539052A0 publication Critical patent/ES539052A0/es
Publication of ES8602271A1 publication Critical patent/ES8602271A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/527—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel
    • G06F7/5272—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products
    • G06F7/5275—Multiplying only in serial-parallel fashion, i.e. one operand being entered serially and the other in parallel with row wise addition of partial products using carry save adders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Quality & Reliability (AREA)
  • Complex Calculations (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

CIRCUITO DE MULTIPLICACION PARA MULTIPLICADORES DE GRAN VELOCIDAD EN EL SISTEMA DE UN ORDENADOR. COMPRENDE UN MULTIPLICADOR (1) Y UNA SUMADORA DE PROPAGACION DE ACARREO (2), DONDE EL MULTIPLICADOR TIENE UNA SUMA (S) Y ACARREO (C) POR CADA BITIO UTILIZANDO ARBOLES DE SUMADORAS (CSA) CON RETENCION DE ACARREO QUE TIENEN UNA PLURALIDAD DE SUMADORAS CON RETENCION DE ACARREO, Y GENERA UNA FUNCION DE GENERACION DE ACARREO Y UNA FUNCION DE PROPAGACION DE ACARREO EN BASE DE LA SUMA Y EL ACARREO UTILIZANDO UNA UNIDAD DE GENERACION/PROPAGACION (GP20), DONDE LA SUMADORA DE PROPAGACION DE ACARREO OBTIENE UN PRODUCTO FINAL EN BASE DE LA FUNCION DE GENERACION DE CARREO Y LA FUNCION DE PROPAGACION DE ACARREO.
ES539052A 1983-12-26 1984-12-26 Circuito de multiplicacion para multiplicadores de gran velocidad en el sistema de un ordenador Expired ES8602271A1 (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP58247392A JPS60136831A (ja) 1983-12-26 1983-12-26 レシデユ−生成回路
JP25192483A JPH0227686B2 (ja) 1983-12-27 1983-12-27 Jozankairo
JP59024135A JPS60168235A (ja) 1984-02-10 1984-02-10 乗算器チエツク方式

Publications (2)

Publication Number Publication Date
ES539052A0 ES539052A0 (es) 1985-11-16
ES8602271A1 true ES8602271A1 (es) 1985-11-16

Family

ID=27284521

Family Applications (1)

Application Number Title Priority Date Filing Date
ES539052A Expired ES8602271A1 (es) 1983-12-26 1984-12-26 Circuito de multiplicacion para multiplicadores de gran velocidad en el sistema de un ordenador

Country Status (8)

Country Link
US (1) US4727507A (es)
EP (1) EP0147296B1 (es)
KR (1) KR900000477B1 (es)
AU (1) AU550740B2 (es)
BR (1) BR8406677A (es)
CA (1) CA1232072A (es)
DE (1) DE3485535D1 (es)
ES (1) ES8602271A1 (es)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6347874A (ja) * 1986-08-16 1988-02-29 Nec Corp 算術演算装置
US4989168A (en) * 1987-11-30 1991-01-29 Fujitsu Limited Multiplying unit in a computer system, capable of population counting
US5283755A (en) * 1993-04-14 1994-02-01 International Business Machines Corporation Multiplier employing carry select or carry look-ahead adders in hierarchical tree configuration
US5636155A (en) * 1993-04-27 1997-06-03 Matsushita Electric Industrial Co., Ltd. Arithmetic processor and arithmetic method
US5684731A (en) * 1995-08-31 1997-11-04 National Semiconductor Corporation Booth multiplier using data path width adder for efficient carry save addition
US5847981A (en) * 1997-09-04 1998-12-08 Motorola, Inc. Multiply and accumulate circuit
US7543713B2 (en) * 2001-04-19 2009-06-09 Graham Packaging Company L.P. Multi-functional base for a plastic, wide-mouth, blow-molded container
US6763367B2 (en) * 2000-12-11 2004-07-13 International Business Machines Corporation Pre-reduction technique within a multiplier/accumulator architecture
US6917956B2 (en) * 2001-08-14 2005-07-12 Sun Microsystems, Inc. Apparatus and method for efficient modular exponentiation
GB2396708B (en) * 2002-12-05 2006-06-21 Micron Technology Inc Hybrid arithmetic logic unit

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3840727A (en) * 1972-10-30 1974-10-08 Amdahl Corp Binary multiplication by addition with non-verlapping multiplier recording
US4041292A (en) * 1975-12-22 1977-08-09 Honeywell Information Systems Inc. High speed binary multiplication system employing a plurality of multiple generator circuits

Also Published As

Publication number Publication date
ES539052A0 (es) 1985-11-16
KR900000477B1 (en) 1990-01-30
EP0147296B1 (en) 1992-03-04
DE3485535D1 (de) 1992-04-09
EP0147296A3 (en) 1988-01-20
EP0147296A2 (en) 1985-07-03
KR850004819A (ko) 1985-07-27
CA1232072A (en) 1988-01-26
AU550740B2 (en) 1986-04-10
BR8406677A (pt) 1985-10-22
US4727507A (en) 1988-02-23
AU3685684A (en) 1985-07-04

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