ES8205485A1 - Un metodo para sincronizar una senal entrante de datos con una senal de sincronismo local asincrona disponible en un re-ceptor. - Google Patents

Un metodo para sincronizar una senal entrante de datos con una senal de sincronismo local asincrona disponible en un re-ceptor.

Info

Publication number
ES8205485A1
ES8205485A1 ES500229A ES500229A ES8205485A1 ES 8205485 A1 ES8205485 A1 ES 8205485A1 ES 500229 A ES500229 A ES 500229A ES 500229 A ES500229 A ES 500229A ES 8205485 A1 ES8205485 A1 ES 8205485A1
Authority
ES
Spain
Prior art keywords
message
data signal
clock signal
condition
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES500229A
Other languages
English (en)
Other versions
ES500229A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of ES500229A0 publication Critical patent/ES500229A0/es
Publication of ES8205485A1 publication Critical patent/ES8205485A1/es
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

PROCEDIMIENTO Y DISPOSISTIVO PARA SINCRONIZAR UNA SEÑAL DE DATOS BINARIOS CON UNA SEÑAL DE SINCRONISMO DISPUESTA LOCALMENTE EN UN RECEPTOR. POR MEDIO DE UN PRIMER CIRCUITO DE MUESTREO (1), SE REALIZA UNA SINCRONIZACION ENTRE LA SEÑAL DE DATOS (4) Y LA SEÑAL DE SINCRONISMO (5) DESFASADA 180 EN UN INVERSOR (3), CUANDO LOS FLANCOS DE AMBAS TIENDEN A COINCIDIR. LA SEÑAL RESULTANTE SE SINCRONIZA NUEVAMENTE, EN UN SEGUNDO CIRCUITO DE MUESTREO (2), CON LA SEÑAL DE SINCRONISMO NO CORREGIDA. EXISTEN DIFERENTES ALTERNATIVAS DE REALIZACION EN CUANTO A LOS CIRCUITOS DE MUESTREO SE REFIERE.
ES500229A 1980-03-11 1981-03-10 Un metodo para sincronizar una senal entrante de datos con una senal de sincronismo local asincrona disponible en un re-ceptor. Expired ES8205485A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8001910A SE422263B (sv) 1980-03-11 1980-03-11 Forfarande och anordning for synkronisering av en biner datasignal

Publications (2)

Publication Number Publication Date
ES500229A0 ES500229A0 (es) 1982-06-01
ES8205485A1 true ES8205485A1 (es) 1982-06-01

Family

ID=20340485

Family Applications (1)

Application Number Title Priority Date Filing Date
ES500229A Expired ES8205485A1 (es) 1980-03-11 1981-03-10 Un metodo para sincronizar una senal entrante de datos con una senal de sincronismo local asincrona disponible en un re-ceptor.

Country Status (15)

Country Link
US (1) US4464769A (es)
JP (1) JPS57500269A (es)
CA (1) CA1169945A (es)
CH (1) CH656037A5 (es)
DK (1) DK152474C (es)
ES (1) ES8205485A1 (es)
FI (1) FI65152C (es)
FR (1) FR2478410B1 (es)
GB (1) GB2091975B (es)
IT (1) IT1197402B (es)
NL (1) NL189022C (es)
NO (1) NO152435C (es)
NZ (1) NZ196414A (es)
SE (1) SE422263B (es)
WO (1) WO1981002654A1 (es)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4544850A (en) * 1983-12-05 1985-10-01 Gte Automatic Electric Incorporated Race condition mediator circuit
US4534026A (en) * 1983-12-06 1985-08-06 Paradyne Corporation Normalized error compensator for modems using radial amplitude modulation for multiplexing
FR2604043B1 (fr) * 1986-09-17 1993-04-09 Cit Alcatel Dispositif de recalage d'un ou plusieurs trains de donnees binaires de debits identiques ou sous-multiples sur un signal de reference d'horloge synchrone
WO2002062004A1 (en) * 2001-02-01 2002-08-08 Vitesse Semiconductor Corporation Rz recovery
JP2006332945A (ja) * 2005-05-25 2006-12-07 Nec Electronics Corp 半導体集積回路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6513602A (es) * 1965-10-21 1967-04-24
US3631463A (en) * 1969-03-10 1971-12-28 Sperry Rand Corp Self-clocked encoding scheme
US3697881A (en) * 1969-07-10 1972-10-10 Kokusai Denshin Denwa Co Ltd Phase detection system for at least one digital phase-modulated wave
GB1265530A (es) * 1969-08-30 1972-03-01 Marconi Co Ltd
US3920918A (en) * 1974-06-06 1975-11-18 L M Ericsson Pty Lid Pulse edge coincidence detection circuit for digital data transmission using diphase data sync
US3936602A (en) * 1974-10-23 1976-02-03 Northern Electric Company Limited Full duplex data transmission system using two speeds of diphase signal for simplified sync
US4010323A (en) * 1975-10-29 1977-03-01 Bell Telephone Laboratories, Incorporated Digital timing recovery
CA1081364A (en) * 1976-09-28 1980-07-08 Shuichi Samejima Differential detection systems with non-redundant error correction
JPS5451709A (en) * 1977-10-03 1979-04-23 Fujitsu Ltd Bit phase synchronizing circuit
JPS5451710A (en) * 1977-10-03 1979-04-23 Fujitsu Ltd Bit phase synchronizing circuit
US4208724A (en) * 1977-10-17 1980-06-17 Sperry Corporation System and method for clocking data between a remote unit and a local unit
DE2836422C2 (de) * 1978-08-19 1986-01-02 ANT Nachrichtentechnik GmbH, 7150 Backnang Synchronisierverfahren und -anordnung

Also Published As

Publication number Publication date
DK152474B (da) 1988-02-29
SE8001910L (sv) 1981-09-12
US4464769A (en) 1984-08-07
JPS57500269A (es) 1982-02-12
SE422263B (sv) 1982-02-22
NL8120071A (nl) 1982-07-01
NO152435C (no) 1985-09-25
NL189022C (nl) 1992-12-01
WO1981002654A1 (en) 1981-09-17
FR2478410A1 (fr) 1981-09-18
FI821193L (fi) 1982-04-05
FI65152C (fi) 1984-03-12
DK152474C (da) 1988-08-01
FI65152B (fi) 1983-11-30
ES500229A0 (es) 1982-06-01
NO813669L (no) 1981-10-29
CA1169945A (en) 1984-06-26
CH656037A5 (de) 1986-05-30
NL189022B (nl) 1992-07-01
IT1197402B (it) 1988-11-30
FI821193A0 (fi) 1982-04-05
NZ196414A (en) 1984-03-16
IT8120278A0 (it) 1981-03-11
NO152435B (no) 1985-06-17
FR2478410B1 (fr) 1985-01-25
GB2091975A (en) 1982-08-04
GB2091975B (en) 1984-10-10
DK497381A (da) 1981-11-10

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