ES536759A0 - Un circuito oscilador controlado, para usarse especialmente en bucles enganchados en fase - Google Patents

Un circuito oscilador controlado, para usarse especialmente en bucles enganchados en fase

Info

Publication number
ES536759A0
ES536759A0 ES536759A ES536759A ES536759A0 ES 536759 A0 ES536759 A0 ES 536759A0 ES 536759 A ES536759 A ES 536759A ES 536759 A ES536759 A ES 536759A ES 536759 A0 ES536759 A0 ES 536759A0
Authority
ES
Spain
Prior art keywords
loopes
controlled oscillator
oscillator circuit
used especially
phase engaged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES536759A
Other languages
English (en)
Other versions
ES8506952A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of ES8506952A1 publication Critical patent/ES8506952A1/es
Publication of ES536759A0 publication Critical patent/ES536759A0/es
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L5/00—Automatic control of voltage, current, or power
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses
ES536759A 1983-10-17 1984-10-15 Un circuito oscilador controlado, para usarse especialmente en bucles enganchados en fase Granted ES536759A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8303561A NL8303561A (nl) 1983-10-17 1983-10-17 Geregelde oscillatorschakeling.

Publications (2)

Publication Number Publication Date
ES8506952A1 ES8506952A1 (es) 1985-08-01
ES536759A0 true ES536759A0 (es) 1985-08-01

Family

ID=19842568

Family Applications (1)

Application Number Title Priority Date Filing Date
ES536759A Granted ES536759A0 (es) 1983-10-17 1984-10-15 Un circuito oscilador controlado, para usarse especialmente en bucles enganchados en fase

Country Status (9)

Country Link
US (1) US4568887A (es)
EP (1) EP0138276B1 (es)
JP (1) JPH0740667B2 (es)
KR (1) KR920010214B1 (es)
DE (1) DE3469331D1 (es)
ES (1) ES536759A0 (es)
HK (1) HK84591A (es)
NL (1) NL8303561A (es)
SG (1) SG49490G (es)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3676870D1 (de) * 1985-04-22 1991-02-21 Csk Corp Binaeres kodierverfahren fuer daten, welche von einer optischen platte gelesen werden und geraet dafuer.
NL8502802A (nl) * 1985-10-14 1987-05-04 Philips Nv Inrichting voor het uitlezen en/of inschrijven van een optische spoorvormige informatiestruktuur.
GB2197553A (en) * 1986-10-07 1988-05-18 Western Digital Corp Phase-locked loop delay line
JPH07118166B2 (ja) * 1987-05-21 1995-12-18 パイオニア株式会社 トラッキング回路
DE3810809A1 (de) * 1988-03-30 1989-10-12 Fev Motorentech Gmbh & Co Kg Verfahren zur phasengekoppelten frequenzumsetzung
GB2234371A (en) * 1989-07-07 1991-01-30 Inmos Ltd Clock generation
US6150855A (en) * 1990-02-06 2000-11-21 Bull, S.A. Phase-locked loop and resulting frequency multiplier
US5159205A (en) * 1990-10-24 1992-10-27 Burr-Brown Corporation Timing generator circuit including adjustable tapped delay line within phase lock loop to control timing of signals in the tapped delay line
JPH07142997A (ja) * 1990-11-29 1995-06-02 Internatl Business Mach Corp <Ibm> ディレイ・ライン較正回路
DE69204144T2 (de) * 1991-11-25 1996-03-21 Philips Electronics Nv Phasenregelschleife mit Frequenzabweichungsdetektor und Decodierschaltung mit einer solchen Phasenregelschleife.
DE10057905A1 (de) * 2000-11-21 2002-06-06 Micronas Gmbh Phasenregelkreis mit Verzögerungselement
DE60209774T2 (de) * 2001-11-30 2006-11-02 Koninklijke Philips Electronics N.V. Bitdetektionsanordnung und vorrichtung zur wiedergabe von informationen

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1601909A (es) * 1968-12-27 1970-09-21
FR2448257A1 (fr) * 1979-02-05 1980-08-29 Trt Telecom Radio Electr Dispositif de resynchronisation rapide d'une horloge

Also Published As

Publication number Publication date
EP0138276B1 (en) 1988-02-10
ES8506952A1 (es) 1985-08-01
DE3469331D1 (en) 1988-03-17
EP0138276A3 (en) 1985-06-19
NL8303561A (nl) 1985-05-17
EP0138276A2 (en) 1985-04-24
JPS60103731A (ja) 1985-06-08
SG49490G (en) 1990-08-31
KR850003091A (ko) 1985-05-28
US4568887A (en) 1986-02-04
KR920010214B1 (ko) 1992-11-21
JPH0740667B2 (ja) 1995-05-01
HK84591A (en) 1991-11-01

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001