ES485179A1 - Un sistema de ordenador - Google Patents

Un sistema de ordenador

Info

Publication number
ES485179A1
ES485179A1 ES485179A ES485179A ES485179A1 ES 485179 A1 ES485179 A1 ES 485179A1 ES 485179 A ES485179 A ES 485179A ES 485179 A ES485179 A ES 485179A ES 485179 A1 ES485179 A1 ES 485179A1
Authority
ES
Spain
Prior art keywords
input
output
functional
incidents
page
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES485179A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES485179A1 publication Critical patent/ES485179A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

Un sistema de ordenador que tiene memoria virtual subdividida en páginas, una memoria direccionable para almacenar un bloque de incidencias de entrada salida, una unidad central de tratamiento para recuperar incidencias de entrada salida del bloque de incidencias de entrada salida y para tratar dichas incidencias de entrada salida, una pluralidad de adaptadores conectados para controlar dispositivos de entrada salida y un canal que conecta la pluralidad de adaptadores de entrada salida a la unidad CPU y a la memoria, caracterizado por la mejora consistente en: medios bajo control de los adaptadores de entrada salida para solicitar que una página virtual particular quede disponible en la memoria direccionable, especificando dichos medios información funcional de canal e información de dirección virtual para la página solicitada; medios que responden a los medios de solicitud de página para formar una incidencia funcional de solicitud de página que incorpora la información funcional de canaly la información de dirección virtual, y medios para almacenar la incidencia funcional de solicitud de página formada en el bloque de incidencias de entrada salida.
ES485179A 1978-10-23 1979-10-19 Un sistema de ordenador Expired ES485179A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/953,656 US4231088A (en) 1978-10-23 1978-10-23 Allocating and resolving next virtual pages for input/output

Publications (1)

Publication Number Publication Date
ES485179A1 true ES485179A1 (es) 1980-06-16

Family

ID=25494340

Family Applications (1)

Application Number Title Priority Date Filing Date
ES485179A Expired ES485179A1 (es) 1978-10-23 1979-10-19 Un sistema de ordenador

Country Status (7)

Country Link
US (1) US4231088A (es)
EP (1) EP0010192B1 (es)
JP (1) JPS5558881A (es)
AU (1) AU534577B2 (es)
BR (1) BR7906736A (es)
DE (1) DE2964218D1 (es)
ES (1) ES485179A1 (es)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320456A (en) * 1980-01-18 1982-03-16 International Business Machines Corporation Control apparatus for virtual address translation unit
US4520441A (en) * 1980-12-15 1985-05-28 Hitachi, Ltd. Data processing system
US4577274A (en) * 1983-07-11 1986-03-18 At&T Bell Laboratories Demand paging scheme for a multi-ATB shared memory processing system
EP0156989B1 (de) * 1984-04-06 1987-09-09 Siemens Aktiengesellschaft Verfahren und Anordnung zur zeitgerechten Bereitstellung von reellen Speicheradressen für den direkten Zugriff zum Hauptspeicher durch periphere Geräte in einer Datenverarbeitungsanlage
US4677546A (en) * 1984-08-17 1987-06-30 Signetics Guarded regions for controlling memory access
JPH0656594B2 (ja) * 1985-05-07 1994-07-27 株式会社日立製作所 ベクトルプロセツサ
JP2636212B2 (ja) * 1985-05-27 1997-07-30 株式会社日立製作所 磁気デイスク装置
US4833604A (en) * 1986-01-13 1989-05-23 International Business Machines Corporation Method for the relocation of linked control blocks
JPH0644251B2 (ja) * 1986-08-28 1994-06-08 日本電気株式会社 デ−タ処理装置
US5127094A (en) * 1987-11-09 1992-06-30 Hitachi, Ltd. Virtual storage type computer system
JPH0291747A (ja) * 1988-09-29 1990-03-30 Hitachi Ltd 情報処理装置
US5125086A (en) * 1989-06-29 1992-06-23 Digital Equipment Corporation Virtual memory paging apparatus with variable size in-page clusters
DE68926043T2 (de) * 1989-07-20 1996-08-22 Toshiba Kawasaki Kk Mehrprozessor-Computersystem
US5269009A (en) * 1990-09-04 1993-12-07 International Business Machines Corporation Processor system with improved memory transfer means
US5559980A (en) * 1993-03-18 1996-09-24 Lucent Technologies Inc. Method and apparatus for detecting references to deallocated memory in a dynamic memory allocation system
US7093034B2 (en) * 2003-11-18 2006-08-15 Microsoft Corporation Method and apparatus for input management having a plurality of input provider types wherein staging area holds and allows access by external components
CN114896900B (zh) * 2022-07-15 2022-09-30 中国地质大学（武汉） 一种目标跟踪系统

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3786427A (en) * 1971-06-29 1974-01-15 Ibm Dynamic address translation reversed
US3839706A (en) * 1973-07-02 1974-10-01 Ibm Input/output channel relocation storage protect mechanism
US3976977A (en) * 1975-03-26 1976-08-24 Honeywell Information Systems, Inc. Processor for input-output processing system
US4092715A (en) * 1976-09-22 1978-05-30 Honeywell Information Systems Inc. Input-output unit having extended addressing capability

Also Published As

Publication number Publication date
AU534577B2 (en) 1984-02-09
EP0010192A1 (en) 1980-04-30
BR7906736A (pt) 1980-06-17
EP0010192B1 (en) 1982-12-08
US4231088A (en) 1980-10-28
AU5188079A (en) 1980-05-15
JPS5558881A (en) 1980-05-01
JPS5732429B2 (es) 1982-07-10
DE2964218D1 (en) 1983-01-13

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Legal Events

Date Code Title Description
MM4A Patent lapsed

Effective date: 19960401