ES424731A1 - Procedimiento y dispositivo para tener en cuenta las modi- ficaciones dinamicas de un programa. - Google Patents

Procedimiento y dispositivo para tener en cuenta las modi- ficaciones dinamicas de un programa.

Info

Publication number
ES424731A1
ES424731A1 ES424731A ES424731A ES424731A1 ES 424731 A1 ES424731 A1 ES 424731A1 ES 424731 A ES424731 A ES 424731A ES 424731 A ES424731 A ES 424731A ES 424731 A1 ES424731 A1 ES 424731A1
Authority
ES
Spain
Prior art keywords
control apparatus
computer instruction
instruction control
address
program
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES424731A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Publication of ES424731A1 publication Critical patent/ES424731A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
  • Debugging And Monitoring (AREA)
ES424731A 1973-04-13 1974-03-28 Procedimiento y dispositivo para tener en cuenta las modi- ficaciones dinamicas de un programa. Expired ES424731A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7313502A FR2226079A5 (es) 1973-04-13 1973-04-13

Publications (1)

Publication Number Publication Date
ES424731A1 true ES424731A1 (es) 1976-06-01

Family

ID=9117949

Family Applications (1)

Application Number Title Priority Date Filing Date
ES424731A Expired ES424731A1 (es) 1973-04-13 1974-03-28 Procedimiento y dispositivo para tener en cuenta las modi- ficaciones dinamicas de un programa.

Country Status (7)

Country Link
US (1) US4040030A (es)
JP (1) JPS5028248A (es)
DE (1) DE2417578C2 (es)
ES (1) ES424731A1 (es)
FR (1) FR2226079A5 (es)
GB (1) GB1470102A (es)
IT (1) IT1009827B (es)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4112495A (en) * 1977-02-09 1978-09-05 Texas Instruments Incorporated Electronic calculator or microprocessor having a selectively loadable instruction register
US4155120A (en) * 1977-12-01 1979-05-15 Burroughs Corporation Apparatus and method for controlling microinstruction sequencing by selectively inhibiting microinstruction execution
JPS54107645A (en) * 1978-02-13 1979-08-23 Hitachi Ltd Information processor
US4287561A (en) * 1978-03-16 1981-09-01 International Business Machines Corporation Address formulation interlock mechanism
US4298927A (en) * 1978-10-23 1981-11-03 International Business Machines Corporation Computer instruction prefetch circuit
US4316244A (en) * 1978-11-08 1982-02-16 Data General Corporation Memory apparatus for digital computer system
US4253147A (en) * 1979-04-09 1981-02-24 Rockwell International Corporation Memory unit with pipelined cycle of operations
US4292674A (en) * 1979-07-27 1981-09-29 Sperry Corporation One word buffer memory system
DE2937777C2 (de) * 1979-09-19 1982-04-08 Ibm Deutschland Gmbh, 7000 Stuttgart Steuereinrichtung in einer elektronischen Datenverarbeitungsanlage zur Programmunterbrechung und für die Durchführung erzwungener Operationen
JPS57185545A (en) * 1981-05-11 1982-11-15 Hitachi Ltd Information processor
EP0411679B1 (en) * 1982-08-23 1996-05-01 Western Electric Company, Incorporated Apparatus for dynamically adding a next address field to the instructions of a computer system.
US4635194A (en) * 1983-05-02 1987-01-06 International Business Machines Corporation Instruction buffer bypass apparatus
US4896259A (en) * 1984-09-07 1990-01-23 International Business Machines Corporation Apparatus for storing modifying data prior to selectively storing data to be modified into a register
US4691277A (en) * 1984-10-24 1987-09-01 International Business Machines Corp. Small instruction cache using branch target table to effect instruction prefetch
US4761731A (en) * 1985-08-14 1988-08-02 Control Data Corporation Look-ahead instruction fetch control for a cache memory
US5237667A (en) * 1987-06-05 1993-08-17 Mitsubishi Denki Kabushiki Kaisha Digital signal processor system having host processor for writing instructions into internal processor memory
JP2808774B2 (ja) * 1990-01-11 1998-10-08 松下電器産業株式会社 薄膜磁気ヘッド

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3559183A (en) * 1968-02-29 1971-01-26 Ibm Instruction sequence control
US3577190A (en) * 1968-06-26 1971-05-04 Ibm Apparatus in a digital computer for allowing the skipping of predetermined instructions in a sequence of instructions, in response to the occurrence of certain conditions
US3644900A (en) * 1968-11-30 1972-02-22 Tokyo Shibaura Electric Co Data-processing device
US3553655A (en) * 1969-03-28 1971-01-05 Ibm Short forward conditional skip hardware
US3736567A (en) * 1971-09-08 1973-05-29 Bunker Ramo Program sequence control
BE789583A (fr) * 1971-10-01 1973-02-01 Sanders Associates Inc Appareil de controle de programme pour machine de traitement del'information

Also Published As

Publication number Publication date
IT1009827B (it) 1976-12-20
GB1470102A (en) 1977-04-14
JPS5028248A (es) 1975-03-22
DE2417578C2 (de) 1984-08-09
US4040030A (en) 1977-08-02
FR2226079A5 (es) 1974-11-08
DE2417578A1 (de) 1974-10-31

Similar Documents

Publication Publication Date Title
ES424731A1 (es) Procedimiento y dispositivo para tener en cuenta las modi- ficaciones dinamicas de un programa.
ES332386A1 (es) Una disposicion para tratamientos de datos.
GB1263742A (en) Data storage control apparatus for a multiprogrammed data processing system
JPS54107645A (en) Information processor
ES444377A1 (es) Un aparato de tratamiento de datos.
GB1443971A (en) Computer system with programme-controlled programme counters
JPS53113446A (en) Information processor and its method
JPS57109055A (en) Readout control system for microinstruction
JPS57189398A (en) Control system for memory system
JPS5229131A (en) Storage protection unit for counter-channel input & output device
JPS5452936A (en) Memroy processor
JPS53107240A (en) Control system of register memory
JPS57143640A (en) Data processing device
JPS57169858A (en) Data processor
JPS5430742A (en) Memory control system
JPS5515520A (en) Automatic micro cash control system
JPS55124847A (en) Data processor
JPS5533282A (en) Buffer control system
ES432949A1 (es) Un sistema de proceso de datos.
JPS5239326A (en) Control unit
JPS5616252A (en) Tracer for logical operation
JPS54124644A (en) Data transfer system
JPS57113170A (en) Interprocessor control circuit
JPS56124199A (en) Data processing device
FR2253424A5 (en) Memory address system for data protection - has predetermined limit and two memories with replacement system for first memory by second