FR2253424A5 - Memory address system for data protection - has predetermined limit and two memories with replacement system for first memory by second - Google Patents

Memory address system for data protection - has predetermined limit and two memories with replacement system for first memory by second

Info

Publication number
FR2253424A5
FR2253424A5 FR7342703A FR7342703A FR2253424A5 FR 2253424 A5 FR2253424 A5 FR 2253424A5 FR 7342703 A FR7342703 A FR 7342703A FR 7342703 A FR7342703 A FR 7342703A FR 2253424 A5 FR2253424 A5 FR 2253424A5
Authority
FR
France
Prior art keywords
address
memory
limit
predetermined
predetermined limit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7342703A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Societe Industrielle Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Societe Industrielle Honeywell Bull filed Critical Societe Industrielle Honeywell Bull
Priority to FR7342703A priority Critical patent/FR2253424A5/en
Application granted granted Critical
Publication of FR2253424A5 publication Critical patent/FR2253424A5/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/342—Extension of operand address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/145—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism

Abstract

The system comprises means to protect a first information structure submitted to a memory by the use of a selective access memory contained in a second information structure. The first structure has information address values lower than a predetermined address limit, and the second struct ure values higher than the predetermined limit. A repertoire contains teh address codes. A menas is included to add the value of the relative address to the predetermined address limit. Also included is a replacement procedure for the original factors by addresses equal to the original values plus the value of the predetermined limit. The tabular replacement system operates by a pointer situated at the address limit. The entire system involves a central processor unit and a memory unit for the microcodes.
FR7342703A 1973-11-30 1973-11-30 Memory address system for data protection - has predetermined limit and two memories with replacement system for first memory by second Expired FR2253424A5 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7342703A FR2253424A5 (en) 1973-11-30 1973-11-30 Memory address system for data protection - has predetermined limit and two memories with replacement system for first memory by second

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7342703A FR2253424A5 (en) 1973-11-30 1973-11-30 Memory address system for data protection - has predetermined limit and two memories with replacement system for first memory by second

Publications (1)

Publication Number Publication Date
FR2253424A5 true FR2253424A5 (en) 1975-06-27

Family

ID=9128511

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7342703A Expired FR2253424A5 (en) 1973-11-30 1973-11-30 Memory address system for data protection - has predetermined limit and two memories with replacement system for first memory by second

Country Status (1)

Country Link
FR (1) FR2253424A5 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0214490A2 (en) * 1985-09-06 1987-03-18 Hitachi, Ltd. Data processing apparatus with a virtual storage address boundary check circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0214490A2 (en) * 1985-09-06 1987-03-18 Hitachi, Ltd. Data processing apparatus with a virtual storage address boundary check circuit
EP0214490A3 (en) * 1985-09-06 1990-01-10 Hitachi, Ltd. Data processing apparatus with a virtual storage address boundary check circuit

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Legal Events

Date Code Title Description
ST Notification of lapse