ES396697A1 - Improvements introduced in devices to reduce the inactive burden or sleeping time of the central unit of a calculator that works in real time. (Machine-translation by Google Translate, not legally binding) - Google Patents

Abstract

Improvements introduced in devices to reduce the idle load or idle time of the central unit of a calculator operating in real time, which, within consecutive time intervals determined by chronometric pulses, must execute, in a predetermined consecutive order, a number of programs, each of which is associated with a memory field comprising a first partial field in which a program start address is stored, and a second partial field in which a number is stored, being determined the consecutive order between two arbitrary programs between said programs due to the fact that the program that is ahead in turn has in its associated memory field the lowest numerical value for said number, characterized in that said devices comprise a memory, in which each of said memory fields is stored in an individual position and whose position lower can be rotated by said central unit, and a classification circuit for classifying said memory fields in said memory in such a way that said predetermined consecutive order for the execution of said program must correspond to the consecutive order of the positions in which said memory fields associated with said programs are stored in said memory, and that in said lowest position will be stored the memory field of that program which is first in turn in said predetermined consecutive order, whose classification circuit comprises a certain number of registers for performing readings and writings in arbitrary positions of said memory, a comparison circuit for comparing a memory field transmitted by reading from a position in said memory to a first one of said registers with a memory field transmitted by reading from another position highest of said memory to a second of said regis with respect to the numerical value for said number and to generate a comparison signal indicating (1,0) whether the compared memory fields have the consecutive order provided between their respective positions in said memory or not, a control circuit which depending on said comparison signal from said comparison circuit, it activates a certain number of outputs according to one or two defined sequences (10 + 2, 11,4,5,6 + 7, 8 + 9 and 12 + 2, 1, 2, + 3, 4,5,6 + 7, 8 + 8), respectively, to perform one of two functions of said classification circuit, ie, or that, if said comparison signal indicates (0) that the fields of memory compared by said comparison circuit do not have the consecutive order provided in said memory, the memory field of said second record is written in the next lower position in said memory than where it was taken from (10 + 2), after which, from the next higher position in said memory, it is transmitted by reading a new memory field to said second register (11,4,5, 6 + 7) and then it is compared by said comparison circuit with the memory field in said first register (8 + 9), or that, if said comparison signal indicates (1) that the memory fields compared by said comparison circuit do have the consecutive order provided in said memory, the memory field in said first register is written in the next lowest position in said memory that the one from which the memory field was taken in said second register (12 + 2), after which the memory fields in the lowest position and the next to the lowest in said memory are read to said first and said second register respectively (1,2 + 3, 4,5,6 + 7) and then they are compared (8 + 9) by said comparison circuit, and a certain number of doors y which are connected to said outputs of said circuit control and depending on which the salt is activated these interconnect the said memory, said registers and said comparison circuit so that said tasks of said classification circuit are performed. (Machine-translation by Google Translate, not legally binding)