ES2960054T3 - Superconductores mediante vías de silicio y su método de fabricación - Google Patents

Superconductores mediante vías de silicio y su método de fabricación Download PDF

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Publication number
ES2960054T3
ES2960054T3 ES17811292T ES17811292T ES2960054T3 ES 2960054 T3 ES2960054 T3 ES 2960054T3 ES 17811292 T ES17811292 T ES 17811292T ES 17811292 T ES17811292 T ES 17811292T ES 2960054 T3 ES2960054 T3 ES 2960054T3
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Spain
Prior art keywords
superconducting metal
substrate
vias
superconducting
metal
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ES17811292T
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English (en)
Spanish (es)
Inventor
David Abraham
John Cotte
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International Business Machines Corp
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International Business Machines Corp
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4484—Superconducting materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/46—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a liquid
    • H10P14/47—Electrolytic deposition, i.e. electroplating; Electroless plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0238—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes through pads or through electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0245—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising use of blind vias during the manufacture
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/331—Bonding techniques, e.g. hybrid bonding characterised by the application of energy for connecting
    • H10W80/333—Compression bonding
    • H10W80/334—Thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
ES17811292T 2017-05-31 2017-12-07 Superconductores mediante vías de silicio y su método de fabricación Active ES2960054T3 (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/609,860 US10157842B1 (en) 2017-05-31 2017-05-31 Semiconductor device including superconducting metal through-silicon-vias and method of manufacturing the same
PCT/EP2017/081792 WO2018219484A1 (en) 2017-05-31 2017-12-07 Superconducting metal through-silicon-vias

Publications (1)

Publication Number Publication Date
ES2960054T3 true ES2960054T3 (es) 2024-02-29

Family

ID=60627639

Family Applications (1)

Application Number Title Priority Date Filing Date
ES17811292T Active ES2960054T3 (es) 2017-05-31 2017-12-07 Superconductores mediante vías de silicio y su método de fabricación

Country Status (6)

Country Link
US (3) US10157842B1 (enExample)
EP (1) EP3639295B1 (enExample)
JP (1) JP7182834B2 (enExample)
CN (1) CN110622297B (enExample)
ES (1) ES2960054T3 (enExample)
WO (1) WO2018219484A1 (enExample)

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US9971970B1 (en) 2015-04-27 2018-05-15 Rigetti & Co, Inc. Microwave integrated quantum circuits with VIAS and methods for making the same
US11121301B1 (en) * 2017-06-19 2021-09-14 Rigetti & Co, Inc. Microwave integrated quantum circuits with cap wafers and their methods of manufacture
US10741742B2 (en) * 2018-02-28 2020-08-11 The Regents Of The University Of Colorado, A Body Corporate Enhanced superconducting transition temperature in electroplated rhenium
US11158781B2 (en) 2019-11-27 2021-10-26 International Business Machines Corporation Permanent wafer handlers with through silicon vias for thermalization and qubit modification
US20210280765A1 (en) * 2020-03-06 2021-09-09 The Board Of Trustees Of The University Of Alabama Superconducting carrier and cables for quantum device chips and method of fabrication
CN112420604B (zh) * 2020-11-20 2022-12-06 中国科学院半导体研究所 一种基于热压键合的tsv垂直电学互连器件的制备方法
US12033981B2 (en) 2020-12-16 2024-07-09 International Business Machines Corporation Create a protected layer for interconnects and devices in a packaged quantum structure
FI20215520A1 (en) * 2021-05-04 2022-11-05 Iqm Finland Oy Superconducting vias in the substrate
EP4352664A4 (en) 2021-06-11 2025-04-30 Seeqc Inc. FLUX BIASING SYSTEM AND METHOD FOR SUPERCONDUCTING QUANTUM CIRCUITS
CN115000286A (zh) * 2022-07-13 2022-09-02 材料科学姑苏实验室 一种晶圆孔道填充方法、填充装置、转接片和用途
CN117460398B (zh) * 2023-10-30 2026-01-13 本源量子计算科技（合肥）股份有限公司 超导线路及其制造方法
JP2026028554A (ja) 2024-08-07 2026-02-20 富士通株式会社 デバイスの製造方法及びデバイス

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CA1329952C (en) * 1987-04-27 1994-05-31 Yoshihiko Imanaka Multi-layer superconducting circuit substrate and process for manufacturing same
EP0358879A3 (en) * 1988-09-13 1991-02-27 Hewlett-Packard Company Method of making high density interconnects
DE69403104T2 (de) * 1993-02-15 1997-10-30 Sumitomo Electric Industries Verfahren zum Erzeugen einer strukturierten oxydsupraleitenden Dünnschicht
US6100194A (en) 1998-06-22 2000-08-08 Stmicroelectronics, Inc. Silver metallization by damascene method
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Also Published As

Publication number Publication date
US20180350749A1 (en) 2018-12-06
US10157842B1 (en) 2018-12-18
CN110622297B (zh) 2023-09-01
EP3639295A1 (en) 2020-04-22
JP2020522128A (ja) 2020-07-27
US10833016B2 (en) 2020-11-10
JP7182834B2 (ja) 2022-12-05
CN110622297A (zh) 2019-12-27
US10504842B1 (en) 2019-12-10
EP3639295B1 (en) 2023-09-13
WO2018219484A1 (en) 2018-12-06
US20200251419A1 (en) 2020-08-06

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