ES2191956T3 - Metodo para realizar comparaciones de fase y comparador de fase. - Google Patents

Metodo para realizar comparaciones de fase y comparador de fase.

Info

Publication number
ES2191956T3
ES2191956T3 ES98939667T ES98939667T ES2191956T3 ES 2191956 T3 ES2191956 T3 ES 2191956T3 ES 98939667 T ES98939667 T ES 98939667T ES 98939667 T ES98939667 T ES 98939667T ES 2191956 T3 ES2191956 T3 ES 2191956T3
Authority
ES
Spain
Prior art keywords
signal
state machine
phase
compared
handshaking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES98939667T
Other languages
English (en)
Inventor
Olli Piirainen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Oyj
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Oyj filed Critical Nokia Oyj
Application granted granted Critical
Publication of ES2191956T3 publication Critical patent/ES2191956T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D13/00—Circuits for comparing the phase or frequency of two mutually-independent oscillations
    • H03D13/003—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means
    • H03D13/004—Circuits for comparing the phase or frequency of two mutually-independent oscillations in which both oscillations are converted by logic means into pulses which are applied to filtering or integrating means the logic means delivering pulses at more than one terminal, e.g. up and down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Control Of Electric Motors In General (AREA)
  • Measuring Phase Differences (AREA)
  • Pyrane Compounds (AREA)
  • Pharmaceuticals Containing Other Organic And Inorganic Compounds (AREA)
  • Heterocyclic Carbon Compounds Containing A Hetero Ring Having Oxygen Or Sulfur (AREA)
  • Information Transfer Systems (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Abstract

ESTA INVENCION SE REFIERE A UN PROCEDIMIENTO DE COMPARACION DE FASE Y A UN COMPARADOR DE FASE. EN LA SOLUCION, SE COMPARAN DOS SEÑALES BINARIAS (A Y B) USANDO DOS AUTOMATAS ACABADOS (200 Y 202) ASINCRONOS FUNCIONALMENTE SIMILARES, QUE GENERAN DOS SEÑALES DE SALIDA (PA Y PB). SE UTILIZAN LAS SEÑALES DE SALIDA (PA Y PB) PARA MANDAR UNA FASE. SE INTRODUCE EN EL PRIMER AUTOMATA ACABADO (200) UNA PRIMERA SEÑAL (A) QUE HAY QUE SOMETER A UNA COMPARACION, UNA SEÑAL DE SALIDA (PB) PROCEDENTE DE UN SEGUNDO AUTOMATA ACABADO (202) Y UNA SEÑAL DE RECONOCIMIENTO (RB) PROCEDENTE DEL SEGUNDO AUTOMATA ACABADO (202). SE INTRODUCE EN EL SEGUNDO AUTOMATA ACABADO (202) UNA SEGUNDA SEÑAL (B) QUE HAY QUE SOMETER A UNA COMPARACION, UNA SEÑAL DE SALIDA (PA) QUE PROCEDE DEL PRIMER AUTOMATA ACABADO (200) Y UNA SEÑAL DE RECONOCIMIENTO (RA) PROCEDENTE DEL PRIMER AUTOMATA ACABADO (200). LOS DOS AUTOMATAS ACABADOS (200 Y 202) ACTIVAN SUS SEÑALES DE RECONOCIMIENTO RESPECTIVAS (RA Y RB) DESPUES DE DETECTAR LA ACTIVACION DELA SEÑAL (A Y B RESPECTIVAMENTE) QUE HAY QUE SOMETER A UNA COMPARACION. LA SEÑAL DE RECONOCIMIENTO (RA Y RB) ASEGURA EL FUNCIONAMIENTO LOGICO DEL COMPARADOR DE FASE. LA ACTIVACION DE LAS SEÑALES DE SALIDA (PA Y PB) QUE DETECTAN UNA DIFERENCIA DE FASE ENTRE LOS DOS AUTOMATAS ACABADOS Y QUE MANDAN UNA FASE DE LOS DOS AUTOMATAS ACABADOS (200 Y 202) CONSISTE EN COMPROBAR EL ESTADO DE LA SEÑAL (A Y B) QUE HAY QUE SOMETER A UNA COMPARACION QUE SE TRANSMITE A CADA AUTOMATA ACABADO (200 Y 202), EL ESTADO DE LA SEÑAL DE SALIDA (PA Y PB) DE UN AUTOMATA ACABADO CONTIGUO (200 Y 202) Y EL ESTADO DE LA SEÑAL DE RECONOCIMIENTO (RA Y RB) DEL AUTOMATA ACABADO CONTIGUO (200 Y 202).
ES98939667T 1997-08-20 1998-08-18 Metodo para realizar comparaciones de fase y comparador de fase. Expired - Lifetime ES2191956T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI973421A FI103538B1 (fi) 1997-08-20 1997-08-20 Menetelmä vaihevertailun suorittamiseksi ja vaihevertailija

Publications (1)

Publication Number Publication Date
ES2191956T3 true ES2191956T3 (es) 2003-09-16

Family

ID=8549392

Family Applications (1)

Application Number Title Priority Date Filing Date
ES98939667T Expired - Lifetime ES2191956T3 (es) 1997-08-20 1998-08-18 Metodo para realizar comparaciones de fase y comparador de fase.

Country Status (11)

Country Link
US (1) US6532257B1 (es)
EP (1) EP0938779B1 (es)
JP (1) JP4166841B2 (es)
CN (1) CN1169297C (es)
AT (1) ATE231308T1 (es)
AU (1) AU745305B2 (es)
DE (1) DE69810748T2 (es)
ES (1) ES2191956T3 (es)
FI (1) FI103538B1 (es)
NO (1) NO991859L (es)
WO (1) WO1999009654A2 (es)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6873183B1 (en) * 2003-05-12 2005-03-29 Xilinx, Inc. Method and circuit for glitchless clock control
US7129765B2 (en) 2004-04-30 2006-10-31 Xilinx, Inc. Differential clock tree in an integrated circuit
CN115800992B (zh) * 2023-02-07 2023-06-02 浪潮电子信息产业股份有限公司 一种握手信号的拆分电路、方法、装置、设备及存储介质

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3130156C2 (de) 1981-07-30 1986-11-27 Siemens AG, 1000 Berlin und 8000 München Digitaler Frequenz-Phasenkomparator
US4814726A (en) 1987-08-17 1989-03-21 National Semiconductor Corporation Digital phase comparator/charge pump with zero deadband and minimum offset
EP0520558A1 (en) * 1991-06-27 1992-12-30 Koninklijke Philips Electronics N.V. Phase locked loop and digital phase comparator for use in a phase-locked loop
GB2262415B (en) * 1991-12-13 1995-08-16 Digital Equipment Int Handshake synchronization system
US5744983A (en) * 1995-05-03 1998-04-28 Intel Corporation Phase detector with edge-sensitive enable and disable
US5583458A (en) * 1995-05-03 1996-12-10 Intel Corporation Phase detector with edge-sensitive enable and disable
WO1997023047A2 (en) 1995-12-15 1997-06-26 Telefonaktiebolaget Lm Ericsson Discrete phase locked loop
US5920207A (en) * 1997-11-05 1999-07-06 Hewlett Packard Company Asynchronous phase detector having a variable dead zone
US6239626B1 (en) * 2000-01-07 2001-05-29 Cisco Technology, Inc. Glitch-free clock selector

Also Published As

Publication number Publication date
FI103538B (fi) 1999-07-15
WO1999009654A3 (en) 1999-06-03
CN1169297C (zh) 2004-09-29
EP0938779B1 (en) 2003-01-15
WO1999009654A2 (en) 1999-02-25
FI973421A (fi) 1999-02-21
NO991859D0 (no) 1999-04-19
FI973421A0 (fi) 1997-08-20
AU745305B2 (en) 2002-03-21
DE69810748D1 (de) 2003-02-20
EP0938779A2 (en) 1999-09-01
FI103538B1 (fi) 1999-07-15
CN1237289A (zh) 1999-12-01
JP4166841B2 (ja) 2008-10-15
ATE231308T1 (de) 2003-02-15
US6532257B1 (en) 2003-03-11
DE69810748T2 (de) 2003-10-02
NO991859L (no) 1999-04-19
JP2001505028A (ja) 2001-04-10
AU8809598A (en) 1999-03-08

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