ES2170708A1 - Procedimiento para incrementar la rigidez dielectrica y resistencia de aislamiento entre pistas de placas de circuito impreso. - Google Patents

Procedimiento para incrementar la rigidez dielectrica y resistencia de aislamiento entre pistas de placas de circuito impreso.

Info

Publication number
ES2170708A1
ES2170708A1 ES200002777A ES200002777A ES2170708A1 ES 2170708 A1 ES2170708 A1 ES 2170708A1 ES 200002777 A ES200002777 A ES 200002777A ES 200002777 A ES200002777 A ES 200002777A ES 2170708 A1 ES2170708 A1 ES 2170708A1
Authority
ES
Spain
Prior art keywords
tracks
dielectric
circuit board
increasing
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES200002777A
Other languages
English (en)
Other versions
ES2170708B1 (es
Inventor
Pitel Jose Antonio Cubero
Fernandez Salvador Gomez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lear Automotive EEDS Spain SL
Original Assignee
Lear Automotive EEDS Spain SL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lear Automotive EEDS Spain SL filed Critical Lear Automotive EEDS Spain SL
Priority to ES200002777A priority Critical patent/ES2170708B1/es
Priority to PCT/ES2001/000440 priority patent/WO2002041676A1/es
Publication of ES2170708A1 publication Critical patent/ES2170708A1/es
Application granted granted Critical
Publication of ES2170708B1 publication Critical patent/ES2170708B1/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/098—Special shape of the cross-section of conductors, e.g. very thick plated conductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0346—Deburring, rounding, bevelling or smoothing conductor edges
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0597—Resist applied over the edges or sides of conductors, e.g. for protection during etching or plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

Comprende obtener dichas pistas (2), de grosor apto para aplicaciones de potencia, por ataque químico de una lámina de material electroconductor adherida a un substrato laminar dieléctrico (3) y recubrir finalmente el conjunto de substrato laminar dieléctrico (3) y pistas (2) de una capa protectora (4) aislante, incluyendo, después de la obtención de las pistas (2) y antes de la aplicación de dicha capa protectora (4), una etapa de redondeado de unas aristas (5) de las pistas (2), formadas por las intersecciones de sus superficies superiores (6) con sus superficies laterales (7), mediante un ulterior micro ataque químico sobre dichas aristas (5), cuyo redondeado facilita un grosor regular de dicha capa protectora (4) de material dieléctrico, que incrementa la citada rigidez dieléctrica y aumenta la resistencia de aislamiento.
ES200002777A 2000-11-20 2000-11-20 Procedimiento para incrementar la rigidez dielectrica y resistencia de aislamiento entre pistas de placas de circuito impreso. Expired - Lifetime ES2170708B1 (es)

Priority Applications (2)

Application Number Priority Date Filing Date Title
ES200002777A ES2170708B1 (es) 2000-11-20 2000-11-20 Procedimiento para incrementar la rigidez dielectrica y resistencia de aislamiento entre pistas de placas de circuito impreso.
PCT/ES2001/000440 WO2002041676A1 (es) 2000-11-20 2001-11-16 Procedimiento para incrementar la rigidez dieléctrica y resistencia de aislamiento entre pistas de placas de circuito impreso

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
ES200002777A ES2170708B1 (es) 2000-11-20 2000-11-20 Procedimiento para incrementar la rigidez dielectrica y resistencia de aislamiento entre pistas de placas de circuito impreso.

Publications (2)

Publication Number Publication Date
ES2170708A1 true ES2170708A1 (es) 2002-08-01
ES2170708B1 ES2170708B1 (es) 2003-12-16

Family

ID=8495697

Family Applications (1)

Application Number Title Priority Date Filing Date
ES200002777A Expired - Lifetime ES2170708B1 (es) 2000-11-20 2000-11-20 Procedimiento para incrementar la rigidez dielectrica y resistencia de aislamiento entre pistas de placas de circuito impreso.

Country Status (2)

Country Link
ES (1) ES2170708B1 (es)
WO (1) WO2002041676A1 (es)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014220650A1 (de) * 2014-10-13 2016-04-14 Heraeus Deutschland GmbH & Co. KG Optimiertes Leiterbahndesign von metallischen Materialien auf keramischen Substanzen
CN105392285A (zh) * 2015-10-29 2016-03-09 重庆方正高密电子有限公司 一种pcb板线路侧壁的处理方法
CN105357888A (zh) * 2015-10-29 2016-02-24 重庆方正高密电子有限公司 一种pcb板的制备方法及pcb板
JP7238712B2 (ja) * 2019-09-18 2023-03-14 トヨタ自動車株式会社 配線基板の製造方法および配線基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508984A (en) * 1967-06-29 1970-04-28 Electro Connective Systems Inc Method of producing printed circuits
DE4406397A1 (de) * 1994-02-26 1995-08-31 Curamik Electronics Gmbh Substrat für elektrische Schaltkreise sowie Verfahren zum Herstellen des Substrates
EP0717586A1 (en) * 1994-12-12 1996-06-19 ALCATEL BELL Naamloze Vennootschap Process to decrease the strength of an electric field produced by a high voltage conductive path on a printed circuit board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508984A (en) * 1967-06-29 1970-04-28 Electro Connective Systems Inc Method of producing printed circuits
DE4406397A1 (de) * 1994-02-26 1995-08-31 Curamik Electronics Gmbh Substrat für elektrische Schaltkreise sowie Verfahren zum Herstellen des Substrates
EP0717586A1 (en) * 1994-12-12 1996-06-19 ALCATEL BELL Naamloze Vennootschap Process to decrease the strength of an electric field produced by a high voltage conductive path on a printed circuit board

Also Published As

Publication number Publication date
ES2170708B1 (es) 2003-12-16
WO2002041676A1 (es) 2002-05-23

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