ES2145908T3 - Sistema informatico. - Google Patents

Sistema informatico.

Info

Publication number
ES2145908T3
ES2145908T3 ES95914446T ES95914446T ES2145908T3 ES 2145908 T3 ES2145908 T3 ES 2145908T3 ES 95914446 T ES95914446 T ES 95914446T ES 95914446 T ES95914446 T ES 95914446T ES 2145908 T3 ES2145908 T3 ES 2145908T3
Authority
ES
Spain
Prior art keywords
instruction
instructions
pct
bit
compressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES95914446T
Other languages
English (en)
Inventor
Paul William Staines Ro Denman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
COMMUNICATE Ltd
Original Assignee
COMMUNICATE Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by COMMUNICATE Ltd filed Critical COMMUNICATE Ltd
Application granted granted Critical
Publication of ES2145908T3 publication Critical patent/ES2145908T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3814—Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G06F9/30156—Special purpose encoding of instructions, e.g. Gray coding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G06F9/30178—Runtime instruction translation, e.g. macros of compressed or encrypted instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30185—Instruction operation extension or modification according to one or more bits in the instruction, e.g. prefix, sub-opcode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30196—Instruction operation extension or modification using decoder, e.g. decoder per instruction set, adaptable or programmable decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Iron Core Of Rotating Electric Machines (AREA)
  • Advance Control (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

EN UN SISTEMA DE ORDENADOR CON UN PROCESADOR RISC (14) QUE UTILIZA INSTRUCCIONES DE 32 BITS, CIERTAS INSTRUCCIONES SE ALMACENAN EN FORMA COMPRIMIDA DE 16 BITS Y SE EXPANDEN PARA SU USO POR EL PROCESADOR, REDUCIENDO EL TIEMPO DE ACCESO. UNA INSTRUCCION ES EXTRAIDA DE LA MEMORIA (POR MEDIO DEL BUS (10)) POR MEDIO DE UN CONJUNTO DE MEMORIAS INTERMEDIAS (11-1 A 11-4) QUE SON CARGADAS SECUENCIALMENTE CON PALABRAS DE 8 O DE 16 BITS. EL FORMATO DE LAS INSTRUCCIONES INCLUYE UN CAMPO DE CONDICION EN SU PRIMERA PALABRA, QUE DEFINE LA CONDICION PARA EJECUTAR LA INSTRUCCION. UN CODIGO NV (=NEVER) EN ESE CAMPO INDICA QUE LA INSTRUCCION NO SE VA A EJECUTAR; ESTE CODIGO (QUE NO SE UTILIZA NORMALMENTE) SE UTILIZA PARA IDENTIFICAR INSTRUCCIONES COMPRIMIDAS. UNA UNIDAD DETECTORA DE INSTRUCCIONES COMPRIMIDAS (18) EXPANDE LA INSTRUCCION COMPRIMIDA; Y EL DETECTOR (18) CONTROLA UN MULTIPLEXOR (13) PARA PASAR CUALQUIERA DE LAS INSTRUCCIONES EXPANDIDAS DESDE EL MISMO O LAS INSTRUCCIONES DE LONGITUD COMPLETA DIRECTAMENTE DESDE LAS MEMORIAS INTERMEDIAS (11-1 A 11-4) AL PROCESADOR (14). UNA UNIDAD DE MAQUINA DE ESTADO EMPAQUETADORA (17) TERMINA EL ACCESO DE LA INSTRUCCION UNA VEZ QUE SE HA ACCEDIDO A SUS 16 BITS.
ES95914446T 1994-04-05 1995-04-05 Sistema informatico. Expired - Lifetime ES2145908T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9406666A GB9406666D0 (en) 1994-04-05 1994-04-05 Computer system

Publications (1)

Publication Number Publication Date
ES2145908T3 true ES2145908T3 (es) 2000-07-16

Family

ID=10753009

Family Applications (1)

Application Number Title Priority Date Filing Date
ES95914446T Expired - Lifetime ES2145908T3 (es) 1994-04-05 1995-04-05 Sistema informatico.

Country Status (11)

Country Link
US (1) US5784585A (es)
EP (1) EP0803091B1 (es)
AT (1) ATE190148T1 (es)
AU (1) AU686358B2 (es)
DE (1) DE69515339T2 (es)
DK (1) DK0803091T3 (es)
ES (1) ES2145908T3 (es)
GB (1) GB9406666D0 (es)
GR (1) GR3033496T3 (es)
PT (1) PT803091E (es)
WO (1) WO1995027244A1 (es)

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GB2290395B (en) 1994-06-10 1997-05-28 Advanced Risc Mach Ltd Interoperability with multiple instruction sets
GB2354354B (en) * 1996-06-10 2001-05-02 Lsi Logic Corp An apparatus and method for detecting and decompressing instructions form a variable-length compressed instruction set
DE19629130A1 (de) * 1996-07-19 1998-05-14 Philips Patentverwaltung Signalprozessor
JP3781519B2 (ja) * 1997-08-20 2006-05-31 富士通株式会社 プロセッサの命令制御機構
FI113708B (fi) 1997-09-29 2004-05-31 Nokia Corp Menetelmä ja laite suoritettavien ohjelmien tallentamiseksi ja käyttämiseksi
US6101592A (en) * 1998-12-18 2000-08-08 Billions Of Operations Per Second, Inc. Methods and apparatus for scalable instruction set architecture with dynamic compact instructions
DE69823642T2 (de) * 1998-03-27 2005-04-21 Motorola Inc System und Verfahren zur Umwandlung von Befehlen
US6185670B1 (en) * 1998-10-12 2001-02-06 Intel Corporation System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields
US6338132B1 (en) * 1998-12-30 2002-01-08 Intel Corporation System and method for storing immediate data
KR100308211B1 (ko) * 1999-03-27 2001-10-29 윤종용 압축 명령을 갖는 마이크로 컴퓨터 시스템
DE69934394D1 (de) * 1999-05-03 2007-01-25 St Microelectronics Sa Vorrichtung zum Bereitstellen von Maschinenbefehlen
US7761857B1 (en) 1999-10-13 2010-07-20 Robert Bedichek Method for switching between interpretation and dynamic translation in a processor system based upon code sequence execution counts
US6408382B1 (en) * 1999-10-21 2002-06-18 Bops, Inc. Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture
US6691305B1 (en) * 1999-11-10 2004-02-10 Nec Corporation Object code compression using different schemes for different instruction types
JP3629181B2 (ja) * 2000-03-28 2005-03-16 Ｎｅｃマイクロシステム株式会社 プログラム開発支援装置
US6594821B1 (en) 2000-03-30 2003-07-15 Transmeta Corporation Translation consistency checking for modified target instructions by comparing to original copy
JP2002215387A (ja) * 2001-01-22 2002-08-02 Mitsubishi Electric Corp 命令トランスレータを備えたデータ処理装置およびメモリインタフェース装置
US6985633B2 (en) * 2001-03-26 2006-01-10 Ramot At Tel Aviv University Ltd. Device and method for decoding class-based codewords
ITMI20022003A1 (it) * 2002-09-20 2004-03-21 Atmel Corp Apparecchio e metodo per la decompressione dinamica di programmi.
US7310723B1 (en) 2003-04-02 2007-12-18 Transmeta Corporation Methods and systems employing a flag for deferring exception handling to a commit or rollback point
US7698539B1 (en) * 2003-07-16 2010-04-13 Banning John P System and method of instruction modification
DE602005005289T2 (de) * 2005-01-31 2009-07-09 Stmicroelectronics S.R.L., Agrate Brianza Verfahren, System und Computerprogrammprodukt zur Korrektur von Fehlern in einem Festwertspeicher
US20060174089A1 (en) * 2005-02-01 2006-08-03 International Business Machines Corporation Method and apparatus for embedding wide instruction words in a fixed-length instruction set architecture
US8413162B1 (en) 2005-06-28 2013-04-02 Guillermo J. Rozas Multi-threading based on rollback
CN102156629A (zh) * 2011-05-04 2011-08-17 苏州国芯科技有限公司 32位指令扩展的方法
US9372696B2 (en) 2013-10-18 2016-06-21 Via Technologies, Inc. Microprocessor with compressed and uncompressed microcode memories
US9361097B2 (en) 2013-10-18 2016-06-07 Via Technologies, Inc. Selectively compressed microcode
TWI522910B (zh) * 2013-10-18 2016-02-21 威盛電子股份有限公司 微處理器、選擇性解壓縮微程式碼方法、產生選擇性壓縮微程式碼方法、產生描述方法以及電腦程式產品
US9952865B2 (en) 2015-04-04 2018-04-24 Texas Instruments Incorporated Low energy accelerator processor architecture with short parallel instruction word and non-orthogonal register data file
US9817791B2 (en) 2015-04-04 2017-11-14 Texas Instruments Incorporated Low energy accelerator processor architecture with short parallel instruction word
US11847427B2 (en) 2015-04-04 2023-12-19 Texas Instruments Incorporated Load store circuit with dedicated single or dual bit shift circuit and opcodes for low power accelerator processor
US10503474B2 (en) 2015-12-31 2019-12-10 Texas Instruments Incorporated Methods and instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition
US10401412B2 (en) 2016-12-16 2019-09-03 Texas Instruments Incorporated Line fault signature analysis

Family Cites Families (9)

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JPS5713549A (en) * 1980-06-25 1982-01-23 Nec Corp Program compression store system
US4633388A (en) * 1984-01-18 1986-12-30 Siemens Corporate Research & Support, Inc. On-chip microprocessor instruction decoder having hardware for selectively bypassing on-chip circuitry used to decipher encrypted instruction codes
US5057837A (en) * 1987-04-20 1991-10-15 Digital Equipment Corporation Instruction storage method with a compressed format using a mask word
JPH0395629A (ja) * 1989-09-08 1991-04-22 Fujitsu Ltd データ処理装置
JPH0454271A (ja) * 1990-06-22 1992-02-21 Mitsuba Electric Mfg Co Ltd 燃料供給ポンプ
JPH04205421A (ja) * 1990-11-30 1992-07-27 Matsushita Electric Ind Co Ltd オペレーティングシステムの起動方法およびその起動装置
JPH05324314A (ja) * 1992-05-20 1993-12-07 Hitachi Ltd データ処理装置
JPH06348490A (ja) * 1993-06-08 1994-12-22 Hitachi Ltd 演算処理方法、及びマイクロコンピュータ
JPH07121352A (ja) * 1993-10-21 1995-05-12 Canon Inc 演算処理装置

Also Published As

Publication number Publication date
WO1995027244A1 (en) 1995-10-12
GR3033496T3 (en) 2000-09-29
DE69515339D1 (de) 2000-04-06
AU686358B2 (en) 1998-02-05
AU2144095A (en) 1995-10-23
GB9406666D0 (en) 1994-05-25
ATE190148T1 (de) 2000-03-15
US5784585A (en) 1998-07-21
EP0803091A1 (en) 1997-10-29
DK0803091T3 (da) 2000-07-31
DE69515339T2 (de) 2000-12-07
PT803091E (pt) 2000-07-31
EP0803091B1 (en) 2000-03-01

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