ES2132208T3 - Circuito de fusible para circuito integrado. - Google Patents

Circuito de fusible para circuito integrado.

Info

Publication number
ES2132208T3
ES2132208T3 ES93402582T ES93402582T ES2132208T3 ES 2132208 T3 ES2132208 T3 ES 2132208T3 ES 93402582 T ES93402582 T ES 93402582T ES 93402582 T ES93402582 T ES 93402582T ES 2132208 T3 ES2132208 T3 ES 2132208T3
Authority
ES
Spain
Prior art keywords
fuse
circuit
state
circuits
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93402582T
Other languages
English (en)
Inventor
Jacek Kowalski
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gemplus SA
Original Assignee
Gemplus Card International SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gemplus Card International SA filed Critical Gemplus Card International SA
Application granted granted Critical
Publication of ES2132208T3 publication Critical patent/ES2132208T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

LA INVENCION SE REFIERE A CIRCUITOS INTEGRADOS, Y MAS EN ESPECIAL A CIRCUITOS DE FUSIBLES. PARA MEJORAR LA FIABILIDAD DE LOS CIRCUITOS INTEGRADOS DE FUSIBLE FISICO, LA INVENCION PROPONE ASOCIAR AL FUSIBLE (F) UNA CELULA DE MEMORIA NO VOLATIL PROGRAMABLE ELECTRICAMENTE (TGF), ESTANDO LA CELULA PROGRAMADA AL MISMO TIEMPO QUE EL FUSIBLE ESTA FUNDIDO. EL ESTADO DEL FUSIBLE SE CONFIRMA POR EL ESTADO DE LA MEMORIA. EN PARTICULAR, EL ESTADO FUNDIDO DEL FUSIBLE PUEDE CONFIRMARSE MEDIANTE EL ESTADO PROGRAMADO DE LA MEMORIA, EN APLICACIONES DONDE LO QUE IMPORTA ES ASEGURARSE DE QUE EL CIRCUITO PUEDE CONTINUAR CONSERVANDO LAS FUNCIONALIDADES DEFINIDAS POR EL ESTADO FUNDIDO DEL FUSIBLE. SI LA ESTRUCTURA FUNDIDA VUELVE A TOMAR POSTERIORMENTE MAS O MENOS LAS CARACTERISTICAS DE LA ESTRUCTURA INTACTA, LA CELULA DE MEMORIA SUPLIRA AL FUSIBLE DEFECTUOSO.
ES93402582T 1992-10-29 1993-10-20 Circuito de fusible para circuito integrado. Expired - Lifetime ES2132208T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9212969A FR2697673B1 (fr) 1992-10-29 1992-10-29 Circuit à fusible, pour circuit intégré.

Publications (1)

Publication Number Publication Date
ES2132208T3 true ES2132208T3 (es) 1999-08-16

Family

ID=9434997

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93402582T Expired - Lifetime ES2132208T3 (es) 1992-10-29 1993-10-20 Circuito de fusible para circuito integrado.

Country Status (6)

Country Link
US (1) US5442589A (es)
EP (1) EP0597745B1 (es)
JP (1) JPH077139A (es)
DE (1) DE69324328T2 (es)
ES (1) ES2132208T3 (es)
FR (1) FR2697673B1 (es)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0149259B1 (ko) * 1995-06-30 1998-10-15 김광호 반도체 메모리 장치의 퓨즈 시그너쳐 회로
FR2739706B1 (fr) * 1995-10-09 1997-11-21 Inside Technologies Perfectionnements aux cartes a memoire
FR2739737B1 (fr) * 1995-10-09 1997-11-21 Inside Technologies Perfectionnements aux cartes a memoire
US5631862A (en) * 1996-03-05 1997-05-20 Micron Technology, Inc. Self current limiting antifuse circuit
US5861793A (en) * 1996-04-29 1999-01-19 Hatton; Ken W. Re-settable fuse
US5734617A (en) * 1996-08-01 1998-03-31 Micron Technology Corporation Shared pull-up and selection circuitry for programmable cells such as antifuse cells
JP3274364B2 (ja) * 1996-08-14 2002-04-15 株式会社東芝 半導体装置及びヒューズチェック方法
GB2318228B (en) * 1996-10-09 2000-08-09 Ericsson Telefon Ab L M Trimming circuit
US6104209A (en) * 1998-08-27 2000-08-15 Micron Technology, Inc. Low skew differential receiver with disable feature
US5953276A (en) * 1997-12-18 1999-09-14 Micron Technology, Inc. Fully-differential amplifier
US5835324A (en) * 1997-07-14 1998-11-10 Hatton; Ken W. Programmable electronic fuse box having a key pad which does not require fuse elements
US5889679A (en) * 1997-07-15 1999-03-30 Integrated Device Technology, Inc. Fuse array control for smart function enable
US6212482B1 (en) 1998-03-06 2001-04-03 Micron Technology, Inc. Circuit and method for specifying performance parameters in integrated circuits
US6268760B1 (en) * 1998-04-30 2001-07-31 Texas Instruments Incorporated Hysteretic fuse control circuit with serial interface fusing
US5999038A (en) * 1998-09-24 1999-12-07 Atmel Corporation Fuse circuit having zero power draw for partially blown condition
DE10063685A1 (de) * 2000-12-20 2002-07-18 Infineon Technologies Ag Schaltungsanordnung zur Ansteuerung einer programmierbaren Verbindung
DE10063684A1 (de) * 2000-12-20 2002-07-18 Infineon Technologies Ag Schaltungsanordnung zur Ansteuerung einer programmierbaren Verbindung
JP2002203901A (ja) * 2000-12-27 2002-07-19 Toshiba Microelectronics Corp フューズ回路
US6515904B2 (en) 2001-03-21 2003-02-04 Matrix Semiconductor, Inc. Method and system for increasing programming bandwidth in a non-volatile memory device
US6574145B2 (en) 2001-03-21 2003-06-03 Matrix Semiconductor, Inc. Memory device and method for sensing while programming a non-volatile memory cell
US6597234B2 (en) * 2001-12-14 2003-07-22 Motorola, Inc. Anti-fuse circuit and method of operation
US7006392B2 (en) * 2004-01-26 2006-02-28 Micron Technology, Inc. Memory redundancy programming
US7755162B2 (en) 2004-05-06 2010-07-13 Sidense Corp. Anti-fuse memory cell
US9123572B2 (en) 2004-05-06 2015-09-01 Sidense Corporation Anti-fuse memory cell
US8735297B2 (en) 2004-05-06 2014-05-27 Sidense Corporation Reverse optical proximity correction method
JP4981661B2 (ja) * 2004-05-06 2012-07-25 サイデンス コーポレーション 分割チャネルアンチヒューズアレイ構造
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
CN108320007A (zh) * 2018-02-06 2018-07-24 常州印刷电子产业研究院有限公司 防伪标签及其控制方法
FR3085530B1 (fr) * 2018-08-31 2020-10-02 St Microelectronics Rousset Circuit integre comportant au moins une cellule memoire avec un dispositif anti-fusible.
US11093164B2 (en) * 2019-08-27 2021-08-17 Micron Technology, Inc. Handling bad blocks generated during a block erase operation

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4198696A (en) * 1978-10-24 1980-04-15 International Business Machines Corporation Laser cut storage cell
JPS60182219A (ja) * 1984-02-29 1985-09-17 Fujitsu Ltd 半導体装置
JPS61123169A (ja) * 1984-11-20 1986-06-11 Fujitsu Ltd 半導体集積回路
FR2649823B1 (fr) * 1989-07-13 1993-10-22 Gemplus Card International Fusible mos a claquage d'oxyde et son application aux cartes a memoire
JP2547451B2 (ja) * 1989-09-18 1996-10-23 富士通株式会社 半導体記憶装置
JPH07105159B2 (ja) * 1989-11-16 1995-11-13 株式会社東芝 半導体記憶装置の冗長回路
FR2660795B1 (fr) * 1990-04-10 1994-01-07 Sgs Thomson Microelectronics Sa Circuit de detection de fusible.
FR2684206B1 (fr) * 1991-11-25 1994-01-07 Sgs Thomson Microelectronics Sa Circuit de lecture de fusible de redondance pour memoire integree.

Also Published As

Publication number Publication date
FR2697673A1 (fr) 1994-05-06
US5442589A (en) 1995-08-15
JPH077139A (ja) 1995-01-10
EP0597745A1 (fr) 1994-05-18
EP0597745B1 (fr) 1999-04-07
DE69324328D1 (de) 1999-05-12
FR2697673B1 (fr) 1994-12-16
DE69324328T2 (de) 1999-09-23

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