ES2128308T3 - Detector de secuencia de maxima probabilidad. - Google Patents
Detector de secuencia de maxima probabilidad.Info
- Publication number
- ES2128308T3 ES2128308T3 ES91305034T ES91305034T ES2128308T3 ES 2128308 T3 ES2128308 T3 ES 2128308T3 ES 91305034 T ES91305034 T ES 91305034T ES 91305034 T ES91305034 T ES 91305034T ES 2128308 T3 ES2128308 T3 ES 2128308T3
- Authority
- ES
- Spain
- Prior art keywords
- detector
- data sources
- partial path
- bits
- equaliser
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03178—Arrangements involving sequence estimation techniques
- H04L25/03184—Details concerning the metric
- H04L25/03197—Details concerning the metric methods of calculation involving metrics
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
- H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
- H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Theoretical Computer Science (AREA)
- Error Detection And Correction (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Measurement Of Current Or Voltage (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
- Color Television Systems (AREA)
Abstract
UN DETECTOR DE SECUENCIAS DE MAXIMA PROBABILIDAD QUE UTILIZA EL ALGORITMO DE VITERBI PARA ESTIMAR UNA SECUENCIA DE BITS DE DATOS RECIBIDA SOBRE UN CANAL DE COMUNICACION. DEPENDIENDO DE LA LONGITUD DE COMPRESION (C), SE ASOCIA UNA GRAN VARIEDAD DE ESTADOS DIFERENTES CON LOS BITS TRANSMITIDOS (EJ: 16 SI C=4). EL DETECTOR COMPRENDE VARIAS FUENTES DE DATOS (13, 14, 17, 23, 24, 28) RELACIONADAS RESPECTIVAMENTE, CON LAS PROBABILIDADES DE TRANSICION DEL ESTADO (METRICAS RAMIFICADAS, PREVIAS A METRICAS DE PASO PARCIAL) Y CON LOS VALORES OBSERVADOS DE LOS BITS RECIBIDOS. SE PROPORCIONAN MEDIOS PARA CALCULAR LAS METRICAS DE PASO PARCIAL PARA CADA ESTADO, UTILIZANDO VALORES DE DICHAS FUENTES DE DATOS. LOS MEDIOS DE CALCULO COMPRENDEN UN ACUMULADOR/AÑADIDOR COMUN (1) PARA REALIZAR OPERACIONES ARITMETICAS DE ADICION REPETIDAS Y PARA ALMACENAR EL RESULTADO ACUMULADO DE LAS MISMAS. SE PROPORCIONAN TAMBIEN MEDIOS MULTIPLEXORES (10, 15) PARA ACOPLAR LAS FUENTES DE DATOS SELECTIVAMENTE EN UN ORDEN PREDETERMINADO AL ACUMULADOR/AÑADIDOR PARA IMPLEMENTAR EL CALCULO METRICO DEL PASO PARCIAL. LA ARQUITECTURA ES COMPATIBLE CON LAS TECNICAS VLSI Y PERMITEN IMPLEMENTAR EL DETECTOR UTILIZANDO UN AREA SEMICONDUCTORA MINIMA. EL DETECTOR PUEDE UTILIZARSE INDEPENDIENTEMENTE, COMO ECUALIZADOR O DECODIFICADOR, PERO EN UNA INCORPORACION PREFERENTE ESTAS FUNCIONES REUTILIZAN EL MISMO HARDWARE COMUN EN SERIE PERMITIENDO QUE TANTO EL ECUALIZADOR COMO EL DECODIFICADOR SE IMPLEMENTEN EN UN SOLO CIRCUITO INTEGRADO (EJ: EN UN CHIP).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9015854A GB2246272B (en) | 1990-07-19 | 1990-07-19 | Maximum likelihood sequence detector |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2128308T3 true ES2128308T3 (es) | 1999-05-16 |
Family
ID=10679317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES91305034T Expired - Lifetime ES2128308T3 (es) | 1990-07-19 | 1991-06-04 | Detector de secuencia de maxima probabilidad. |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP0467522B1 (es) |
AT (1) | ATE175538T1 (es) |
DE (1) | DE69130717T2 (es) |
ES (1) | ES2128308T3 (es) |
GB (1) | GB2246272B (es) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5291499A (en) * | 1992-03-16 | 1994-03-01 | Cirrus Logic, Inc. | Method and apparatus for reduced-complexity viterbi-type sequence detectors |
GB2281179B (en) * | 1993-08-18 | 1998-03-11 | Roke Manor Research | Apparatus for use in equipment providing a digital radio link between a fixed and a mobile radio unit |
EP0682414B1 (en) | 1993-11-29 | 2001-11-21 | Oki Electric Industry Company, Limited | Device for estimating soft judgement value and device for estimating maximum likelihood system |
US5550870A (en) * | 1994-03-02 | 1996-08-27 | Lucent Technologies Inc. | Viterbi processor |
JP3203941B2 (ja) * | 1994-03-24 | 2001-09-04 | 松下電器産業株式会社 | ビタビ復号装置 |
US5717723A (en) * | 1994-08-17 | 1998-02-10 | Roke Manor Research Limited | Apparatus for use in equipment providing a digital radio link between a fixed radio unit and a mobile radio unit |
US6023492A (en) * | 1995-11-24 | 2000-02-08 | Telefonaktiebolaget Lm Ericsson | Method and apparatus for conditionally combining bit metrics in a communication system |
GB2309867A (en) * | 1996-01-30 | 1997-08-06 | Sony Corp | Reliability data in decoding apparatus |
KR100190291B1 (ko) * | 1996-07-30 | 1999-06-01 | 윤종용 | 비터비 디코더의 트레이스백 제어 장치 |
FI102230B (fi) | 1997-02-28 | 1998-10-30 | Nokia Telecommunications Oy | Vastaanottomenetelmä ja vastaanotin |
US8788921B2 (en) * | 2011-10-27 | 2014-07-22 | Lsi Corporation | Detector with soft pruning |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3872432A (en) * | 1974-04-10 | 1975-03-18 | Itt | Synchronization circuit for a viterbi decoder |
DE3725655A1 (de) * | 1987-08-03 | 1989-02-16 | Ant Nachrichtentech | Verfahren zum auswerten von zweig- und pfadmetriken sowie anordnung |
FI82871C (fi) | 1989-05-17 | 1991-04-25 | Nokia Mobira Oy | Kretsanordning foer foerverkligande av en viterbi-algoritm. |
-
1990
- 1990-07-19 GB GB9015854A patent/GB2246272B/en not_active Expired - Fee Related
-
1991
- 1991-06-04 ES ES91305034T patent/ES2128308T3/es not_active Expired - Lifetime
- 1991-06-04 AT AT91305034T patent/ATE175538T1/de not_active IP Right Cessation
- 1991-06-04 EP EP91305034A patent/EP0467522B1/en not_active Expired - Lifetime
- 1991-06-04 DE DE69130717T patent/DE69130717T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2246272A (en) | 1992-01-22 |
EP0467522A3 (en) | 1993-10-27 |
EP0467522B1 (en) | 1999-01-07 |
EP0467522A2 (en) | 1992-01-22 |
ATE175538T1 (de) | 1999-01-15 |
GB9015854D0 (en) | 1990-09-05 |
DE69130717D1 (de) | 1999-02-18 |
GB2246272B (en) | 1994-09-14 |
DE69130717T2 (de) | 1999-07-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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