ES2123024T3 - Circuito de sincronizacion. - Google Patents

Circuito de sincronizacion.

Info

Publication number
ES2123024T3
ES2123024T3 ES93200225T ES93200225T ES2123024T3 ES 2123024 T3 ES2123024 T3 ES 2123024T3 ES 93200225 T ES93200225 T ES 93200225T ES 93200225 T ES93200225 T ES 93200225T ES 2123024 T3 ES2123024 T3 ES 2123024T3
Authority
ES
Spain
Prior art keywords
clock signal
clsys
cld
synchronous
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93200225T
Other languages
English (en)
Inventor
Laender Jos Camiel Irene De
Joan Berthe Sylvain Ceuterick
Philippe Meylemans
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel Alsthom Compagnie Generale dElectricite
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Alsthom Compagnie Generale dElectricite filed Critical Alcatel Alsthom Compagnie Generale dElectricite
Application granted granted Critical
Publication of ES2123024T3 publication Critical patent/ES2123024T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • H04L7/0338—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals the correction of the phase error being performed by a feed forward loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

EL CIRCUITO DE SINCRONIZACION SINCRONIZA UNA SEÑAL DIN DE ENTRADA DIGITAL, SINCRONA CON UNA PRIMERA SEÑAL DE RELOJ CLBYTE CON FRECUENCIA VARIABLE, CON UNA SEGUNDA SEÑAL DE RELOJ CLSYS CON FRECUENCIA FIJA. INCLUYE UN CIRCUITO DEMULTIPLEXOR CLD, DMO,...DM7 PARA DEMULTIPLEXAR DIN SOBRE 8 CANALES. CLD ES UN CIRCUITO DIVISOR QUE GENERA, DESDE LA PRIMERA CITADA SEÑAL DE RELOJ, 8 SEÑALES DT0 A DT7 SEÑALES DE RELOJ DIVIDIDAS DE FRECUENCIA, QUE CONTROLAN DM0 A DM7, Y QUE SE APLICAN A LOS RESPECTIVOS CIRCUITOS DE DETECCION, DF01 A DF03, XORO;... DF1 A DF73, XOR7, PARA GENERAR SEÑALES DE CONTROL CS0 A CS7, INDICATIVAS DE LAS TRANSICIONES DE VALOR DE DT0 A DT7. CS0 A CS7 SE USAN PARA MUESTREAR LAS SEÑALES DE ENTRADA DIN0 A DIN7 DEMULTIPLEXADAS, PROPORCIONANDO ASI DOUT0 A DOUT7, QUE SON SINCRONAS CON CLSYS.. SE USA UN MODULO M DE MEMORIA PARA ALMACENAR LAS ULTIMAS SEÑALES CUANDO SON ESTABLES. SEGUN SU APLICACION, SE LEEN EN UNA FORMA PREDETERMINADA PARA FORMAR DOUT.
ES93200225T 1993-01-28 1993-01-28 Circuito de sincronizacion. Expired - Lifetime ES2123024T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP19930200225 EP0608578B1 (en) 1993-01-28 1993-01-28 Synchronizing circuit

Publications (1)

Publication Number Publication Date
ES2123024T3 true ES2123024T3 (es) 1999-01-01

Family

ID=8213595

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93200225T Expired - Lifetime ES2123024T3 (es) 1993-01-28 1993-01-28 Circuito de sincronizacion.

Country Status (4)

Country Link
EP (1) EP0608578B1 (es)
AU (1) AU670973B2 (es)
DE (1) DE69320616T2 (es)
ES (1) ES2123024T3 (es)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL183214C (nl) * 1980-01-31 1988-08-16 Philips Nv Inrichting voor het synchroniseren van de fase van een lokaal opgewekt kloksignaal met de fase van een ingangssignaal.
US4756011A (en) * 1986-12-24 1988-07-05 Bell Communications Research, Inc. Digital phase aligner
EP0379279A3 (en) * 1989-01-17 1991-09-11 Marconi Instruments Limited Data transmission synchroniser

Also Published As

Publication number Publication date
EP0608578B1 (en) 1998-08-26
EP0608578A1 (en) 1994-08-03
AU670973B2 (en) 1996-08-08
DE69320616D1 (de) 1998-10-01
DE69320616T2 (de) 1999-02-11
AU5214593A (en) 1994-08-04

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