ES2087922T3 - VERIFICATION SYSTEM OF A PRINTED CIRCUIT PROVIDED WITH INTEGRATED CIRCUITS AND APPLICATION OF THIS SYSTEM TO THE VERIFICATION OF SUCH PRINTED CIRCUIT. - Google Patents

VERIFICATION SYSTEM OF A PRINTED CIRCUIT PROVIDED WITH INTEGRATED CIRCUITS AND APPLICATION OF THIS SYSTEM TO THE VERIFICATION OF SUCH PRINTED CIRCUIT.

Info

Publication number
ES2087922T3
ES2087922T3 ES91104175T ES91104175T ES2087922T3 ES 2087922 T3 ES2087922 T3 ES 2087922T3 ES 91104175 T ES91104175 T ES 91104175T ES 91104175 T ES91104175 T ES 91104175T ES 2087922 T3 ES2087922 T3 ES 2087922T3
Authority
ES
Spain
Prior art keywords
printed circuit
test
cell
verification
tracks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES91104175T
Other languages
Spanish (es)
Inventor
Dominique Castel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
Alcatel Mobile Communication France SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Mobile Communication France SA filed Critical Alcatel Mobile Communication France SA
Application granted granted Critical
Publication of ES2087922T3 publication Critical patent/ES2087922T3/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells

Abstract

The system consists of test equipment fitted with a connecting unit and an integrated circuit incorporating at least one functional cell (1) and a test cell. The printed circuit comprises functional tracks (7, 8) and test tracks giving access respectively to the functional cell and the test cell. This test cell incorporates means for connecting an input and an output of the functional cell. The test tracks are suitable for an integrated circuit and the connecting unit giving access to each of the printed circuit tracks. The test cell also includes means for putting all the outputs from the functional cell to a high impedance state in response to a neutralising signal derived from the state of the test track. The system enables a printed circuit to be tested by the injection of signals through the connecting unit. <IMAGE>
ES91104175T 1990-03-23 1991-03-18 VERIFICATION SYSTEM OF A PRINTED CIRCUIT PROVIDED WITH INTEGRATED CIRCUITS AND APPLICATION OF THIS SYSTEM TO THE VERIFICATION OF SUCH PRINTED CIRCUIT. Expired - Lifetime ES2087922T3 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9003754A FR2660071B1 (en) 1990-03-23 1990-03-23 SYSTEM FOR TESTING A PRINTED CIRCUIT PROVIDED WITH INTEGRATED CIRCUITS AND APPLICATION OF THIS SYSTEM TO TESTING SUCH A PRINTED CIRCUIT.

Publications (1)

Publication Number Publication Date
ES2087922T3 true ES2087922T3 (en) 1996-08-01

Family

ID=9395057

Family Applications (1)

Application Number Title Priority Date Filing Date
ES91104175T Expired - Lifetime ES2087922T3 (en) 1990-03-23 1991-03-18 VERIFICATION SYSTEM OF A PRINTED CIRCUIT PROVIDED WITH INTEGRATED CIRCUITS AND APPLICATION OF THIS SYSTEM TO THE VERIFICATION OF SUCH PRINTED CIRCUIT.

Country Status (9)

Country Link
EP (1) EP0453758B1 (en)
AT (1) ATE137595T1 (en)
DE (1) DE69119140T2 (en)
DK (1) DK0453758T3 (en)
ES (1) ES2087922T3 (en)
FI (1) FI911366A (en)
FR (1) FR2660071B1 (en)
GR (1) GR3020493T3 (en)
NO (1) NO302446B1 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU8963582A (en) * 1981-10-30 1983-05-05 Honeywell Information Systems Incorp. Design and testing electronic components
JPS62220879A (en) * 1986-03-22 1987-09-29 Hitachi Ltd Semiconductor device
JPH01259274A (en) * 1988-04-08 1989-10-16 Fujitsu Ltd Test system for integrated circuit
DE3839289C1 (en) * 1988-11-21 1990-05-23 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung Ev, 8000 Muenchen, De Circuit for the operation of an integrated circuit of which it is a component, optionally in a test operation mode or a functional operation mode

Also Published As

Publication number Publication date
NO911131D0 (en) 1991-03-21
FR2660071B1 (en) 1992-07-24
DK0453758T3 (en) 1996-08-12
NO302446B1 (en) 1998-03-02
DE69119140D1 (en) 1996-06-05
FI911366A (en) 1991-09-24
DE69119140T2 (en) 1996-08-14
EP0453758B1 (en) 1996-05-01
GR3020493T3 (en) 1996-10-31
ATE137595T1 (en) 1996-05-15
EP0453758A1 (en) 1991-10-30
FI911366A0 (en) 1991-03-20
NO911131L (en) 1991-09-24
FR2660071A1 (en) 1991-09-27

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