ES2069572T3 - Encapsulado y metodo de un chip de circuito integrado. - Google Patents

Encapsulado y metodo de un chip de circuito integrado.

Info

Publication number
ES2069572T3
ES2069572T3 ES89200445T ES89200445T ES2069572T3 ES 2069572 T3 ES2069572 T3 ES 2069572T3 ES 89200445 T ES89200445 T ES 89200445T ES 89200445 T ES89200445 T ES 89200445T ES 2069572 T3 ES2069572 T3 ES 2069572T3
Authority
ES
Spain
Prior art keywords
integrated circuit
input
same
silice
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89200445T
Other languages
English (en)
Inventor
Vahak K Sahakian
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of ES2069572T3 publication Critical patent/ES2069572T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H01L23/08—Containers; Seals characterised by the material of the container or its electrical properties the material being an electrical insulator, e.g. glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

CHIP DE CIRCUITO INTEGRADO (IC) QUE ESTA FORMADO MEDIANTE LA EXTENSION DE TODAS LAS DIMENSIONES DE UN CIRCUITO INTEGRADO CONVENCIONAL SOBRE UN SUBSTRATO SEMICONDUCTOR, TIPICAMENTE UNA PRIMERA PLAQUITA DE SILICE, PARA PROPORCIONAR UNA BANDA INTEGRAL DE MATERIAL SEMICONDUCTOR ALREDEDOR DEL MISMO SOBRE LA QUE SE FORMA UNA SERIE DE CHIPS DE CIRCUITO INTEGRADO DE UNA PARTE DE ENTRADA/SALIDA QUE SE EXTIENDE A LO LARGO DE LA BANDA. UN BORDE INFERIOR PERIFERICO DE UNA COFIA DISCONTINUA DEL MISMO MATERIAL CONDUCTOR, POR EJEMPLO SILICE, SE HALLA FIJADA DE FORMA ESTANCA ALREDEDOR DE UNA PERIFERIA INTERIOR DE LA BANDA DE LA SERIE DE CHIPS Y FUERA DEL AREA ACTIVA DEL CIRCUITO INTEGRADO, DE FORMA QUE LA COFIA INTERIORMENTE ESPACIADA CUBRE EL AREA ACTIVA DEL CIRCUITO, EXPONIENDOSE LAS PARTES DE ENTRADA/SALIDA. LAS COFIAS PUEDEN REALIZARSE POR FOTOLITOGRAFIA Y TECNICAS DE MICROGRABADO A PARTIR DE UNA SEGUNDA PLAQUITA SEMICONDUCTORA DEL MISMO TIPO QUE LA PLAQUITA DEL CIRCUITO INTEGRADO. LA METALIZACION SE EXTIENDE SOBRE LA PRIMERA PLAQUITA DESDE LAS PARTES DE CONEXION DEL AREA DEL CIRCUITO ACTIVO HASTA LAS PARTES DE ENTRADA/SALIDA EXPUESTAS Y EXTENDIDAS EXTERIORES A LA COFIA. EL CIRCUITO INTEGRADO PUEDE SER EXAMINADO A FINES DE COMPROBACION ANTES DE REALIZAR EL CUBRIMIENTO. SE EVITA LA UTILIZACION DE BASTIDORES DE PLOMO, PROCESOS DE ENCAPSULACION DE PLASTICO Y ALOJAMIENTOS CERAMICOS, A LA VEZ QUE SE MAXIMIZA EL USO DE MATERIALES COMPATIBLES QUE TIENEN EL MISMO COEFICIENTE DE EXPANSION TERMICA. EN UN DISEÑO, ESTA REALIZADO POR COMPLETO CON SILICE.
ES89200445T 1988-03-01 1989-02-22 Encapsulado y metodo de un chip de circuito integrado. Expired - Lifetime ES2069572T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/162,716 US4907065A (en) 1988-03-01 1988-03-01 Integrated circuit chip sealing assembly

Publications (1)

Publication Number Publication Date
ES2069572T3 true ES2069572T3 (es) 1995-05-16

Family

ID=22586851

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89200445T Expired - Lifetime ES2069572T3 (es) 1988-03-01 1989-02-22 Encapsulado y metodo de un chip de circuito integrado.

Country Status (5)

Country Link
US (1) US4907065A (es)
EP (1) EP0331245B1 (es)
JP (1) JP2557974B2 (es)
DE (1) DE68920603T2 (es)
ES (1) ES2069572T3 (es)

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US5412247A (en) * 1989-07-28 1995-05-02 The Charles Stark Draper Laboratory, Inc. Protection and packaging system for semiconductor devices
EP0431261A1 (en) * 1989-12-07 1991-06-12 International Business Machines Corporation Integrated circuit package with cap and device of the same material
US5323051A (en) * 1991-12-16 1994-06-21 Motorola, Inc. Semiconductor wafer level package
JP3613838B2 (ja) * 1995-05-18 2005-01-26 株式会社デンソー 半導体装置の製造方法
US5744084A (en) * 1995-07-24 1998-04-28 Lsi Logic Corporation Method of improving molding of an overmolded package body on a substrate
US5604160A (en) * 1996-07-29 1997-02-18 Motorola, Inc. Method for packaging semiconductor devices
JP3340333B2 (ja) * 1996-12-26 2002-11-05 株式会社東芝 半導体装置及びその製造方法
DE19856331B4 (de) * 1998-12-07 2009-01-02 Robert Bosch Gmbh Verfahren zur Eingehäusung elektronischer Bauelemente
US7345316B2 (en) * 2000-10-25 2008-03-18 Shipley Company, L.L.C. Wafer level packaging for optoelectronic devices
US6932519B2 (en) 2000-11-16 2005-08-23 Shipley Company, L.L.C. Optical device package
US6827503B2 (en) * 2000-12-01 2004-12-07 Shipley Company, L.L.C. Optical device package having a configured frame
US7022546B2 (en) * 2000-12-05 2006-04-04 Analog Devices, Inc. Method and device for protecting micro electromechanical systems structures during dicing of a wafer
US6883977B2 (en) * 2000-12-14 2005-04-26 Shipley Company, L.L.C. Optical device package for flip-chip mounting
US6465280B1 (en) 2001-03-07 2002-10-15 Analog Devices, Inc. In-situ cap and method of fabricating same for an integrated circuit device
US6828663B2 (en) * 2001-03-07 2004-12-07 Teledyne Technologies Incorporated Method of packaging a device with a lead frame, and an apparatus formed therefrom
US7279787B1 (en) 2001-12-31 2007-10-09 Richard S. Norman Microelectronic complex having clustered conductive members
US7275312B2 (en) * 2003-06-30 2007-10-02 Intel Corporation Apparatus for precise alignment of packaging caps on a substrate
JP2006109400A (ja) * 2004-09-13 2006-04-20 Seiko Epson Corp 電子部品、回路基板、電子機器、電子部品の製造方法
DE102006019080B3 (de) * 2006-04-25 2007-08-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Herstellungsverfahren für ein gehäustes Bauelement
US7656236B2 (en) * 2007-05-15 2010-02-02 Teledyne Wireless, Llc Noise canceling technique for frequency synthesizer
US8179045B2 (en) * 2008-04-22 2012-05-15 Teledyne Wireless, Llc Slow wave structure having offset projections comprised of a metal-dielectric composite stack
US8723343B2 (en) * 2011-03-14 2014-05-13 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor with energy-harvesting device
US9202660B2 (en) 2013-03-13 2015-12-01 Teledyne Wireless, Llc Asymmetrical slow wave structures to eliminate backward wave oscillations in wideband traveling wave tubes
TWI545714B (zh) * 2015-03-06 2016-08-11 矽品精密工業股份有限公司 電子封裝件及其製法

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JPS55128846A (en) * 1979-03-28 1980-10-06 Hitachi Ltd Semiconductor device
JPS5612760A (en) * 1979-07-10 1981-02-07 Nec Corp Multi chip lsi package
US4355463A (en) * 1980-03-24 1982-10-26 National Semiconductor Corporation Process for hermetically encapsulating semiconductor devices
FR2501414A1 (fr) * 1981-03-06 1982-09-10 Thomson Csf Microboitier d'encapsulation de pastilles de semi-conducteur, testable apres soudure sur un substrat
JPS58166753A (ja) * 1982-03-27 1983-10-01 Toshiba Corp 半導体装置
JPS6084842A (ja) * 1983-10-14 1985-05-14 Mitsubishi Electric Corp 半導体集積回路パツケ−ジ
JPS60100450A (ja) * 1983-11-07 1985-06-04 Disco Abrasive Sys Ltd 半導体ウエーハ装着及び切断装置
DE3512628A1 (de) * 1984-04-11 1985-10-17 Moran, Peter, Cork Packung fuer eine integrierte schaltung
JPS62104056A (ja) * 1985-07-08 1987-05-14 Nec Corp 半導体部品の実装構造
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Also Published As

Publication number Publication date
DE68920603T2 (de) 1995-05-18
US4907065A (en) 1990-03-06
JPH01315165A (ja) 1989-12-20
EP0331245A2 (en) 1989-09-06
EP0331245B1 (en) 1995-01-18
JP2557974B2 (ja) 1996-11-27
DE68920603D1 (de) 1995-03-02
EP0331245A3 (en) 1991-05-08

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