ES2056232T3 - Metodo para fabricar una oblea plana. - Google Patents

Metodo para fabricar una oblea plana.

Info

Publication number
ES2056232T3
ES2056232T3 ES89313008T ES89313008T ES2056232T3 ES 2056232 T3 ES2056232 T3 ES 2056232T3 ES 89313008 T ES89313008 T ES 89313008T ES 89313008 T ES89313008 T ES 89313008T ES 2056232 T3 ES2056232 T3 ES 2056232T3
Authority
ES
Spain
Prior art keywords
thin
polished
nitride
slice
slices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89313008T
Other languages
English (en)
Inventor
Jeffrey T Koze
Anton Johann Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of ES2056232T3 publication Critical patent/ES2056232T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H01L21/31056—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching the removal being a selective chemical etching step, e.g. selective dry etching through a mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

UN PERFECCIONAMIENTO EN LA LISURA DE RODAJAS DELGADAS Y PULIDAS DE SILICIO SE OBTIENE MEDIANTE LA DISMINUCION DEL TIEMPO CONSUMIDO EN ALISAR LA RODAJA DELGADA Y PULIDA. DESPUES DE UNA OPERACION CONVENCIONAL DE SOLAPAMIENTO, LA RODAJA DELGADA Y PULIDA SE REVISTE CON UN REVESTIMIENTO RESISTENTE A LA CORROSION, TIPICAMENTE NITRURO DE SILICIO. UNA FASE DE ALISAMIENTO ELIMINA EL REVESTIMIENTO DE NITRURO SOBRE LAS SUPERFICIES PLANAS DE LA RODAJA DELGADA Y PULIDA, PERO DEJA UN REVESTIMIENTO DE NITRURO SOBRE LOS LATERALES DE HOYOS QUE SE FORMAN EN LA OPERACION DE SOLAPAMIENTO. LA RODAJA DELGADA Y PULIDA SE TRATA DESPUES AL AGUA FUERTE, TIPICAMENTE EN KOH, PARA ELIMINAR LA SUPERFICIE DE SILICIO HASTA DEBAJO DE LA PROFUNDIDAD DE LOS HOYOS. EL CORTE POCO PROFUNDO O REBAJO DEL REVESTIMIENTO DE NITRURO ELIMINA LOS HOYOS, O DEJA PROTUSIONES RELATIVAMENTE PEQUEÑAS EN SU LUGAR. LAS PROTUSIONES PUEDEN ELIMINARSE MEDIANTE UNA OPERACION BREVE DE ALISAMIENTO. TAMBIEN SON POSIBLES OTROS TIPOS DE RODAJAS DELGADAS Y PULIDAS Y MATERIALES RESISTENTES A LA CORROSION. CIRCUITOS INTEGRADOS SE FORMAN TIPICAMENTE SOBRE LAS RODAJAS DELGADAS Y PULIDAS MEDIANTE TECNICAS LITOGRAFICAS QUE, VENTAJOSAMENTE, UTILIZAN LA LISURA PERFECCIONADA.
ES89313008T 1988-12-23 1989-12-13 Metodo para fabricar una oblea plana. Expired - Lifetime ES2056232T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/290,653 US4874463A (en) 1988-12-23 1988-12-23 Integrated circuits from wafers having improved flatness

Publications (1)

Publication Number Publication Date
ES2056232T3 true ES2056232T3 (es) 1994-10-01

Family

ID=23116985

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89313008T Expired - Lifetime ES2056232T3 (es) 1988-12-23 1989-12-13 Metodo para fabricar una oblea plana.

Country Status (6)

Country Link
US (1) US4874463A (es)
EP (1) EP0375258B1 (es)
JP (1) JPH069194B2 (es)
DE (1) DE68916393T2 (es)
ES (1) ES2056232T3 (es)
HK (1) HK135295A (es)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391798B1 (en) 1987-02-27 2002-05-21 Agere Systems Guardian Corp. Process for planarization a semiconductor substrate
EP0368584B1 (en) * 1988-11-09 1997-03-19 Sony Corporation Method of manufacturing a semiconductor wafer
GB2227362B (en) * 1989-01-18 1992-11-04 Gen Electric Co Plc Electronic devices
US5142828A (en) * 1990-06-25 1992-09-01 Microelectronics And Computer Technology Corporation Correcting a defective metallization layer on an electronic component by polishing
US5137597A (en) * 1991-04-11 1992-08-11 Microelectronics And Computer Technology Corporation Fabrication of metal pillars in an electronic component using polishing
EP0529888A1 (en) * 1991-08-22 1993-03-03 AT&T Corp. Removal of substrate perimeter material
EP0619495B1 (de) * 1993-04-05 1997-05-21 Siemens Aktiengesellschaft Verfahren zur Herstellung von Tunneleffekt-Sensoren
US5356513A (en) * 1993-04-22 1994-10-18 International Business Machines Corporation Polishstop planarization method and structure
US5473433A (en) * 1993-12-07 1995-12-05 At&T Corp. Method of high yield manufacture of VLSI type integrated circuit devices by determining critical surface characteristics of mounting films
US5733175A (en) * 1994-04-25 1998-03-31 Leach; Michael A. Polishing a workpiece using equal velocity at all points overlapping a polisher
US5607341A (en) 1994-08-08 1997-03-04 Leach; Michael A. Method and structure for polishing a wafer during manufacture of integrated circuits
US5885900A (en) * 1995-11-07 1999-03-23 Lucent Technologies Inc. Method of global planarization in fabricating integrated circuit devices
US5766971A (en) * 1996-12-13 1998-06-16 International Business Machines Corporation Oxide strip that improves planarity
US6514875B1 (en) 1997-04-28 2003-02-04 The Regents Of The University Of California Chemical method for producing smooth surfaces on silicon wafers
US6019806A (en) * 1998-01-08 2000-02-01 Sees; Jennifer A. High selectivity slurry for shallow trench isolation processing
CN1347566A (zh) * 1999-04-16 2002-05-01 东京电子株式会社 半导体器件的制造方法及其制造生产线
US6600557B1 (en) * 1999-05-21 2003-07-29 Memc Electronic Materials, Inc. Method for the detection of processing-induced defects in a silicon wafer
US6416391B1 (en) 2000-02-28 2002-07-09 Seh America, Inc. Method of demounting silicon wafers after polishing
US6446948B1 (en) 2000-03-27 2002-09-10 International Business Machines Corporation Vacuum chuck for reducing distortion of semiconductor and GMR head wafers during processing

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4278987A (en) * 1977-10-17 1981-07-14 Hitachi, Ltd. Junction isolated IC with thick EPI portion having sides at least 20 degrees from (110) orientations
US4331546A (en) * 1979-01-31 1982-05-25 Mobil Oil Corporation Lubricant composition containing phosphite-diarylamine-carbonyl compound reaction product
US4251300A (en) * 1979-05-14 1981-02-17 Fairchild Camera And Instrument Corporation Method for forming shaped buried layers in semiconductor devices utilizing etching, epitaxial deposition and oxide formation
US4588421A (en) * 1984-10-15 1986-05-13 Nalco Chemical Company Aqueous silica compositions for polishing silicon wafers
US4671851A (en) * 1985-10-28 1987-06-09 International Business Machines Corporation Method for removing protuberances at the surface of a semiconductor wafer using a chem-mech polishing technique
US4735679A (en) * 1987-03-30 1988-04-05 International Business Machines Corporation Method of improving silicon-on-insulator uniformity

Also Published As

Publication number Publication date
DE68916393D1 (de) 1994-07-28
EP0375258B1 (en) 1994-06-22
EP0375258A2 (en) 1990-06-27
DE68916393T2 (de) 1994-12-22
JPH02226723A (ja) 1990-09-10
US4874463A (en) 1989-10-17
HK135295A (en) 1995-09-01
JPH069194B2 (ja) 1994-02-02
EP0375258A3 (en) 1991-03-20

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