ES2047387T3 - Circuito de constante de tiempo regulable y aplicacion a un circuito de retardo regulable. - Google Patents
Circuito de constante de tiempo regulable y aplicacion a un circuito de retardo regulable.Info
- Publication number
- ES2047387T3 ES2047387T3 ES91402288T ES91402288T ES2047387T3 ES 2047387 T3 ES2047387 T3 ES 2047387T3 ES 91402288 T ES91402288 T ES 91402288T ES 91402288 T ES91402288 T ES 91402288T ES 2047387 T3 ES2047387 T3 ES 2047387T3
- Authority
- ES
- Spain
- Prior art keywords
- circuit
- capacity
- time constant
- adjustable
- application
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/26—Time-delay networks
- H03H11/265—Time-delay networks with adjustable delay
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
- H03K2005/00058—Variable delay controlled by a digital setting
- H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/0015—Layout of the delay element
- H03K2005/00195—Layout of the delay element using FET's
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Networks Using Active Elements (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Logic Circuits (AREA)
Abstract
EL CIRCUITO CON CONSTANTE DE TIEMPO SEGUN LA INVENCION LLEVA VARIAS PUERTAS DE TRANSFERENCIA (G0, G1,...,GN) COMPUESTAS DE TRANSISTORES DE TIPO MOS, CUYOS CAMINOS DRENAJE-FUENTE CONSTITUYEN ELEMENTOS RESISTENTES. LA CONSTANTE DE TIEMPO ES REGULABLE ACTIVANDO SELECTIVAMENTE (RE0, RE1,..., REN) LAS PUERTAS DE TRANSFERENCIA, SIENDO LA CAPACIDAD DEL CIRCUITO LA CAPACIDAD DE ESTRUCTURA DE LOS TRANSISTORES MOS. PARA CONSERVAR EN LA CAPACIDAD UN VALOR CONSTANTE, CADA PUERTA DE TRANSFERENCIA (G0, G1,...,GN) ESTA ASOCIADA A UN CIRCUITO (GC0, GC1,... GCN), DE COMPENSACION QUE, CUANDO ESTA ACTIVADO INTRODUCE UNA CAPACIDAD (C0, C1,...CN) DE IGUAL VALOR QUE LA CAPACIDAD DE LA PUERTA EN ESTADO CONDUCTOR. LA INVENCION SE REFIERE TAMBIEN A UN CIRCUITO DE RETARDO QUE UTILIZA EL CIRCUITO CON CONSTANTE DE TIEMPO. APLICACION EN PARTICULAR EN EL AJUSTE DE FASE DE SEÑALES DE RELOJ DE UN SISTEMA SINCRONO.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9010579A FR2666183B1 (fr) | 1990-08-23 | 1990-08-23 | Circuit a constante de temps reglable et application a un circuit a retard reglable. |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2047387T3 true ES2047387T3 (es) | 1994-02-16 |
Family
ID=9399800
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES91402288T Expired - Lifetime ES2047387T3 (es) | 1990-08-23 | 1991-08-21 | Circuito de constante de tiempo regulable y aplicacion a un circuito de retardo regulable. |
Country Status (6)
Country | Link |
---|---|
US (1) | US5185540A (es) |
EP (1) | EP0474534B1 (es) |
JP (1) | JPH0744437B2 (es) |
DE (1) | DE69100528T2 (es) |
ES (1) | ES2047387T3 (es) |
FR (1) | FR2666183B1 (es) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5764093A (en) * | 1981-11-28 | 1998-06-09 | Advantest Corporation | Variable delay circuit |
KR970005124B1 (ko) * | 1991-08-14 | 1997-04-12 | 가부시끼가이샤 아드반테스트 | 가변지연회로 |
FR2690022B1 (fr) * | 1992-03-24 | 1997-07-11 | Bull Sa | Circuit a retard variable. |
FR2696061B1 (fr) * | 1992-09-22 | 1994-12-02 | Rainard Jean Luc | Procédé pour retarder temporellement un signal et circuit à retard correspondant. |
US5412263A (en) * | 1992-09-30 | 1995-05-02 | At&T Corp. | Multiple control voltage generation for MOSFET resistors |
US5650739A (en) * | 1992-12-07 | 1997-07-22 | Dallas Semiconductor Corporation | Programmable delay lines |
TW253083B (es) * | 1993-10-05 | 1995-08-01 | Advanced Micro Devices Inc | |
JP3238562B2 (ja) * | 1994-03-03 | 2001-12-17 | 株式会社東芝 | 半導体集積回路 |
FR2720852B1 (fr) * | 1994-06-01 | 1996-08-02 | Matra Mhs | Dispositif de détection de transition engendrant une impulsion de durée variable. |
US5729158A (en) * | 1995-07-07 | 1998-03-17 | Sun Microsystems, Inc. | Parametric tuning of an integrated circuit after fabrication |
US5731725A (en) * | 1995-12-15 | 1998-03-24 | Unisys Corporation | Precision delay circuit |
JP3175634B2 (ja) * | 1997-04-18 | 2001-06-11 | 日本電気株式会社 | 半導体遅延回路 |
JP3560780B2 (ja) * | 1997-07-29 | 2004-09-02 | 富士通株式会社 | 可変遅延回路及び半導体集積回路装置 |
JP2002015569A (ja) * | 2000-06-27 | 2002-01-18 | Mitsubishi Electric Corp | 半導体装置 |
US6650159B2 (en) * | 2002-03-29 | 2003-11-18 | Intel Corporation | Method and apparatus for precise signal interpolation |
DE10236478B4 (de) * | 2002-08-08 | 2010-07-29 | Deutsch-Französisches Forschungsinstitut Saint-Louis, Saint-Louis | Modulare Pulsstromversorgung und Verfahren hierzu |
KR100532955B1 (ko) * | 2003-06-16 | 2005-12-01 | 주식회사 하이닉스반도체 | 반도체 장치의 딜레이 공유 회로 |
JP4687882B2 (ja) * | 2005-07-29 | 2011-05-25 | スタンレー電気株式会社 | 静電容量式施錠スイッチ |
DE102015015479B3 (de) | 2015-11-28 | 2017-03-30 | Audi Ag | Schaltungsanordnung zum Ermitteln einer Stromstärke eines elektrischen Stroms |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL7014137A (es) * | 1970-09-25 | 1972-03-28 | ||
JPS6152022A (ja) * | 1984-08-22 | 1986-03-14 | Hitachi Ltd | 半導体集積回路装置 |
JPH0681018B2 (ja) * | 1986-03-31 | 1994-10-12 | 三菱電機株式会社 | 半導体集積回路 |
ATE68298T1 (de) * | 1987-03-16 | 1991-10-15 | Siemens Ag | Gatterschaltung mit mos-transistoren. |
US5111085A (en) * | 1987-04-29 | 1992-05-05 | Ncr Corporation | Digitally controlled delay circuit |
US5028824A (en) * | 1989-05-05 | 1991-07-02 | Harris Corporation | Programmable delay circuit |
-
1990
- 1990-08-23 FR FR9010579A patent/FR2666183B1/fr not_active Expired - Fee Related
-
1991
- 1991-08-14 US US07/744,951 patent/US5185540A/en not_active Expired - Lifetime
- 1991-08-21 ES ES91402288T patent/ES2047387T3/es not_active Expired - Lifetime
- 1991-08-21 EP EP91402288A patent/EP0474534B1/fr not_active Expired - Lifetime
- 1991-08-21 DE DE91402288T patent/DE69100528T2/de not_active Expired - Fee Related
- 1991-08-23 JP JP3237068A patent/JPH0744437B2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
FR2666183B1 (fr) | 1992-11-06 |
JPH0744437B2 (ja) | 1995-05-15 |
US5185540A (en) | 1993-02-09 |
EP0474534A1 (fr) | 1992-03-11 |
JPH04363908A (ja) | 1992-12-16 |
EP0474534B1 (fr) | 1993-10-20 |
FR2666183A1 (fr) | 1992-02-28 |
DE69100528D1 (de) | 1993-11-25 |
DE69100528T2 (de) | 1994-02-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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