ES2033742T3 - Aparato de sincronizacion de cambio de nivel por interrupcion de multiprocesadores. - Google Patents

Aparato de sincronizacion de cambio de nivel por interrupcion de multiprocesadores.

Info

Publication number
ES2033742T3
ES2033742T3 ES198787109194T ES87109194T ES2033742T3 ES 2033742 T3 ES2033742 T3 ES 2033742T3 ES 198787109194 T ES198787109194 T ES 198787109194T ES 87109194 T ES87109194 T ES 87109194T ES 2033742 T3 ES2033742 T3 ES 2033742T3
Authority
ES
Spain
Prior art keywords
interruption
level
circuits
bus
units
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES198787109194T
Other languages
English (en)
Inventor
James W. Keeley
George J. Barlow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Application granted granted Critical
Publication of ES2033742T3 publication Critical patent/ES2033742T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

EL APARATO ESTA INCLUIDO DENTRO DE LOS CIRCUITOS DE CONEXION DE BUS DE CADA UNIDAD DE PROCESO DE UN SISTEMA DE MULTIPROCESO QUE SE CONECTA EN COMUN CON LAS OTRAS UNIDADES DEL SISTEMA MEDIANTE UN BUS DE SISTEMA ASINCRONO. EL APARATO SE ACOPLA AL REGISTRO DE NIVEL DE LA UNIDAD DE PROCESO Y A LOS CIRCUITOS DE INTERRUPCION. EN RESPUESTA A UN COMANDO QUE ESPECIFICA UN CAMBIO DE NIVEL, EL APARATO CONDICIONA A ESOS CIRCUITOS PARA ALMACENAR EL NIVEL E INTERRUMPIR LAS SEÑALES APLICADAS AL BUS DEL SISTEMA COMO PARTE DEL COMANDO DE LA CPU DURANTE UN CICLO DE BUS DE OPERACION PERMITIDA A LA UNIDAD DE PROCESO EN UNA PRIORIDAD BASICA. ESTO ASEGURA UNA CONMUTACION FIABLE ENTRE LOS NIVELES DE INTERRUPCION Y LA NOTIFICACION DE TALES CAMBIOS DE NIVEL A LAS OTRAS UNIDADES DEL SISTEMA SIN INTERFERENCIA DE OTRAS UNIDADES DE PROCESO.
ES198787109194T 1986-06-27 1987-06-26 Aparato de sincronizacion de cambio de nivel por interrupcion de multiprocesadores. Expired - Lifetime ES2033742T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/879,858 US4802087A (en) 1986-06-27 1986-06-27 Multiprocessor level change synchronization apparatus

Publications (1)

Publication Number Publication Date
ES2033742T3 true ES2033742T3 (es) 1993-04-01

Family

ID=25375026

Family Applications (1)

Application Number Title Priority Date Filing Date
ES198787109194T Expired - Lifetime ES2033742T3 (es) 1986-06-27 1987-06-26 Aparato de sincronizacion de cambio de nivel por interrupcion de multiprocesadores.

Country Status (9)

Country Link
US (1) US4802087A (es)
EP (1) EP0251234B1 (es)
JP (1) JPH0786865B2 (es)
AU (1) AU597674B2 (es)
CA (1) CA1286415C (es)
DE (1) DE3780526T2 (es)
ES (1) ES2033742T3 (es)
MX (1) MX168705B (es)
YU (1) YU121287A (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01126751A (ja) * 1987-11-11 1989-05-18 Fujitsu Ltd グルーピング装置
EP0357075A3 (en) * 1988-09-02 1991-12-11 Fujitsu Limited Data control device and system using the same
US5072365A (en) * 1989-12-27 1991-12-10 Motorola, Inc. Direct memory access controller using prioritized interrupts for varying bus mastership
FR2680591B1 (fr) * 1991-08-22 1996-01-26 Telemecanique Controleur d'interruption programmable, systeme interruptif et procede de controle d'interruption.
US5301283A (en) * 1992-04-16 1994-04-05 Digital Equipment Corporation Dynamic arbitration for system bus control in multiprocessor data processing system
JP2008018340A (ja) * 2006-07-13 2008-01-31 Trinc:Kk 浮遊物捕捉装置および浮遊物反発装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3848233A (en) * 1971-11-01 1974-11-12 Bunker Ramo Method and apparatus for interfacing with a central processing unit
GB1448866A (en) * 1973-04-13 1976-09-08 Int Computers Ltd Microprogrammed data processing systems
US3999165A (en) * 1973-08-27 1976-12-21 Hitachi, Ltd. Interrupt information interface system
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system
US3984820A (en) * 1975-06-30 1976-10-05 Honeywell Information Systems, Inc. Apparatus for changing the interrupt level of a process executing in a data processing system
US4023143A (en) * 1975-10-28 1977-05-10 Cincinnati Milacron Inc. Fixed priority interrupt control circuit
US4035780A (en) * 1976-05-21 1977-07-12 Honeywell Information Systems, Inc. Priority interrupt logic circuits
US4271467A (en) * 1979-01-02 1981-06-02 Honeywell Information Systems Inc. I/O Priority resolver
US4459665A (en) * 1979-01-31 1984-07-10 Honeywell Information Systems Inc. Data processing system having centralized bus priority resolution
NL7907179A (nl) * 1979-09-27 1981-03-31 Philips Nv Signaalprocessorinrichting met voorwaardelijke- -interrupteenheid en multiprocessorsysteem met deze signaalprocessorinrichtingen.
US4470111A (en) * 1979-10-01 1984-09-04 Ncr Corporation Priority interrupt controller
JPS5827243A (ja) * 1981-08-08 1983-02-17 Nippon Telegr & Teleph Corp <Ntt> 情報処理方式
US4464717A (en) * 1982-03-31 1984-08-07 Honeywell Information Systems Inc. Multilevel cache system with graceful degradation capability
JPS6115260A (ja) * 1984-06-29 1986-01-23 Nec Corp デ−タ処理装置

Also Published As

Publication number Publication date
EP0251234B1 (en) 1992-07-22
AU597674B2 (en) 1990-06-07
JPH0786865B2 (ja) 1995-09-20
US4802087A (en) 1989-01-31
CA1286415C (en) 1991-07-16
YU121287A (en) 1990-06-30
EP0251234A3 (en) 1988-07-20
EP0251234A2 (en) 1988-01-07
AU7478787A (en) 1988-01-07
DE3780526T2 (de) 1992-12-17
JPS6332648A (ja) 1988-02-12
MX168705B (es) 1993-06-04
DE3780526D1 (de) 1992-08-27

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