JPS57191743A - Data transfer controlling circuit - Google Patents
Data transfer controlling circuitInfo
- Publication number
- JPS57191743A JPS57191743A JP56076330A JP7633081A JPS57191743A JP S57191743 A JPS57191743 A JP S57191743A JP 56076330 A JP56076330 A JP 56076330A JP 7633081 A JP7633081 A JP 7633081A JP S57191743 A JPS57191743 A JP S57191743A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data transfer
- external
- synchronizing
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
Abstract
PURPOSE:To obtain a circuit which does not require the design change for external conditions or the like and controls the high-speed data transfer with simple constitution, by providing specific external condition synchronizing means, processing order monitoring means, and cycle holding means. CONSTITUTION:A data transfer controlling circuit connected to a central processor or the like through a high-speed line 108 is provided with an external condition synchronizing circuit 115 which synchronizes analysis conditions for transmission/receiving or the like by a start command 119 from the external, a processing order monitoring circuit 113 where the processing instruction sequence for condition analysis and data analysis corresponding to the output of the circuit 115 is held in an ROM, and a cycle holding circuit 114 which secures the number of cycles required for each processing. Said ciruit 113 consists of, for example, an ROM10 where a program for line control is stored, an external condition synchronizing circuit 9, and synchronizing circuits 8 and 11.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56076330A JPS57191743A (en) | 1981-05-19 | 1981-05-19 | Data transfer controlling circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56076330A JPS57191743A (en) | 1981-05-19 | 1981-05-19 | Data transfer controlling circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57191743A true JPS57191743A (en) | 1982-11-25 |
JPS6148188B2 JPS6148188B2 (en) | 1986-10-23 |
Family
ID=13602336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56076330A Granted JPS57191743A (en) | 1981-05-19 | 1981-05-19 | Data transfer controlling circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57191743A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0315515Y2 (en) * | 1985-03-14 | 1991-04-04 |
-
1981
- 1981-05-19 JP JP56076330A patent/JPS57191743A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6148188B2 (en) | 1986-10-23 |
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