ES2017735B3 - Procedimiento de enlace programable por laser de dos conductores superpuestos de la red de interconexion de un circuito integrado, y circuito integrado resultante. - Google Patents

Procedimiento de enlace programable por laser de dos conductores superpuestos de la red de interconexion de un circuito integrado, y circuito integrado resultante.

Info

Publication number
ES2017735B3
ES2017735B3 ES87401535T ES87401535T ES2017735B3 ES 2017735 B3 ES2017735 B3 ES 2017735B3 ES 87401535 T ES87401535 T ES 87401535T ES 87401535 T ES87401535 T ES 87401535T ES 2017735 B3 ES2017735 B3 ES 2017735B3
Authority
ES
Spain
Prior art keywords
integrated circuit
interconnection network
linking procedure
laser programmable
overlapping conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES87401535T
Other languages
English (en)
Inventor
Alain Boudou
Marie-Francoise Bonnal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of ES2017735B3 publication Critical patent/ES2017735B3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/071—Heating, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
ES87401535T 1986-07-11 1987-07-01 Procedimiento de enlace programable por laser de dos conductores superpuestos de la red de interconexion de un circuito integrado, y circuito integrado resultante. Expired - Lifetime ES2017735B3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8610205A FR2601500B1 (fr) 1986-07-11 1986-07-11 Procede de liaison programmable par laser de deux conducteurs superposes du reseau d'interconnexion d'un circuit integre, et circuit integre en resultant

Publications (1)

Publication Number Publication Date
ES2017735B3 true ES2017735B3 (es) 1991-03-01

Family

ID=9337389

Family Applications (1)

Application Number Title Priority Date Filing Date
ES87401535T Expired - Lifetime ES2017735B3 (es) 1986-07-11 1987-07-01 Procedimiento de enlace programable por laser de dos conductores superpuestos de la red de interconexion de un circuito integrado, y circuito integrado resultante.

Country Status (6)

Country Link
US (2) US4916809A (es)
EP (1) EP0252814B1 (es)
JP (1) JPH061793B2 (es)
DE (1) DE3764892D1 (es)
ES (1) ES2017735B3 (es)
FR (1) FR2601500B1 (es)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5281553A (en) * 1987-07-02 1994-01-25 Bull, S.A. Method for controlling the state of conduction of an MOS transistor of an integrated circuit
FR2617637B1 (fr) * 1987-07-02 1989-10-27 Bull Sa Procede de commande de l'etat de conduction d'un transistor mos et circuit integre mettant en oeuvre le procede
US5223735A (en) * 1988-09-30 1993-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device in which circuit functions can be remedied or changed and the method for producing the same
US5614756A (en) * 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
US5780323A (en) * 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
US5166556A (en) * 1991-01-22 1992-11-24 Myson Technology, Inc. Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits
JP2695548B2 (ja) * 1991-09-04 1997-12-24 富士通株式会社 半導体装置
JP3272028B2 (ja) * 1992-05-13 2002-04-08 株式会社東芝 電子回路
IL103566A (en) * 1992-10-27 1995-06-29 Quick Tech Ltd Active matrix of a display panel
US5459355A (en) * 1992-12-09 1995-10-17 Intel Corporation Multiple layer programmable layout for version identification
US5316803A (en) * 1992-12-10 1994-05-31 International Business Machines Corporation Method for forming electrical interconnections in laminated vias
US5485031A (en) * 1993-11-22 1996-01-16 Actel Corporation Antifuse structure suitable for VLSI application
US5475246A (en) * 1993-12-20 1995-12-12 General Electric Company Repair line structure for thin film electronic devices
US5813881A (en) * 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
US5726482A (en) * 1994-02-08 1998-03-10 Prolinx Labs Corporation Device-under-test card for a burn-in board
US5917229A (en) * 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
US5808351A (en) * 1994-02-08 1998-09-15 Prolinx Labs Corporation Programmable/reprogramable structure using fuses and antifuses
US5537108A (en) * 1994-02-08 1996-07-16 Prolinx Labs Corporation Method and structure for programming fuses
US5572409A (en) * 1994-02-08 1996-11-05 Prolinx Labs Corporation Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board
US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5861325A (en) * 1994-03-10 1999-01-19 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
US5920789A (en) * 1994-10-11 1999-07-06 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
US5940727A (en) * 1994-10-11 1999-08-17 Massachusetts Institute Of Technology Technique for producing interconnecting conductive links
JPH09510320A (ja) 1994-03-10 1997-10-14 マサチユセツツ・インスチチユート・オブ・テクノロジー 接続用導電リンクの製造方法
US5585602A (en) * 1995-01-09 1996-12-17 Massachusetts Institute Of Technology Structure for providing conductive paths
US5464794A (en) * 1994-05-11 1995-11-07 United Microelectronics Corporation Method of forming contact openings having concavo-concave shape
US5962815A (en) * 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
US5506499A (en) * 1995-06-05 1996-04-09 Neomagic Corp. Multiple probing of an auxilary test pad which allows for reliable bonding to a primary bonding pad
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5728608A (en) * 1995-10-11 1998-03-17 Applied Komatsu Technology, Inc. Tapered dielectric etch in semiconductor devices
US5767575A (en) * 1995-10-17 1998-06-16 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US5872338A (en) * 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
JP3186664B2 (ja) * 1997-09-19 2001-07-11 日本電気株式会社 半導体装置およびその製造方法
US6034427A (en) * 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US6187652B1 (en) 1998-09-14 2001-02-13 Fujitsu Limited Method of fabrication of multiple-layer high density substrate
US6412168B1 (en) * 2000-09-06 2002-07-02 Visteon Global Tech, Inc. Method of making an electrical circuit board
US7316934B2 (en) * 2000-12-18 2008-01-08 Zavitan Semiconductors, Inc. Personalized hardware
US7485511B2 (en) * 2005-06-01 2009-02-03 Semiconductor Energy Laboratory Co., Ltd. Integrated circuit device and method for manufacturing integrated circuit device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3549432A (en) * 1968-07-15 1970-12-22 Texas Instruments Inc Multilayer microelectronic circuitry techniques
US3584183A (en) * 1968-10-03 1971-06-08 North American Rockwell Laser encoding of diode arrays
US4258468A (en) * 1978-12-14 1981-03-31 Western Electric Company, Inc. Forming vias through multilayer circuit boards
JPS5847596Y2 (ja) * 1979-09-05 1983-10-29 富士通株式会社 半導体装置
US4531144A (en) * 1982-05-14 1985-07-23 Burroughs Corporation Aluminum-refractory metal interconnect with anodized periphery
JPS59168652A (ja) * 1983-03-16 1984-09-22 Hitachi Ltd 素子修正方法及びその装置
CA1186070A (en) * 1983-06-17 1985-04-23 Iain D. Calder Laser activated polysilicon connections for redundancy
US4659427A (en) * 1984-12-31 1987-04-21 Gte Laboratories Incorporated Via formation for multilayered metalization
US4674176A (en) * 1985-06-24 1987-06-23 The United States Of America As Represented By The United States Department Of Energy Planarization of metal films for multilevel interconnects by pulsed laser heating
US4642160A (en) * 1985-08-12 1987-02-10 Interconnect Technology Inc. Multilayer circuit board manufacturing

Also Published As

Publication number Publication date
JPH061793B2 (ja) 1994-01-05
DE3764892D1 (de) 1990-10-18
EP0252814A1 (fr) 1988-01-13
JPS6329955A (ja) 1988-02-08
FR2601500B1 (fr) 1988-10-21
FR2601500A1 (fr) 1988-01-15
US4916809A (en) 1990-04-17
US4893167A (en) 1990-01-09
EP0252814B1 (fr) 1990-09-12

Similar Documents

Publication Publication Date Title
ES2017735B3 (es) Procedimiento de enlace programable por laser de dos conductores superpuestos de la red de interconexion de un circuito integrado, y circuito integrado resultante.
DE3774911D1 (de) Matrix-strukturierte multiplizierschaltung.
DE3688472D1 (de) Programmierbare logische schaltung.
FI871205A0 (fi) Anordning foer elektrostatisk beskiktning av foeremaol.
DE3751031T2 (de) Programmierbarer Difibrillator.
FI872612A0 (fi) Nytt antihypertensivt aemne.
DE3751541T2 (de) Anzeigeverfahren.
DE3787548D1 (de) Makrolid-verbindungen.
DE3878655T2 (de) Dc-ac-brueckenschaltung.
DE3786025D1 (de) Makrolid-verbindungen.
FI891559A0 (fi) Foerfarande foer framstaellning av lignocellulosamaterialfibrer innehaollande produkter.
FI873518A0 (fi) Foerfarande foer polymerisation av a-olefin.
DE3788413T2 (de) Filterschaltung.
DE3676897D1 (de) Ringlaserkreisel.
DE69005656T2 (de) Isolierter Anschluss und Modul.
FI882022A0 (fi) Foerfarande foer fastsaettning av faest- eller upphaengningsdon jaemte don foer foerfarandets genomfoerande.
DE209995T1 (de) Loetverfahren.
FI870103A0 (fi) Producering av humanserum albumin i en bacillus-stam.
DE3768729D1 (de) Kurzschlussschutz.
DE59009340D1 (de) Schaltungsanordnung zur Herstellung von Konferenzverbindungen.
DE3784601D1 (de) Schmelzsicherung.
FI871183A (fi) Magnetiseringsanordning foer magnetografisk inspektion av produkter.
DE3780699D1 (de) Loetverfahren.
DE59000144D1 (de) Ringlaserkreisel.
FI870572A0 (fi) Nytt foerfarande foer framstaellning av keramiska produkter.