DE3774911D1 - Matrix-strukturierte multiplizierschaltung. - Google Patents
Matrix-strukturierte multiplizierschaltung.Info
- Publication number
- DE3774911D1 DE3774911D1 DE8787104236T DE3774911T DE3774911D1 DE 3774911 D1 DE3774911 D1 DE 3774911D1 DE 8787104236 T DE8787104236 T DE 8787104236T DE 3774911 T DE3774911 T DE 3774911T DE 3774911 D1 DE3774911 D1 DE 3774911D1
- Authority
- DE
- Germany
- Prior art keywords
- structured
- matrix
- multiplier circuit
- multiplier
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
- G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
- G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
- G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61072947A JPS62229440A (ja) | 1986-03-31 | 1986-03-31 | 配列乗算器 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3774911D1 true DE3774911D1 (de) | 1992-01-16 |
Family
ID=13504083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8787104236T Expired - Lifetime DE3774911D1 (de) | 1986-03-31 | 1987-03-23 | Matrix-strukturierte multiplizierschaltung. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4825401A (de) |
EP (1) | EP0239899B1 (de) |
JP (1) | JPS62229440A (de) |
DE (1) | DE3774911D1 (de) |
Families Citing this family (54)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR920003908B1 (ko) * | 1987-11-19 | 1992-05-18 | 미쓰비시뎅끼 가부시끼가이샤 | 승산기(乘算器) |
US4989168A (en) * | 1987-11-30 | 1991-01-29 | Fujitsu Limited | Multiplying unit in a computer system, capable of population counting |
US4953119A (en) * | 1989-01-27 | 1990-08-28 | Hughes Aircraft Company | Multiplier circuit with selectively interconnected pipelined multipliers for selectively multiplication of fixed and floating point numbers |
EP0383965A1 (de) * | 1989-02-21 | 1990-08-29 | International Business Machines Corporation | Multiplizierwerk |
US5047973A (en) * | 1989-04-26 | 1991-09-10 | Texas Instruments Incorporated | High speed numerical processor for performing a plurality of numeric functions |
US5001662A (en) * | 1989-04-28 | 1991-03-19 | Apple Computer, Inc. | Method and apparatus for multi-gauge computation |
US5038315A (en) * | 1989-05-15 | 1991-08-06 | At&T Bell Laboratories | Multiplier circuit |
US5144576A (en) * | 1989-09-05 | 1992-09-01 | Cyrix Corporation | Signed digit multiplier |
US5040139A (en) * | 1990-04-16 | 1991-08-13 | Tran Dzung J | Transmission gate multiplexer (TGM) logic circuits and multiplier architectures |
JP2651267B2 (ja) * | 1990-07-26 | 1997-09-10 | 富士通株式会社 | 演算処理装置及び演算処理方法 |
US5162666A (en) * | 1991-03-15 | 1992-11-10 | Tran Dzung J | Transmission gate series multiplexer |
US5245564A (en) * | 1991-05-10 | 1993-09-14 | Weitek Corporation | Apparatus for multiplying operands |
US5255216A (en) * | 1991-08-16 | 1993-10-19 | International Business Machines Corporation | Reduced hardware look up table multiplier |
US5218562A (en) * | 1991-09-30 | 1993-06-08 | American Neuralogix, Inc. | Hamming data correlator having selectable word-length |
JPH05204609A (ja) * | 1992-01-13 | 1993-08-13 | Nec Corp | 乗算回路 |
DE4317074C1 (de) * | 1993-05-21 | 1994-06-23 | Itt Ind Gmbh Deutsche | Multiplizierer für reelle und komplexe Zahlen |
JP3637073B2 (ja) * | 1993-10-21 | 2005-04-06 | 株式会社東芝 | 倍精度・単精度・内積演算および複素乗算が可能な乗算器 |
EP0924601B1 (de) * | 1993-11-23 | 2001-09-26 | Hewlett-Packard Company, A Delaware Corporation | Parallele Datenverarbeitung in einem Einzelprozessor |
US5446651A (en) * | 1993-11-30 | 1995-08-29 | Texas Instruments Incorporated | Split multiply operation |
US5586070A (en) * | 1994-08-03 | 1996-12-17 | Chromatic Research, Inc. | Structure and method for embedding two small multipliers in a larger multiplier |
US6643765B1 (en) | 1995-08-16 | 2003-11-04 | Microunity Systems Engineering, Inc. | Programmable processor with group floating point operations |
US6295599B1 (en) * | 1995-08-16 | 2001-09-25 | Microunity Systems Engineering | System and method for providing a wide operand architecture |
US5751622A (en) * | 1995-10-10 | 1998-05-12 | Chromatic Research, Inc. | Structure and method for signed multiplication using large multiplier having two embedded signed multipliers |
US5761106A (en) * | 1996-06-24 | 1998-06-02 | Motorola, Inc. | Horizontally pipelined multiplier circuit |
US5880985A (en) * | 1996-10-18 | 1999-03-09 | Intel Corporation | Efficient combined array for 2n bit n bit multiplications |
JP3479438B2 (ja) * | 1997-09-18 | 2003-12-15 | 株式会社東芝 | 乗算回路 |
US6026483A (en) * | 1997-10-23 | 2000-02-15 | Advanced Micro Devices, Inc. | Method and apparatus for simultaneously performing arithmetic on two or more pairs of operands |
US6269384B1 (en) | 1998-03-27 | 2001-07-31 | Advanced Micro Devices, Inc. | Method and apparatus for rounding and normalizing results within a multiplier |
US6085213A (en) * | 1997-10-23 | 2000-07-04 | Advanced Micro Devices, Inc. | Method and apparatus for simultaneously multiplying two or more independent pairs of operands and summing the products |
US6144980A (en) * | 1998-01-28 | 2000-11-07 | Advanced Micro Devices, Inc. | Method and apparatus for performing multiple types of multiplication including signed and unsigned multiplication |
US6134574A (en) * | 1998-05-08 | 2000-10-17 | Advanced Micro Devices, Inc. | Method and apparatus for achieving higher frequencies of exactly rounded results |
WO1999021078A2 (en) * | 1997-10-23 | 1999-04-29 | Advanced Micro Devices, Inc. | A method and apparatus for multi-function arithmetic |
US6223198B1 (en) | 1998-08-14 | 2001-04-24 | Advanced Micro Devices, Inc. | Method and apparatus for multi-function arithmetic |
US6115732A (en) * | 1998-05-08 | 2000-09-05 | Advanced Micro Devices, Inc. | Method and apparatus for compressing intermediate products |
US6223192B1 (en) | 1997-10-23 | 2001-04-24 | Advanced Micro Devices, Inc. | Bipartite look-up table with output values having minimized absolute error |
US6115733A (en) * | 1997-10-23 | 2000-09-05 | Advanced Micro Devices, Inc. | Method and apparatus for calculating reciprocals and reciprocal square roots |
US6393554B1 (en) | 1998-01-28 | 2002-05-21 | Advanced Micro Devices, Inc. | Method and apparatus for performing vector and scalar multiplication and calculating rounded products |
US5999959A (en) * | 1998-02-18 | 1999-12-07 | Quantum Corporation | Galois field multiplier |
US6088800A (en) | 1998-02-27 | 2000-07-11 | Mosaid Technologies, Incorporated | Encryption processor with shared memory interconnect |
RU2131145C1 (ru) | 1998-06-16 | 1999-05-27 | Закрытое акционерное общество Научно-технический центр "Модуль" | Нейропроцессор, устройство для вычисления функций насыщения, вычислительное устройство и сумматор |
US6249799B1 (en) * | 1998-06-19 | 2001-06-19 | Ati International Srl | Selective carry boundary |
JP3139466B2 (ja) * | 1998-08-28 | 2001-02-26 | 日本電気株式会社 | 乗算器及び積和演算器 |
KR100324313B1 (ko) * | 1998-11-02 | 2002-06-22 | 김영환 | n비트와n/2비트를연산하는곱셈기 |
US6523055B1 (en) | 1999-01-20 | 2003-02-18 | Lsi Logic Corporation | Circuit and method for multiplying and accumulating the sum of two products in a single cycle |
US6692534B1 (en) * | 1999-09-08 | 2004-02-17 | Sun Microsystems, Inc. | Specialized booth decoding apparatus |
AU2002339867A1 (en) | 2001-09-04 | 2003-03-18 | Microunity Systems Engineering, Inc. | System and method for performing multiplication |
KR100430526B1 (ko) * | 2001-12-14 | 2004-05-10 | 한국전자통신연구원 | 수정된 부스 디코더를 적용한 고정 길이 승산기 및 그승산 방법 |
US6978426B2 (en) * | 2002-04-10 | 2005-12-20 | Broadcom Corporation | Low-error fixed-width modified booth multiplier |
US7269616B2 (en) * | 2003-03-21 | 2007-09-11 | Stretch, Inc. | Transitive processing unit for performing complex operations |
US7506017B1 (en) | 2004-05-25 | 2009-03-17 | Altera Corporation | Verifiable multimode multipliers |
US8706793B1 (en) * | 2009-04-02 | 2014-04-22 | Xilinx, Inc. | Multiplier circuits with optional shift function |
US8527572B1 (en) * | 2009-04-02 | 2013-09-03 | Xilinx, Inc. | Multiplier architecture utilizing a uniform array of logic blocks, and methods of using the same |
US9002915B1 (en) | 2009-04-02 | 2015-04-07 | Xilinx, Inc. | Circuits for shifting bussed data |
US9411554B1 (en) | 2009-04-02 | 2016-08-09 | Xilinx, Inc. | Signed multiplier circuit utilizing a uniform array of logic blocks |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3814924A (en) * | 1973-03-12 | 1974-06-04 | Control Data Corp | Pipeline binary multiplier |
DE2647262A1 (de) * | 1975-11-04 | 1977-05-05 | Motorola Inc | Multiplizierschaltung |
US4153938A (en) * | 1977-08-18 | 1979-05-08 | Monolithic Memories Inc. | High speed combinatorial digital multiplier |
JPS59149540A (ja) * | 1983-02-15 | 1984-08-27 | Toshiba Corp | 分割型乗算器 |
JPS60205746A (ja) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | 配列乗算器 |
US4575812A (en) * | 1984-05-31 | 1986-03-11 | Motorola, Inc. | X×Y Bit array multiplier/accumulator circuit |
-
1986
- 1986-03-31 JP JP61072947A patent/JPS62229440A/ja active Granted
-
1987
- 1987-03-12 US US07/025,201 patent/US4825401A/en not_active Expired - Lifetime
- 1987-03-23 DE DE8787104236T patent/DE3774911D1/de not_active Expired - Lifetime
- 1987-03-23 EP EP87104236A patent/EP0239899B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS62229440A (ja) | 1987-10-08 |
JPH0431413B2 (de) | 1992-05-26 |
US4825401A (en) | 1989-04-25 |
EP0239899A1 (de) | 1987-10-07 |
EP0239899B1 (de) | 1991-12-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8320 | Willingness to grant licences declared (paragraph 23) |