ES2008232A6 - Sistema para interconectar equipos asincronos por medio de memorias. - Google Patents

Sistema para interconectar equipos asincronos por medio de memorias.

Info

Publication number
ES2008232A6
ES2008232A6 ES8702736A ES8702736A ES2008232A6 ES 2008232 A6 ES2008232 A6 ES 2008232A6 ES 8702736 A ES8702736 A ES 8702736A ES 8702736 A ES8702736 A ES 8702736A ES 2008232 A6 ES2008232 A6 ES 2008232A6
Authority
ES
Spain
Prior art keywords
ram
memory
counter
counters
apparatuses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8702736A
Other languages
English (en)
Inventor
Silvio Cucchi
Vittorio Corradi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TELETRA TELEFONIA ELECTTRONICA
Original Assignee
TELETRA TELEFONIA ELECTTRONICA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TELETRA TELEFONIA ELECTTRONICA filed Critical TELETRA TELEFONIA ELECTTRONICA
Publication of ES2008232A6 publication Critical patent/ES2008232A6/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Abstract

SISTEMA PARA INTERCONECTAR EQUIPOS ASINCRONOS POR MEDIO DE MEMORIAS, EL CUAL COMPRENDE ESENCIALMENTE UNA RAM (MEMORIA DE ACCESO DIRECTO) DE PUERTA UNICA SINCRONIZADA CON SOLO UNO DE LOS DOS RELOJES DE LOS EQUIPOS ANTES MENCIONADOS (EN PARTICULAR CON EL RELOJ MAESTRO) Y UNA MEMORIA FIFO (PRIMERO EN ENTRAR, PRIMERO EN SALIR). LA INVENCION COMPRENDE ASIMISMO UN DISPOSITIVO PARA EJECUTAR DICHO SISTEMA QUE CONSISTE EN UNA RAM DE PUERTA UNICA, UNA MEMORIA FIFO, DOS CONTADORES, UNO DE LOS CUALES ES UN CONTADOR DE ESCRITURA Y EL OTRO ES UN CONTADOR DE LECTURA, UN MULTIPLEXOR (MUX) QUE SELECCIONA UNO DE LOS DOS CONTADORES, UNA LOGICA DE CONTROL DE ACCESO RAM QUE GENERA LAS SEÑALES DE CONTROL RAM Y LAS SEÑALES DE ACTIVACION DE LOS CONTADORES Y LA SEÑAL DE SELECCION DEL MULTIPLEXOR ANTES MENCIONADO.
ES8702736A 1986-09-25 1987-09-24 Sistema para interconectar equipos asincronos por medio de memorias. Expired ES2008232A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT21810/86A IT1197273B (it) 1986-09-25 1986-09-25 Sistema e dispositivi per interfacciare macchine asincrone tra loro

Publications (1)

Publication Number Publication Date
ES2008232A6 true ES2008232A6 (es) 1989-07-16

Family

ID=11187167

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8702736A Expired ES2008232A6 (es) 1986-09-25 1987-09-24 Sistema para interconectar equipos asincronos por medio de memorias.

Country Status (5)

Country Link
US (1) US4899352A (es)
ES (1) ES2008232A6 (es)
GB (1) GB2196765B (es)
IT (1) IT1197273B (es)
NO (1) NO174985C (es)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179692A (en) * 1985-08-07 1993-01-12 Seiko Epson Corporation Emulation device for driving a LCD with signals formatted for a CRT display
GB2217056A (en) * 1988-03-23 1989-10-18 Benchmark Technologies Double buffering in multi-processor
US5052025A (en) * 1990-08-24 1991-09-24 At&T Bell Laboratories Synchronous digital signal to asynchronous digital signal desynchronizer
US6189077B1 (en) * 1994-12-15 2001-02-13 Texas Instruments Incorporated Two computer access circuit using address translation into common register file
KR960035283A (ko) * 1995-03-23 1996-10-24 김주용 이중 채널 선입 선출 회로
US6377071B1 (en) * 2000-03-31 2002-04-23 Cypress Semiconductor Corp. Composite flag generation for DDR FIFOs
US6434674B1 (en) * 2000-04-04 2002-08-13 Advanced Digital Information Corporation Multiport memory architecture with direct data flow
US7738496B1 (en) 2002-12-31 2010-06-15 Cypress Semiconductor Corporation Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains
US7934057B1 (en) * 2003-12-24 2011-04-26 Cypress Semiconductor Corporation Logic for implementing a dual clock domain read access with predictable timing for bi-directional inputs/outputs
US7752355B2 (en) * 2004-04-27 2010-07-06 International Business Machines Corporation Asynchronous packet based dual port link list header and data credit management structure
US20060075184A1 (en) * 2004-10-01 2006-04-06 Jen-Ying Chen Synchronous\asynchronous memory device with single port memory unit
US8589632B1 (en) 2007-03-09 2013-11-19 Cypress Semiconductor Corporation Arbitration method for programmable multiple clock domain bi-directional interface
US8145809B1 (en) 2007-03-09 2012-03-27 Cypress Semiconductor Corporation Busy detection logic for asynchronous communication port
CN102866874B (zh) * 2012-08-29 2014-12-24 哈尔滨工业大学 通用异步fifo模块存储方法
US10891071B2 (en) * 2018-05-15 2021-01-12 Nxp Usa, Inc. Hardware, software and algorithm to precisely predict performance of SoC when a processor and other masters access single-port memory simultaneously

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3895357A (en) * 1973-02-23 1975-07-15 Ibm Buffer memory arrangement for a digital television display system
US4048625A (en) * 1976-05-05 1977-09-13 General Electric Company Buffered print control system using fifo memory
US4271483A (en) * 1977-08-04 1981-06-02 Independent Broadcasting Authority Delay circuits
US4333143A (en) * 1979-11-19 1982-06-01 Texas Instruments Input process sequence controller
US4327411A (en) * 1980-03-04 1982-04-27 Bell Telephone Laboratories, Incorporated High capacity elastic store having continuously variable delay
US4348754A (en) * 1980-05-15 1982-09-07 Ampex Corporation Digital delay for high quality audio use
GB2084361B (en) * 1980-09-19 1984-11-21 Sony Corp Random access memory arrangements
CA1169976A (en) * 1980-10-27 1984-06-26 Bernard L. Reagan, Jr. Interface memory system and method for writing into and reading from a large serial memory
US4429386A (en) * 1981-01-05 1984-01-31 Siemens Corporation Buffer arrangement of a PCM exchange system
US4661966A (en) * 1985-09-17 1987-04-28 T-Bar Incorporated Method and apparatus for adjusting transmission rates in data channels for use in switching systems
NL8601437A (nl) * 1986-06-04 1988-01-04 Philips Nv Sequentiele bufferinrichting.

Also Published As

Publication number Publication date
IT8621810A0 (it) 1986-09-25
NO174985B (no) 1994-05-02
IT1197273B (it) 1988-11-30
GB2196765A (en) 1988-05-05
IT8621810A1 (it) 1988-03-25
NO873965D0 (no) 1987-09-23
NO873965L (no) 1988-03-28
NO174985C (no) 1994-08-10
US4899352A (en) 1990-02-06
GB2196765B (en) 1991-04-03
GB8722559D0 (en) 1987-11-04

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20001204