CA1169976A

CA1169976A - Interface memory system and method for writing into and reading from a large serial memory

Info

Publication number: CA1169976A
Application number: CA000388373A
Authority: CA
Inventors: Bernard L. Reagan, Jr.
Original assignee: NCR Corp
Current assignee: NCR Voyix Corp
Priority date: 1980-10-27
Filing date: 1981-10-20
Publication date: 1984-06-26
Also published as: EP0062670A1; WO1982001608A1; JPS57501607A

Abstract

INTERFACE MEMORY SYSTEM AND METHOD FOR
WRITING INTO AND READING FROM A LARGE SERIAL MEMORY

Abstract of the Disclosure A buffer memory system for effecting parallel transfer of data between an eight-bit processor and a large continually recirculating serial memory includes a 1024 word by 20 bit static random access memory (RAM).
Twenty data terminals of the serial RAM are coupled by means of first bi-directional driver circuitry to cor-responding terminals of the static RAM. Three groups of the data terminals of the static RAM are sequentially multiplexed onto a data bus of the processor. Control circuitry responsive to control signals produced by the microprocessor and the serial memory includes first and second counters, outputs of which are multiplexed to the static RAM to enable the processor to write information into and read information out of the static RAM and to enable the serial memory to write information into and read information out of the static RAM.

Description

INTERFACE MEMORY SYSTEM AND METHOD FOR
W~ITING INTO AND READING FROM A LARGE SERIAL MEMORY

Background of the Invention _ield of the Invention The invention relates to computer memories, and more particularly to circuitry and methods for transfer-ring data between a parallel processor and a continuously recirculating dynamic serial memory.

Description of the Prior Art Low cost charge coupled devices (CCDs) have been utilized to implement serial memories for storing information to be outputted to and displayed on video display systems which include cathode ray tubes (CRTs) and associated scanning circuitry. CCDs are dynamic in nature and must be continually recirculated at a minimum shift rate to ensure refreshing of each memory cell to avoid loss of stored data. As is well known, the scanning circuitry for cathode ray tube display systems ordinarily continuously scans the screen area in order to provide a continuous display. Consequently, information to be displayed on the CRT screen must be serlally inputted to the scanning circuitry at a rate which is synchronized with the scanning rate. It is desirable to utilize CCD memory devices (which ~re relatively low cost memory devices) operating in syn-chronization with the scanning circuitry of a CRT dis-play system. However, it has been relatively incon-venient and expensive to implem~nt transfer of parallel formatted data from a microprocessor system to scanning circuitry associated with a serial charged coupled de-vice memory system at the required data rate.
Accordingly, it is one object of the present invention to provide a system and method for economically effecting rapid transfer of parallel formatted data into a recirculating serial memory system.
A relatively large number of bits (approximately 1.3 million bits) must be temporarily stored in order .

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to effect display of informa-tion on the cathode ray tube of a conventional video display system. It is frequently desirable to be able to print out this stored informa-tion, which also is being displayed on a CRT of the video display system. Further, it frequently is desir-able to be able to perform diagnostic operations on a serial memory utilized to store data (which subsequently is serially outputted to a cathode ray tube video dis-play system) without utilizing complex circuitry (re-ferred to as decompression circuitry) used inconjunction with interfacing a dynamic serial RAM to a parallel processor.
Accordingly, it is another object of the in-vention to provide an interface memory system and method for effecting use of a processor to control writing parallel formatted data into a recirculating serial memory and reading data in a parallel format out of the recirculating serial memory.

Summary of the Invention Briefly described, and in accordance with a first aspect of the invention, there is provided a system and method Eor loading data in parallel format into a recirculating serial memory. In this first aspect of the invention, data is loaded into a random access memory from a processor bus as locations of the random access memory are sequentially ac`dressed in response to a first counter which is indicated by write signals produced by a processor. When the random access memory is loaded, the recirculating serial memory produces a sequence of ;~ 30 strobe signals, one correspo~ding to each shifting of data in the recirculating serial memory. The processor loads a group address into a latch circuit. The strobe signal increments a second counter, a first group of outputs of which are coupled to address inputs of the random access memory and a second group of which are ,~

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compared to the group address stored in the latch circuit to produce a memory enable signal. The memory enable signal enables the random access memory to output data which has been loaded therein when the second counter is incremented to an address equal to the group address mem-ber. Data then is outputted from the random access memory and transferred to the recirculating serial memory as the second counter continues to be incremented. One bit of each word loaded into the random access memory is uti-lized as a write control bit which is used by therecirculating memory to determine whether that word is actually written into the recirculating serial memory.
This enables the processor to modify a particular word without having to re-write other words (which do not need to be modified) into the random access memory. In this first aspect of the invention, the random access memory is a static device, and the first and second counters are coupled to the address inputs of the random access memory by means of a multiplexer circuit. The system is also capable of transferred data stored in the recirculating serial memory back to the random access memory and then transferring that data from the random access memory to the processor bus. The process is referred to as a fetching operation. A first bi-directional bus driver circuit responsive to a firstdirection control signal is utilized to transfer data from the processor to the random access memory to effect the loading operation. A second bidirectional bus driver circuit responsive to a second direction control signal is used to transfer data from the random access memory to the recirculating memory to further effect the loading operation. The second bidirectional bus driver circuit also is responsive to a third direction control signal to transfer data from the recirculating serial memory to the random access memory to effect the fetching operation by the processor. The first bi-directional bus driver circuit also is responsive to a , ,, ,,; , : ~ '' ' ' :, '~, , :.

fourth direction control signal to transfer that data from the random access memory to the processor to further effect the fetching operation. The four direction control signals are loaded into a latch by the processor in order to perform the loading and fetching operations.
In this first aspect of the invention, three words outputted by the processor are sequentially routed to three corresponding groups of data terminals of the random access memory in order to load one word into the random access memory during a loading operation.
Similarly, during a fetching operation, a word is se-quentially transferred in three sections from the random access memory to the processor. In this first aspect of the invention, the system is utilized to attain high speed, efficient transferring of data from an eight bit processor system to a CCD serial memory system which interfaces with a CRT display system. The described system can be utilized to fetch information displayed ~; on the CRT to allow efficient selective printing of information displayed on the CRT and also to allow efficient testing of the CCD memory.
In accordance with a second aspect of the in-vention, there is provided a system for loading data into a first memory, the system comprising in combination: a processor system, the processor system producing a write signal to effect the data loading;
direction means responsive to the processor system for producing first and second direction signals to effect the data loading; a memory system having a plurality of address inputs, and a plurality of data terminals; first means responsive to the first direction signal for performing a first transfer function transferring data , from the processor system to the data terminals in re-sponse to the write signal; second means responsive to the second direction signal for performing a second transfer function transferring data from the data termi-~`~ nals to the first memory in response to the write ~i :
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-4a-signal; first addressing means for producing a first se-quence of addresses on the address inputs in response to the write signal; and second addressing means for produc-ing a second sequence of address signals on the address inputs in response to a sequence oE synchronization sig-nals produced by the first memory.
In accordance with a third aspect of the in-vention, there is provided a system for loading data into and fetching data out of a recirculating serial memory, the system comprising in combination: a processor system, the processor system producing a write signal to effect the data loading and a r~ad signal to effect the data fetching; direction means responsive to the processor system for producing a first direction signal during the 15 data loading and a second direction signal during the data fetching; a random access memory system having a plurality of address inputs, and a plurality of data ~ terminals; first means responsive to the first direction : signal for performing a first transfer function trans-- 20 ferring data from the processor system to the data terminals in response to the write signal; second means ~ responsive to the second direction signal for performing :~ a second transfer function transferring data from the data terminals to the serial memory in response to the write signal; and first addressing means for producing a first sequence of addresses on the address inputs in ~ response to the read signal or the write signal and pro-: ~ ducing a second sequence of address signals on the address inputs in response to a sequence of synchroniza-tion signals produced by the serial memoryO
: In accordance with a fourth aspect of the in-vention, there is provided a method for loading data into a recirculating serial memory, the method comprising the , ~
steps of: (a) producing a data word on a data bus;
(b) transmitting that data word to a random access : memory; (c) incrementing a first counter to address a : location of the random access memory to effect loading of ";

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that data word into that location; (d) repeating steps (a) through (c) until the random access memory is loaded, and producing a first information indicating that the random access memory is loaded; (e) incrementing a second counter means for each shift of data in the recir-culating serial memory to produce addresses for accessing the random access memory in response -to the first infor-mation; comparing a most significant portion of those addresses with a group address produced by the processor, and producing a memory enable signal when one oE those addresses equals the group address to effect reading oE
the loaded data out of the random access memory; (f) transmitting the data read ou-t of the random access memory to the recirculating serial memory; and (g) re-peating steps (e) through (f) until all of the data loaded into the random access memory has been transmitted to address locations of the recirculating serial memory determined by the group address.

Brief Description of the Drawings ..
Fig. 1 is a block diagram of the interface ~` memory system of the present invention;
Figs. 2A and 2B, inclusive, show a detailed block diagram of additional control circuitry used with the processor system 5 in the interface memory system of Fig. l;
Figs. 3A and 3B, inclusive, show a detailedblock diagram of bidirectional bus driver circuitry 41 of the memory interface system of Fig. 1.
Figs. 4A-C, inclusive, show a detailed block diagram of screen counter 27, logic circuit 97, address counter 37 and group latch circuit 33 of interface memory system of Fig. 1.
Fig. 5 is a detailed block diagram of multi-- plexer circuitry 31 and comparator 55 of the interface memory system of Fig. 1.

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~4c-Figs. 6A-C, inclusive, show a detailed block diagram of static random access memory (~M) 11 and bi-directional bus driver circuitry 19 o~ the interface memory ~ . _ : /

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Fig. 7 i5 a timing diagram useful in describing the operation of interface memory system of Fig~ l; and Fig. 8 is a diagram showing the manner in which Figs. 2A-B, Figs. 3A-B, Figs. 4A-C, and Figs. 6A-C
are arranged to form the logic circuitry.

Description of the Invention Referring now to Fig. 1, reference number 1 designates a video display system including a cathode ray tube (CRT) display terminal 9, a charge coupled device ~CCD) serial memory system 7 (including asso-ciated control and scanning circuitry), a processor system 5 ~including a memory and control circuitry) and an interface memory system 3, also referred to as a buffer memory system or a loader memory system. Buffer memory system 3 interfaces between processor system 5 and CCD serial memory system 7 (hereinafter referred to simply as CCD memory system 7) to effect both writing of information from processor system 5 into CCD memory sys-tem 7 and reading of data stored in CCD memory system 7.
CCD memory system 7 includes a CCD memorywhich includes 65,536 (commonly known in the art as 64K) twenty bit words. The 65,536 words continually circulate in synchronization with the above-mentioned scanning circuitry~ The scanning circuitry produces scanning signals on conductor 23, which scanning signals are inputted to CRT display device 9, hereinafter referred to as CRT 9. It should be noted that the CCD memory portion of CCD memory system 7 "continuously'i recircu-lates by shifting information contained therein at aminimum frequency to avoid loss of stored information by "refreshing" each CCD cell. Processor system 5 is con-nected ~o buffer memory system 3 by means of bidirec~
tional eight bit data bus 43i which is referred to herein as the "processor bus~, and which includes con-ductors DT0-D~7. Processor system 5 produces a number of control signals, including a write control signal .

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WRTCON on conductor 47, a write data signal WRDAT on conductor 49 and a read data signal RDDAT on conductor 51. Processor system 5 also produces a signal CPLT on conductor 60. The signal CPLT is a "hand-shake" signal which notifies CCD memory system 7 that buffer memory 3 has been filled and is ready to transmit a block of data into CCD memory system 7.
CCD memory system 7 is connected to interface memory system 3 by means of a 22 hit bidirectional bus 21, hereinafter referred to as the "image data bus".
Image data lines 21 include conductors D0-D21. CCD
memory system 7 produces a data strobe signal IDSTRB on conductor 25. The IDSTRB and SYNC signals are shown in Fig. 7~ The SYNC signal on conductor 53 is produced with every occurrence of a vertical synchronization signal which is applied to cathode ray tube 9. Synch-ronization signals produced by CRT scanning circuitry are well-known to those skilled in the art, and need not be discussed further herein. The IDSTRB signal is 20 a signal which includes 512 "bursts" of 64 pulses in synchronization with the SYNC signal for each loading or unloading of a static RAM 11, subsequently described.
Data is clocked into CRT 9 from CCD memory ; system 7 at a 60 MHz. rate. The above-mentioned scanning circuitry causes the data to be outputted to CRT 9 during a scan from the top to the bottom of the CRT
screen every 16.6 milliseconds. During the 16.6 milli-seconds, the even numbered lines on CRT 9 are scanned.
During the following 16.6 millisecond interval, the odd numbered lines of the CRT screen are scanned. Pro-cessor system 5 produces a FRAME 0 signal (shown in Fig. 7) which is applied to conductor 102 in Figs. 1 and 5. The FR~ME 0 signal is at a logical "zero" during scanning o~ the even numbered lines of CRT 9 and is at a logical "one" during scanning of the odd numbered lines of CRT 9. (The time required for the CRT beam to move from the bottom of the CRT screen to the top of the CRT
screen to make another pass is referred to as the ~ J~'^`
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"vertical blank time".) During the hori~ontal scanning of the CRT
screen, the CCD memory portion of CC~ memory system 7 is clocked (i.e., undergoes a data shift) 64 times/
followed by a horizontal blanking interval of approxi-mately 9 microseconds; this is repeated during scanning of the 512 even lines and the 512 odd lines of CRT 9.
During each horizontal blanking interval, one pulse of the SYNC signal appears on conductor 53. Each time the data in CCD memory undergoes a shift, another pulse of IDSTRB appears on conductor 25. Therefore, 512 '~bursts"
of IDSTRB pulses occur af~er each S~NC pulse, as indi-cated in the timing diagram in Fig. 7.
There are 64 twenty bit words of information displayed on each horizontal scan line of CRT 9. Static RAM ll contains 1024 (commonly known in the art as lK) twenty bit words. This is the amount of information which can be displayed on 16 lines of the CRT 9, and represents l/64 of the total amount of data which can be displayed on the entire screen of CRT 9.
Referring still to Fig. l, the 1024 words of static RAM 11 are addressed by means of lO address inputs MA0-MA9 transmitted via address bus 13 from a ~multiplexer circuit ~MUX) 31. Twenty-two data terminals ;25 of static RAM ll are connected to a 22 bit bidirectional data bus 15, (hereina~ter referred to as the "memory data bus"). Twen$y two conductors included in memory data bus 15 are designated ID0-ID21. (It should be noted that in the described embodiment of the invention, 30 conductors ID20 and ID21 (Fig. 6C) are no$ used). The 22 conductors of bidirec~ional data bus 1~ are connected to corresponding ones of a first group of input/output terminals of bidirec~ional bus driver circuitry l~, (hereinafter referred to simply as bus driver circuitry).
A signal WD' is produced on another data terminal of static RAM 11, w~ich data terminal is connected to conductor 57. Conductor 57 is connected ~o bidirectional bus driver circuitry l9.

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~ us driver circuitry 19 includes a second group of input/output terminals connected to image data bus conductors D0-D21, which are connected to CCD serial memory system 7 for transferring 20-bit data words between CCD memory system 7 and bidirectional bus driver circuitry 19. A signal WD (corresponding to WDI) is transmitted from bidirectional bus driver circuitry 19 ~o CCD memory system 7 on conductor 57'.
Bidirectional bus driver circuitry 41 (herein-after referred to simply as "bus driver circuitry 41") includes first and second groups vf input/output ter-minals~ The conductors of memory data bus 15 are respectively connected to corresponding ones of the first group of input/output terminals of bus driver circuitry 41. As subsequently explained with reference to Fig. 3A, there are three separately packaged groups of individual bus driver circuits contained in bus driver circuitry 41; the three groups are sequentially enabled in response to three control signals CSl, CS2, and CS-3. Only four bits of the third eight bit word contain video data; a fifth bit contains a write control bit to determine the level of the WD' and WD signals.
The three remaining bits of the third eight bit word are blank. Also, when data is read from static RAM 11 by processor system 5, the three sections or bytes of the 20 bit words outputted onto memory data bus 43 are sequentially routed via the above mentioned three groups of bus drivers to conductors DT0-DT7 in response to CSl, CS2 and CS3.
-~ 30 The three control signals CSl, CS2 and CS3 are also inputted to static RAM 11 to enable three corres-ponding 1024 word by eight bit sections of static RAM 11 to receive the above mentioned eight bi~ words multi-plexed via bus driver circuitry 41 from processor system 5 to static RAM 11, as subsequently explained.
six of the conductors of processor bus 43, which conductors are designated by reference numeral 43' ' .

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in Eig. 1, are connected to inputs of a six bit latch circuit 33, (hereinafter referred to as "group latch"
33). The outputs of group latch 33 are connected by bus 34 to inputs of comparator circuitry 55; the conductors of bus 34 are designated C10-C15. Interface memory system 3 includes a screen counter 27, which is a 16 bit counter. Screen counter 27 is reset by the SYNC
signal on conductor 53 from CCD memory system 7 and is incremented by the IDSTR~ signal on conductor 25 from CCD memory system 7. The outputs of screen counter 27 are connected to a bus 29, which includes conductors I0-I15. Conductors I0-I8 of bus 29 are connected to a first group of inputs of a multiplex~r circuit 31.
Conductors I9-I14 are connected to respective ones of a first set of inputs of comparator 55. Respective ones of a second set of inputs of comparator 55 are connected to conductors C10-C15 of bus 34 (which is connected to outputs of group latch 33)O
An address counter 37 produces a ten bit address on bus 39, which includes conductors C0-C9.
Conductors C0-C9 are connected to a second group of inputs of multiplexer 31. Address counter 37, which is required to address 1024 word static RAM 11, is in-cremented by the AUTOINC signal, which is shown on con-ductor 104 in Fig. 4B by one-shot ~ircuit 97.
The above-mentioned 10 bits outputted onto conductors I0-I8 by screen counter 27 along with the ` FRAME 0 signal enable the CCD memory sys-tem 7 to "ad-: dress" static memory 11, and the 10 bits C0-C9 outputted by address counter 37 enable processor system 5 to "ad-dress" static RAM 11. Therefore, depending upon the ~: type of operation being executed, processor system 5 either addresses static RAM 11 to write new information , ~ into it or read information out of it (a "processor bus -~:: 35 operation") or processor system 5 signals CCD memory system 7 to produce the IDSTRB signal, which causes screen counter 27 to be incremented while other control .
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signals cause static RAM 11 to be accessed at the ad-dresses produced on conductors I0-I8 of bus 29. This causes information stored in static RAM 11 to be trans-ferred to CCD memory system 7 or causes information stored in CCD memory system 7 to be written into static RAM 11 (the latter two operations being referred to as "image bus operations").
sefore explaining in detail the operation of video display system 1, it may be helpful to describe in detail an actual implementation of the interface memory system 3 of Fig. 1.
Figs. 2A-B, 3A-B, 4A-C, 5, and 6A-C in com~
bination constitute a detailed block diagram of the interface memory system 3 shown in Fig. 1. Static RAM
11 and bidirectional bus driver circuitry 19 are shown ; in Figs. 6A-C. Static RAM 11 is implemented by means of six Intel 2114-2 static random access memory integrated circuits, each of which are organized as 1024 words by four bits. In Figs. 6A C, the six static random access memory integrated circuits are designated by re~erence numerals 11A, llB, llC, llD, llE and llF. Integrated circuit random access memory (RAM) devices 11A and llB
; are selected by means of the previously mentioned CSl signal applied to conductor 61A. Similarly, integrated circult RAM devices llC and llD are selected in response to CS2 on conductor 61B, and integrated circuits RAM
devices llE and llF are selected in response to CS3 on conductor 61C.
The 24 outputs of RAM devices 11A-11F are connected, respectively, to corresponding ones of con-ductors IDO-ID21 Of memory bus 15. One of the unused data outputs of integrated circuit RAM device 11F is utilized to conduct the previously mentioned WD' signal.
BUS driver circuitry 19 includes three inte-grated circuit bidirectional three state driver devicesdesignated in Figs. 6A-C by reference numerals 19A, 19B
and l9C. Devices l9A, 19B and l9C are implemented by , . ..

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means of Texas Instrurnents 7~LS245 Universal Bidirectional Bus Driver Integrated Circuits. (It should be no-ted that in the drawings, certain lead numbers of the inte-grated circuits identified herein by a manufacturer's part number are indicated, in order -to make it completely clear how such integrated circuits are interconnected.
However, manufacturer's part numbers and lead numbers have been omi-tted herein for conventional logic gates shown in the drawings).
The memory data bus terminals ID0-ID21 are connected, respectively, to individual ones of a first group of bidirectional data terminals of bus driver integrated circuits l9A, 19B and l9C as shown in Figs.
6A-C. Each of a second group of bidirectional data terminals of hus driver integrated circuits l9A, l9B and l9C are connected, respectively, to image data bus con-ductors D0-D21. The direction of transfer of informa-tion in bus driver circuits l9A-19C is determined by the read image data bus signal RDIDB produced on conductor 63. Conductor 63 is conducted to lead No. 1 of each of integrated circuit bus drivers l9A, l9B and l9C.
Each of the integrated bus dri~er circuits l9A, l9B and l9C has a three state output driver connected, respectively, to each of the data terminals of that integrated circuit. The output drivers can be caused to assume a high impedance state by means of a signal applied to leads 19 of the respective bus driver cir-cuits l9A, 19B and l9C. Lead 19 of each of bus driver circuits l9A-19C is connected to conductor 65. Conduc-tolr 65 is connected to the output of a~ AN~ gate 67,which has its inputs connected, respectively, to a con-ductor to which a "read image data bus" signal RDIDB
is applied and to a conductor to which a "write image data bus" signal WRIDB is applied. Since negative logic signals are applied to the inputs of AND gate 67, AND
gate 67 performs a "logical ORing" function, so that a read image data bus command or a write image data bus .
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otherwise, the bus driver circuits contained in block 19 (Fig. 1) assume high output impedance configurations.
The WD (write data) signal on conductor 57' is produced by logically ANDing the write image data bus signal WRIDB and the ENAB signal with the WD' signal via gates 63A, 63B and 63C, as shown in Fig. 6C. The purpose of the WD signal is to allow transfer of all information s-tored in static RAM 11 to be transmitted via image data bus 21 to CCD memory system 7 while only allowing a portion of that data to actually be written into CCD serial memory system 7. (This capability allows a check verification system in which the video display system 1 is utilized to obtain an image of a signature on a check to be verified by means of a video camera and display the image on the CRT screen adjacent to an authorized signature previously retrieved from a computer memory and displayed on the screen without rewriting the signature data into the CCD memory).
The static memory address inputs MAO-MA9 shown in Figs. 6A-C are connected, respectively, to leads AO-A9 of each of memory integrated circuits llA-llF.
Lead 10 of each of integrated RAM circuits llA-llF is a write input terminal of that RAM circuit.
The write signal applied thereto is produced by a logic circuit including NAND gate 69A, AND gates 69B and 69C
and AND gate 69D.
A detailed block diagram of the bus driver circuitry 91 of Fig. 1 is shown in Figs. 3A and 3B.
The bus driver circuitry 41 is implemented by means of three 74LS245 integrated circuits designated by reference numerals 41A, 41B and 41C in Fig. 3A. Each of a first group of input/output terminals of each of bus driver cir~uits 41A-41C is respectively connected to certain ones of conductors DTO-DT7 of processor data bus 43.
More speci~ically, DTO is connected to the Al terminal . . ~ - .
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Similarly, DTl is connected to the A2 terminal of :~ /

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each of bu~ driver circuits 41A-C, etc.
A second group of input/output terminals of bus driver circuit 41A are connected, respectively, to conductors IDO-ID7 of memory data bus 15; each of a corresponding group of input/output terminals of bus driver circuit 41B is connected, respectively, to con-ductors ID8-ID15 of memory data bus 15; and each of a corresponding group of input/output terminals of bus driver circuit 41C is connected, respèctively, to con-ductors ID16-ID23 of memory data bus 15.
A signal RDCCB applied to conductor 71 in Fig. 3~ controls the direction of data transfer for bi-directional bus driver circuits 41A-41C, and causes data to be transferred from processor data bus 43 to static RAM 11 if RDCCB is at a logical "one" and causes the direction of data transfer to be in the opposite direc-tion if RDCCB is at logical "zero".
Driver 41A is enabled by signal CSl via gates 42A, 42B, 42C, and 42D; driver 41B is enabled by signal 20 CS2 via gates 42E, 42F, 42G, and 42H; driver 41C is enabled by signal CS3 via gates 42J, 42K, 42L9 and 42M.
The logic circuitry connected to lead 19 of each of bi-directional bus driver circuits 4iA-41C causes all of - the inputjoutput terminals o each of bus driver circuit 25 41A 41C to assume a high impedance state via gates 44A
and 44B if either a "read image data bus" (RDIDB~ or a "write image data bus" (WRIDB) operation occursl or via gate 44C if either a read data (RDDAT) operation or a write~data (WRDAT) operation occurs.
Group latch circui$ 33 of Fig. 1 can be imple-mented by means of a Texas Instruments LS174 six bit integrated circuit latch, designated by reference numeral 33 in FigO 4C.
Screen counter 27 of Fig. 1 can be implemented 35 by means of four Texas Instruments 74LS161 inte~rated circuit counters, designated by reference numerals 27A, 27B, 27C and 27D in Fig. 4B, Each of counters 27A-27D
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is reset by a signal SYNC, which is the logical comple-ment of the SYNC signal produced on conductor 53 in Fig. 1. The clock inputs of each of counter circuits 27A-27D are connected to conductor 73. The clock (CLK) input of each of counter circuits 27A-27B receives a clock signal produced in response to IDSTRB via gates 20A, 20B, and 20C (Fig. 4A).
The outputs of counters 27A-27D are connected, respectively, to conductors I0-I15 of bus 29. Conduc-tors I0-I8 along with the FRAME 0 signal are connected to inputs of multiplexer circuitry 31, which can be implemented by means of Texas Instruments 74LS157 Quad

2-to-1 line multiplexer (MUX) integrated circuits 31A, 31B and 31C, as shown in Fig. 5. The multiplexer se-lection is controlled by signals RDIDB and WRIDB via a NAND gate 31D. The signal FRAME 0 is applied to multi-plexer circuit 31B via gates 102A and 102B. Conductors I9~I14 are connected to respective ones of a first group of comparison inputs of comparators 55A and 55B of Fig.
5. Comparators 55A and 55B can be implemented by means of Texas Instruments LS 85 four bit comparator inte-grated circuits, as shown in Fig. 5.
Each of a second group of comparison inputs of comparator circuits 55A and 55B is connected to a res-pective one of outputs C10-C15 of group latch 33 (pre-viously described with reference to Fig. 3A~.
Address counter 37 of Fig. 1 is implernented by means of three integrated circuit counter circuits designated by reference numeral 37A, 37B and 37C (Fig.
4C) which counter circuits can be implemented by means of Texas Instruments LS161 four bit synchronous counters with synchronous clear inputs. The outputs labeled C0-C9 of address counter circuits 37A-37C are connected .
to corresponding inputs of multiplexer circuits 31A-31C
of Fig. 5. The write control signal WRTCON on conduc-tor 47' clears address counters 37A-C. Address counters 37A-C are incremented in response to the occurrence of either a WRDAT pulse or a RDDAT pulse produced by pro-:
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cessor system 5, which WRDAT and RDDAT pulses produce the AUTOINC signal previously mentioned.
Referring now to Figs. 2A and 2B, control circuitry (not shown in -the block diagram of Fig. 1) is disclosed. Processor system 5 genera-tes additional address and control signals, including address signals A0, AL, and A2 applied to inputs A, B and C of a three-line to eight-line decoder circuit 75 implemented by means of a Texas Instruments 74LS138 integrated circuitO
The outputs of decoder circuit 75 produce a plurality of control signals, including a write control signal WRTCON on conductor 77l, a write group signal WRTGRP
on conductor 78' and a write data signal WRDAT on con-ductor 79'. The logical complements of each of the foregoing signals are produced on conductors 77, 78, and 79 as the signals are transmitted -through inverters 65, 67, and 69 respectively. The WRDAT pulses are produced once during every processor write cycle, and the RDDAT
pulses are produced once during every processor read cycle.
Other control signals produced by processor system 5 include an address valid signal AVAL, a master ; select signal MSEL and a board select signal BSEL all of ~ which are applied to inputs of a NAND gate 81. The ; 25 output of gate 81 is transmitted via an inverter 81A to inputs of two NAND gates 82A and 82B. A write signal WRT produced by processor system 5 is applied to another input of gate 82B via an inverter 83, and a POLI, signal is applied to the third input of NAND gate 82B. The output of gate 82B is applied via an inverter 84A to flip-flops 84B and 84C to produce a data valid signal ; DVALT on conductor 90. Flip-flop 84C is controlled by a processor signal COMPR and a reset signal RES via gates 93A and 93B. A data valid signal DVAL and the WRT signal are also applied to inputs of gate 82A. The output of gate 82A is applied to flip-flops 58A and 58B to produce ;~; the signals COMPT and COMPT at the outputs of flip-flop ~ ~ 58B, assuming the processor system is not "busy".
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A second three-line to eight-line decoder cir-cult 85 receives address inputs A0, Al, and A2, and pro-duces a control signal RDSTAT on conductor 86 and a control signal RDDAT on conductor 87 in response to A0, Al, and A2 and several of the above-mentioned control signals produced by processor system 5.
An eight bit octal three state latch imple-mented by means of a Texas Instruments 74LS374 and designated by reference numeral 89 in Fig. 2B has its eight inputs connected to conductors DT0-DT7 of proces-sor data bus 43. Latch 89 stores memory commands loaded therein by processor system 5, four of the outputs of latch 89 being connected to conductors, 89', 90', 91', and 92'. A "read processor bus" signal RDCCB
is produced on conductor 89'. A "write processor data bus" signal WRCCB is produced on conductor 90'. Th~
previously mentioned "read image data bus" signal RDIDB
is produced on conductor 91'. The previously mentioned "write image data bus" signal WRIDB is produced on con-ductor 92'. The complements of these memory commands are generaked by transmitting the WRIDB signal to an inverter 92A, the RDIDB signal to an inverter 91A, trans-mitting the WRCCB signal to an inverter 90A, and trans-~; mitting the RDCCB signal to an inverter 89A.
The operation of the above-described interface system will be best understood if the main control signals and the four above-mentioned memory commands are understood. The MSEL signal applied to AND gate 81 of Fig. 2A indicates that processor system 5 has access to processor bus 43. The WRT signal applied to gate 82A
of Fig. 2A is a command which is utilized to generate the WRTCON signal on conductor 77~ WRTCON is utilized to clock latch 89 of Fig. 2B to load four basic direction signals RDCCB, WRCCB, RDIDB, and WRIDB. WRTCON is utilized in Figs. 4A and B to initialize the sequencing circuitry which produces CSl, CS2 and CS3. In Figs. 4A
and B,~ the three D-type flip-flops 96A, 96B and 96C and associated logic gates 93A and 93B cooperate to produce ~, : ~

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a serial counter which is incremented via gate 96D in response to a WRDAT (write data) or a RDDAT (read data) signal produced by processor system 5. The outputs of the three D-type flip-flops 96A, 96B and 96C are applied to the inputs of three gates 95A, 95B, and 95C (which are enabled via flip flop 99A and gate 99B) by means of a multiplexer (MUX) circuit 101. Multiplexer circuit 101 can be implemented by means of a Texas Instruments 74LS157 2-to 1 line multiplexer integrated circuit.
Multiplexer circuit 101 is enabled if a "processor bus operation" is being performed, i.e., if both RDIDB and WRIDB equals logic "one" via gate 95D. Loglc circuit 97, which can be implemented by means of a Fairchild 9602 "one-shot" flip-flop, produces a clock signal designated AUTOINC on conductor 104. The signal AUTOINC is utilized to clock address counters 37A-C (Fig. 4C) once in response to each RDDAT or WRDAT pulse produced by processor system 5.
The above-mentioned four direction signals produced by processor system 5 cause interface memory system 3 to perform the following functions. The RDCCB
signal causes bus driver circuitry 41 to transfer data on processor bus 43 (Fig. 3A) to memory data bus 15 in three consecutive bytes, whereby they are written into static RAM 11. The RDCCB direction signal causes bus driver circuitry 41 to transfer 20 bits of data from memory data bus 15 in three consecutive bytes onto processor bus 43. Execution of the WRCCB and RDCCB
commands are referred herein to as "processor bus opera-~ 3Q tions?'. The WRIDB direction signal causes bus driver ;~ circuitry 19 to transfer data on memory data bus 15 to image data bus 21 (Fig. 6A). These -twenty bits of data then are written into twenty bits of CCD memory system 7 in response to the IDSTRB signal. The RDIDB signal causes bus driver circuitry 19 to transfer data outputted by CCD memory system 7 onto image data bus 21 via bus driver circuitry 19 to memory data bus 15 (Fig. 6A) ~` whereby that data is written into static RAM 11.

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The basic operation of the system shown in the block diagram of Fig. 1 is as follow~. Firstr a six bit "group number" is written into group latch 33 from processor system 5. The above described control signals (WRTCON, R3:CCB, WRTGRP, WRDAT and RDDAT) are then pro-duced by processor system 5 to cause data to be trans mitted from processor system 5 to bidirectional bus driver 41. Three thousand seventy two ~3072~ eight bit bytes then are transmitted from processor system 5 on conductors DT0-DT7 of bidirectional processor bus 43 to bus driver 41. Each group of three bytes of data form a single 20-bit word, only four bits of the third byte of each group being utiliæed as data, the fifth bit of the third byte,containing information used to generate the WD' and WD signals as seen from Fig. 6C. The CSl signal causes the first byte to be loaded into the first 8 bits of the location of static RAM 11 addressed by address . counter 37. The second byte o~ each three byte group is - conducted from bidirectional bus driver circuitry 41 onto the next eight bits of bidirectional memory bus 15 by means of CS2. Similarly, the third byte of each three byte group is routed to 1024 word by eight bit integrated circuit memory devices llE and llF of skatic RAM 11 in response to CS3.
CCD memory system 7 contains 65,536 20-bit words. Therefore, 16 bits are required to address each word in CCD serial memory system 7, ten of which are produced by address counter 37 to address static RAM 11 as subsequently explained, the other six bits required to address CCD memory system 7 includes outputs C10-C15 of group latch 33. Outputs CO-C9 of address counter 37 of Fig. 1 are used to generate memory address inputs MA0-MA9.
After static RAM 11 is completely loaded by 1024 twenty bit words in the manner described above, ~ the situation is that the CCD serial memory system 7 is simply recirculating at its usual rate~ In response to the CPLT signal produced on conductor 60 by processor

3 9 ~ ~j system 5, the CCD s~rial memory system outputs the SYNC
signal on conductor 53 at the beginning of every vertical retrace signal, as previQusly described. After each SYNC pulse, 51~ IDSTRB pulses are produced on conductor 25, as indicated in Fig. 5. -In response to the IDSTRB
pulses, screen counter 27 produces sequential addresses on conductors I0-I15 to address static RAM 11 and to transfer data from static RAM 11 to CCD serial memory system 7. In order to accomplish this, bits I0-I8 along with the F~AME 0 signal are inputted to multiplexers 31A-C-in ~rder~t-o produce---the--address--inputs-MA0-MA9--f-or~
static RAM 11 and bits I10-I15 are compared by compara-tors 55 A and B with the contents of group latch 33.
The memory enable signal ENAB is produced, causing 15 --static RAM~ll to output---data--at---the-addr-ess-corresponding--to the group number stored in group latch 33 when bits I9-I15 match the group number. This sequence continues 32 times, until all of the 1024 twenty bit words stored in static RAM 11 have been loaded into CCD memory system 7, which includes latch circuitry which temporarily "snaps-up" the twenty bit words.
It should be understood that data stored in CCD memory system 7 is broken up into 64 groups. The group number stored in group latch 33 represents one of these 64 groups. Thus, during execution of the above ~; described operations, the group latch number dete~mines which of the 64 groups is involved. Processor system 5 determines the group by loading the six bit group number in~o group latch 33 by means of the WRTGRP signal gener-ated on conductor 78 in Fig. 2A (as a result of decoding instruction commands produced on address conductors A0, Al and A~ o processor system S).
The WD signal generated in response to the "WD
~; information bit" of static RAM 11 (by means of the cir-cuitry shown at the top of Fig. 6C) enables processor system 5 to write new information into a selected twenty bit word in the CCD serial memory system 7. This capa-..
--~ bility is necessary, since it is not always desired ~o 1 3 6 ~'3 ~ '7 ~i replace an entire stored block of data (1024 words by twenty bits) during a par~icular interface memory reading or writing operation. Interface memory system 3 always transmits 1024 twenty bit words to CCD serial memory system 7 during an interface memory write operation, and utilizes the WD signal to control how much of that in-formation actually ge~s written into the CCD memory system 7~
In order to transfer information stored in CCD memory system 7 to processor system 5, a set of operations which are essentially the reverse of the foregoing set of operations are performed. Processor system 5 sets up the above-described control signals to transfer data outputted onto conductors D0-D~l of image data bus 21 as the CCD memory circulates. Processor system 5 causes the group number of the selected group of 1024 twen~y bit words stored in CCD memory system 7 to be written into group latch 33. The SYNC and IDSTRB
pulses cause screen counter 27 to stay in synchronization with the circulating data in CCD memory system 7, and when the first twenty bit word of the selected group appears on image data bus 21, the resulting match be~
tween I9-I15 and the outputs C10-C15 of group latch 33 enables static memory 11 to begin receiving the selected 1024 word groups. When ~he entire selected group has been written into static RAM 11~ ~he CCD memory system sends a handshake siynal CPLT to processor system 5, causing multiplexer 31 to switch address inputs MA0-MA9 of static RAM 11 from bus 29 to bus 39, and address counter 37 is then incremen~ed in response to RDDAT
signals from processor system 5 to effect outputting successive twenty bit words of the selected group of data from static ~AM 11 onto memory data bus 15. Each such twenty bit word is transferred, one byte at a time, to processor bus 43 in response to CSl, CS2 and CS3.
While the inventive system and method have been described with reference to a particular embodiment ' : . " , , 9 7 ~
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thereof r those skilled in the art will be able to make various modifica~ions to the described systems and method without departing from the true scope and spirit of the invention, as set forth in the appended claims.

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Claims

CLAIMS:

1. A system for loading data into a first memory, said system comprising in combination:
a processor system, said processor system producing a write signal to effect said loading;
direction means responsive to said pro-cessor system for producing first and second direction signals to effect said loading;
a memory system having a plurality of address inputs, and a plurality of data terminals;
first means responsive to said first direction signal for performing a first transfer function transferring data from said processor system to said data terminals in response to said write signal;
second means responsive to said second direction signal for performing a second transfer func-tion transferring data from said data terminals to said first memory in response to said write signal;
first addressing means for producing a first sequence of addresses on said address inputs in response to said write signal; and second addressing means for producing a second sequence of address signals on said address inputs in response to a sequence of synchronization signals pro-duced by said first memory.

2. The system of claim 1 wherein said first addressing means includes a first counter for producing a first group of address output signals in response to said write signal and first coupling means for routing said first group of address output signals to said ad-dress inputs of said memory system.

3. The system of claim 2 wherein said memory system includes a static random access memory.

4. The system of claim 2 wherein said second addressing means includes a second counter for producing a second group of address output signals in response to said synchronization signals and second coupling means for coupling a first portion of said second group of address output signals to said address inputs of said memory system.

5. The system of claim 4 wherein said second addressing means further includes first storage means for receiving and storing a third group of address out-put signals from said processor system and comparison means coupled to said first storage means and said second counter for comparing said third group of address output signals with at least a second portion of said second group of address output signals, said comparison means producing a memory enable signal for enabling said memory system to output stored data onto said data terminals in order to effect said performing of said second transfer function by said second means.

6. The system of claim 5 wherein said first and second coupling means are included in a multiplexer circuit.

7. The system of claim 5 wherein said memory system includes a first number of words each having a second number of bits, these being said second number of said data terminals.

8. The system of claim 7 wherein said pro-.
cessor system includes a data bus being a third number of bits which is less than said second number, wherein said first means includes a first group of bidirectional bus driver circuits coupled between said data terminals and said data bus for transferring data, said third num-ber of bits at a time, between said data bus and said data terminals.

9. The system of claim 8 wherein said second means includes a second group of bidirectional bus driver circuits coupled between said data terminals and said first memory for transferring data between said memory system and said first memory.

10. The system of claim 9 wherein said first memory is capable of receiving a group of bits of data equal to said second number of bits of data each time a shifting of data occurs in said first memory.

11. The system of claim 10 wherein said first memory includes a CCD memory containing a plurality of words each including said second number of bits.

12. The system of claim 9 wherein said pro-cessor system also produces a read signal to effect fetching of data from said first memory.

13. The system of claim 12 wherein said direc-tion means also produces third and fourth direction sig-nals to effect said fetching.

14. The system of claim 13 wherein said second means is responsive to said third direction signal and performs a third transfer function transferring data from said first memory to said data terminals to effect said fetching.

150 The system of claim 14 wherein said second counter is responsive to said read signal, said comparison means producing said memory enable signal to effect writing of data from said first memory into a portion of said memory system determined by said third group of address output signals stored in said first storage means.

16. The system of claim 14 wherein said first means is responsive to said fourth direction signal and performs a fourth transfer function transferring data from said data terminals to said data bus in response to said read signal.

17. The system of claim 5 wherein said first portion of said second group of address output signals is exclusive of said second portion thereof.

18. The system of claim 16 wherein said pro-cessor system produces a first signal to said first memory when said loading is complete, said first signal causing said first memory to produce said sequence of synchronization signals.

19. The system of claim 18 wherein said first memory sends a second signal to said processor system when said memory system is filled with data from said first memory during said fetching, causing said pro-cessor system to produce a control signal to increment said first counter to effect transfer of that data from said memory system to said processor system via said first means.

20. The system of claim 7 wherein one bit of each of said words is a write control bit utilized by said first memory to determine whether or not that word is written into said first memory.

21. A system for loading da a into and fetch-ing data out of a recirculating serial memory, said system comprising in combination:
a processor system, said processor system producing a write signal to effect said loading and a read signal to effect said fetching;

21. (concluded) direction means responsive to said pro-cessor system for producing a first direction signal during said loading and a second direction signal during said fetching;
a random access memory system having a plurality of address inputs, and a plurality of data terminals;
first means responsive to said first direction signal for performing a first transfer func-tion transferring-data-from said processor system-to said data terminals in response to said write signal;
second means responsive to said second direction signal for performing a second transfer func-tion transferring data from said data terminals to said serial memory in response to said write signal; and first addressing means for producing a first sequence of addresses on said address inputs in response to said read signal or said write signal and producing a second sequence of address signals on said address inputs in response to a sequence of synchroniza-tion signals produced by said serial memory.

22. A method for loading data into a recir-culating serial memory, said method comprising the steps of:
(a) producing a data word on a data bus;
(b) transmitting that data word to a random access memory, (c) incrementing a first counter to address a location of the random access memory to effect loading of that data word into that location;
(d) repeating steps (a) through (c) until said random access memory is loaded, and producing a first information indicating that the random access memory is loaded;

22. (concluded) (e) incrementing a second counter means for each shift of data in said recirculating serial memory to produce addresses for accessing said random access memory in response to said first information;
comparing a most significant portion of those addresses with a group address produced by said processor, and producing a memory enable signal when one of those addresses equals said group address to effect reading of the loaded data out of said random access memory;
(f) transmitting the data read out of said random access memory to said recirculating serial memory, and (g) repeating steps (e) through (f) until all of said data loaded into said random access memory has been transmitted to address locations of said recirculating serial memory determined by said group address.

23. The method of claim 22 wherein step (b) is performed by means of a first bidirectional bus driver circuit in a direction determined by a first direction control signal and wherein step (f) is per-formed by means of a second bidirectional bus driver circuit in a direction determined by a second direction control signal.

24. The method of claim 23 further including the steps of fetching data from said recirculating serial memory by incrementing said second counter once for each shift of data in said recirculating serial memory to produce addresses for accessing said random access memory, comparing a most significant portion of those addresses with a group address corresponding to the locations of said recirculating serial memory in

24. (concluded) which the data to be fetched is stored, to produce said memory enable signal when a most significant portion of addresses outputted by said second counter are equal to that group address to effect writing of data from said recirculating serial memory into said random access memory and transmitting that data from said recirculating serial memory to said random access memory by means of said second bidirectional bus driver circuit in a direc-tion determined by a third direction control signal.

25. The method of claim 24 including repeat-ing the steps of claim 24 until the data desired to be fetched is loaded into said random access memory and then incrementing said first counter to effect outputting of that data from said random access memory.

26. The method of claim 25 including the step of transmitting that data to said processor by means of said first bidirectional bus driver circuit in a direc-tion determined by a fourth direction control signal.

27. The method of claim 26 wherein said first, second, third and fourth direction control signals are produced by means of said processor.

28. The method of claim 22 including the steps of using one bit of each data word transmitted from said random access memory to said recirculating serial memory to determine whether that data word is written into said recirculating serial memory.