ES2002443A6 - Un aparato para interconexion microelectronica - Google Patents

Un aparato para interconexion microelectronica

Info

Publication number
ES2002443A6
ES2002443A6 ES8603459A ES8603459A ES2002443A6 ES 2002443 A6 ES2002443 A6 ES 2002443A6 ES 8603459 A ES8603459 A ES 8603459A ES 8603459 A ES8603459 A ES 8603459A ES 2002443 A6 ES2002443 A6 ES 2002443A6
Authority
ES
Spain
Prior art keywords
chip
mesa
interface
conductive
notches
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES8603459A
Other languages
English (en)
Spanish (es)
Inventor
Nils E Patraw
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of ES2002443A6 publication Critical patent/ES2002443A6/es
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492Bases or plates or solder therefor
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    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
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    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L2224/0616Random array, i.e. array with no symmetry
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    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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    • H01L2924/30105Capacitance
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    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Die Bonding (AREA)
ES8603459A 1985-12-20 1986-12-17 Un aparato para interconexion microelectronica Expired ES2002443A6 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US81123985A 1985-12-20 1985-12-20

Publications (1)

Publication Number Publication Date
ES2002443A6 true ES2002443A6 (es) 1988-08-01

Family

ID=25205984

Family Applications (1)

Application Number Title Priority Date Filing Date
ES8603459A Expired ES2002443A6 (es) 1985-12-20 1986-12-17 Un aparato para interconexion microelectronica

Country Status (7)

Country Link
EP (1) EP0250541A1 (ja)
JP (1) JPS63502071A (ja)
KR (1) KR900004719B1 (ja)
ES (1) ES2002443A6 (ja)
IL (1) IL80683A0 (ja)
TR (1) TR22838A (ja)
WO (1) WO1987004010A1 (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3923533A1 (de) * 1989-07-15 1991-01-24 Diehl Gmbh & Co Anordnung eines integrierten schaltkreises auf einem schaltungstraeger
US5504035A (en) * 1989-08-28 1996-04-02 Lsi Logic Corporation Process for solder ball interconnecting a semiconductor device to a substrate using a noble metal foil embedded interposer substrate
US5489804A (en) * 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
US5299730A (en) * 1989-08-28 1994-04-05 Lsi Logic Corporation Method and apparatus for isolation of flux materials in flip-chip manufacturing
US5834799A (en) * 1989-08-28 1998-11-10 Lsi Logic Optically transmissive preformed planar structures
US5770889A (en) * 1995-12-29 1998-06-23 Lsi Logic Corporation Systems having advanced pre-formed planar structures

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1258660A (ja) * 1969-12-19 1971-12-30
JPS58151B2 (ja) * 1978-09-14 1983-01-05 宮川化成工業株式会社 蓄電池の端子導出部の製造方法
US4352449A (en) * 1979-12-26 1982-10-05 Bell Telephone Laboratories, Incorporated Fabrication of circuit packages
US4549247A (en) * 1980-11-21 1985-10-22 Gao Gesellschaft Fur Automation Und Organisation Mbh Carrier element for IC-modules
GB2144907A (en) * 1983-08-09 1985-03-13 Standard Telephones Cables Ltd Mounting integrated circuit devices
KR900001273B1 (ko) * 1983-12-23 1990-03-05 후지쑤 가부시끼가이샤 반도체 집적회로 장치

Also Published As

Publication number Publication date
EP0250541A1 (en) 1988-01-07
IL80683A0 (en) 1987-02-27
TR22838A (tr) 1988-08-22
JPS63502071A (ja) 1988-08-11
WO1987004010A1 (en) 1987-07-02
KR880701020A (ko) 1988-04-13
KR900004719B1 (ko) 1990-07-05

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FD1A Patent lapsed

Effective date: 20010301