EP4609430A1 - Procédé de formation d'une couche de carbure de silicium - Google Patents
Procédé de formation d'une couche de carbure de siliciumInfo
- Publication number
- EP4609430A1 EP4609430A1 EP23805643.6A EP23805643A EP4609430A1 EP 4609430 A1 EP4609430 A1 EP 4609430A1 EP 23805643 A EP23805643 A EP 23805643A EP 4609430 A1 EP4609430 A1 EP 4609430A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- silicon carbide
- carbon
- substrate
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P90/19—Preparing inhomogeneous wafers
- H10P90/1904—Preparing vertically inhomogeneous wafers
- H10P90/1906—Preparing SOI wafers
- H10P90/1914—Preparing SOI wafers using bonding
- H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N30/00—Piezoelectric or electrostrictive devices
- H10N30/01—Manufacture or treatment
- H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
- H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
- H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
- H10P14/2901—Materials
- H10P14/2902—Materials being Group IVA materials
- H10P14/2905—Silicon, silicon germanium or germanium
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
- H10P14/3202—Materials thereof
- H10P14/3204—Materials thereof being Group IVA semiconducting materials
- H10P14/3208—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3406—Carbon, e.g. diamond-like carbon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
- H10P14/3602—In-situ cleaning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/10—Isolation regions comprising dielectric materials
- H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/34—Deposited materials, e.g. layers
- H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
- H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
- H10P14/3408—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
- H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
- H10P14/38—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done after the formation of the materials
Definitions
- the present invention relates to a method of manufacturing a semiconductor-on-insulator or piezoelectric-on-insulator type substrate for radio frequency applications.
- Radio frequency (RF) devices which process signals with frequencies between approximately 10 MHz and 300 GHz, find particular application in the field of telecommunications.
- Such devices can be formed from semiconductor-on-insulator or piezoelectric-on-insulator type substrates, successively comprising a base substrate, an electrical charge trapping layer (called a “trap rich” layer in English), a dielectric layer. disposed on the trapping layer and an active semiconductor or piezoelectric layer disposed on the dielectric layer. Active and/or passive components are formed in and/or on the active layer.
- the charge trapping layer prevents the appearance of a conductive plane under the electrically insulating layer and the drop in resistivity of the base substrate. In addition, such a layer eliminates charge carriers in the substrate that could lead to the generation of harmonics likely to interfere with the signals propagating in the radio frequency device and degrade their quality.
- the charge trapping layer may be made of silicon carbide (SiC).
- SiC silicon carbide
- the formation of such a layer is typically carried out by epitaxy on the base substrate, in order to obtain the crystalline quality necessary for effective harmonic suppression in the RF component. This step is followed by chemical mechanical polishing (CMP, acronym for the Anglo-Saxon term “Chemical Mechanical Polishing”)) in order to obtain a uniform thickness and a sufficiently smooth surface of the silicon carbide layer.
- CMP chemical mechanical polishing
- Epitaxy deposition of a sufficiently thick layer of SiC is slow and therefore expensive.
- an epitaxy enclosure receives a single substrate or a reduced number of substrates.
- An aim of the invention is to design a process for manufacturing a layer of SiC on a silicon substrate, in particular to form a substrate for radio frequency applications, which is faster and less expensive than known processes.
- the invention proposes a method for forming a respective layer of silicon carbide on a plurality of silicon substrates, said method successively comprising:
- the carbon gas is propane or acetylene.
- the carbon gas is mixed with argon or a mixture of argon and hydrogen.
- the formation temperature of the silicon carbide layer is between 750°C and 1100°C.
- the removal temperature of the carbon layer is between 600°C and 950°C.
- the silicon substrate has an electrical resistivity greater than 500 Ohm. cm.
- the thickness of the silicon carbide layer is between 2 and 5 nm.
- the process further comprises, before the introduction of the carbon gas flow:
- the formation of the silicon carbide layer and the removal of the carbon layer are carried out in the same oven.
- the removal of the carbon layer is accomplished by introducing a flow of oxygen into the furnace and reacting the carbon layer with said flow of oxygen.
- the removal of the carbon layer is carried out by an oxygen plasma etching process.
- the invention also relates to a method of manufacturing a semiconductor or piezoelectric type substrate on insulator for radio frequency applications, comprising the following steps:
- Figures 1A and 1B are schematic views of a base substrate before a process according to the invention.
- Figure 2 is a schematic view of a base substrate comprising a silicon carbide layer and a carbon layer.
- Figure 3 is a schematic view of a base substrate comprising a charge trapping layer of silicon carbide
- Figure 4 shows the thermal profile used for a process according to the invention.
- Figures 5A to 5D illustrate the steps of manufacturing a semiconductor or piezoelectric type substrate on insulator.
- Figure 6 illustrates an annealing furnace suitable for forming to form a layer of silicon carbide on the base substrate and a layer of carbon on the layer of silicon carbide according to a preferred embodiment of the invention.
- Figure 1A illustrates a silicon base substrate 10 intended for the manufacture of a semiconductor-on-insulator or piezoelectric-on-insulator type substrate.
- the electrical resistivity of such a base substrate is advantageously greater than 500 Ohm. cm.
- the base substrate has a rear face 110 and a front face 130.
- the base substrate has a layer of native silicon oxide 13 on its surface.
- the native oxide layer is first removed. This step is typically carried out in an oven at a temperature between 950°C and 1150°C, preferably close to 1100°C, under an inert atmosphere.
- the substrate has a front face 120 made of silicon.
- the formation of the silicon carbide layer is carried out in an oven which will be described later.
- the removal of the native oxide layer is carried out in the same oven in order to avoid transfer steps resulting in a loss of time and energy for cooling and subsequent heating, and a need for additional labor. .
- the silicon carbide layer is formed in the gas phase, that is to say the carbon is present in the oven in the form of a carbon gas, for example propane (CsHs) or acetylene (C2H4) gaseous.
- a carbon gas for example propane (CsHs) or acetylene (C2H4) gaseous.
- the carbon gas is mixed with a carrier gas, for example argon or a mixture of argon and hydrogen.
- the substrate is heated in the oven to a temperature for forming the silicon carbide layer.
- the carbon gas phase is transformed into silicon carbide through a reaction with silicon on the substrate surface.
- the reaction is self-limited, that is to say that when all the surface silicon on the front face of the base substrate is consumed, the carbonization reaction stops. We do not provide an additional source of silicon.
- the final thickness of the silicon carbide layer 20 is between 2 and 5 nm.
- a carbon layer 30 is formed on the silicon carbide layer 20.
- the substrate has a front face 320 made of carbon.
- this removal is carried out by a supply of oxygen on the front face of the base substrate.
- the removal of the carbon layer is achieved by introducing a flow of oxygen into the furnace and reacting the carbon layer with said flow of oxygen.
- the removal of the oxygen layer is advantageously carried out in the same oven as the deposition of the silicon carbide layer. This treatment is therefore carried out in situ and does not require any cooling or transfer step to another enclosure. Removal by a flow of oxygen in the same oven makes it possible to obtain a roughness of the front face 220 that is sufficiently low for the subsequent steps to form a semiconductor or piezoelectric type substrate on insulator for radio frequency applications.
- the removal of the carbon layer is carried out by an oxygen plasma etching process.
- This removal is effective, however it requires a step of transferring the substrate to another enclosure.
- plasma treatment can degrade the roughness of the front face 220 of the base substrate, which requires subsequent treatment to improve the surface quality.
- Figure 4 illustrates an example temperature profile for a process for forming a layer of silicon carbide on a silicon substrate in an annealing furnace as a function of elapsed time. In this case, all steps from the removal of the native oxide layer to the removal of the carbon layer are carried out in the same oven.
- the first step E1 begins at a time tO.
- the base substrate comprising a layer of native oxide is at an introduction temperature into the oven which is typically less than or equal to 500°C.
- the substrate is introduced into the oven.
- This heating can, in an illustrative and non-limiting manner, include temperature rises of 5°C/min up to 900°C, then of 2°C/min up to 1000°C, and of 1°C/min up to 1100°C.
- the native oxide withdrawal temperature TO is reached.
- the native oxide removal temperature To is between 1000°C and 1200°C, preferably close to 1100°C. This temperature is maintained during step E2 which typically lasts around 20 minutes until t2. The duration of this step E2 can vary depending on the thickness of the native oxide layer.
- Cooling is then carried out during step E3 to a temperature Tl of injection of carbon gas into the oven at time t3.
- the Cooling can be carried out at a speed of 5°C/min and the Ti gas injection temperature is around 750°C.
- the substrate is heated in step E4 to a temperature TF for forming a layer of silicon carbide.
- the temperature TF for forming the layer of silicon carbide 30 is advantageously between 750°C and 1100°C.
- the nucleation of silicon carbide on the surface of the substrate begins during the temperature rise between t3 and t4 during step E4 and stops when the silicon on the surface of the base substrate has transformed into silicon carbide.
- the SiC formation reaction stops during the temperature rise, when all the silicon is consumed.
- a layer of carbon is formed linked to the high temperature decomposition of the carbon gas.
- the temperature TF is maintained during step E5 during which the carbon gas is evacuated from the oven under a flow of carrier gas for approximately 10 minutes. Subsequently, still at the temperature TF, the silicon carbide layer is annealed, for example for a period of 2 hours up to t5.
- Cooling E6 is then carried out to a temperature TR for removing the carbon layer.
- the temperature T is reached at time t6 and is between 600°C and 950°C. By way of illustration and not limitation, this temperature can be around 800°C.
- the withdrawal temperature TR is maintained and oxygen O2 is injected into the oven. For example, for an injection at 2 to 20 slm, the duration of removal of the carbon layer is approximately 5 min up to t7.
- the temperature to remove the substrate from the oven we then lower, in a final step E8, the temperature to remove the substrate from the oven.
- the base substrate comprising the silicon carbide charge trapping layer can now be used for the manufacture of a semiconductor or piezoelectric type substrate on insulator for radio frequency applications.
- a semiconductor or piezoelectric donor substrate 500 from which a semiconductor or piezoelectric layer will be transferred to the base substrate and the charge trapping layer.
- An electrically insulating layer 40 is formed on the surface of the donor substrate 500.
- an implantation of ionic species, such as hydrogen and/or helium, is implemented through the electrically insulating layer 40, so as to form a weakening zone 51 in the donor substrate 500.
- Said weakening zone 51 defines the semiconductor or piezoelectric layer 50 to be transferred.
- the donor substrate 500 thus implanted is glued onto the charge trapping layer 20 on base substrate 10 via the electrically insulating layer 40. The latter then becomes a buried oxide layer 40. .
- the electrically insulating layer 40 can be formed on the charge trapping layer on the base substrate, and the donor substrate 50 comprising the weakened zone 51 can be bonded to the base substrate 10 comprising the trapping layer. of charges 20 and the electrically insulating layer 40.
- the donor substrate 500 is detached along the weakening zone 51, which leads to the transfer of the semiconductor or piezoelectric layer 50 onto the support substrate 100.
- the electrically insulating layer 40 is arranged between the charge trapping layer 20 and the semiconductor or piezoelectric layer 50. It is subsequently possible to carry out a finishing treatment of the transferred layer 50, so as to cure the defects linked to the implantation and to smooth the free surface of said layer 50.
- the semiconductor or piezoelectric type structure on insulator is now completed and can be used for the manufacture of components for radio frequency applications.
- an annealing furnace capable of simultaneously treating a maximum of substrates under identical conditions is preferably used.
- Such an oven is conventionally called a “batch anneal” oven in the field of microelectronics.
- Figure 6 illustrates an oven adapted to receive a quantity of between 120 and 150 substrates in an annealing chamber.
- the substrates 10 are positioned horizontally in the oven and are superimposed vertically in order to treat a maximum of substrates in the same flow 73 of hot gas.
- a free space is maintained between each substrate 10 and the adjacent substrates 10 to optimize the gas flow and facilitate the formation of the silicon carbide layer.
- Such an oven uses a “top flow” type configuration, that is to say that a flow of gas is routed into the oven from the top 71 and, after passing through the oven, is evacuated through an outlet 79 at the top. bottom of the oven.
- a flow of gas is routed into the oven from the top 71 and, after passing through the oven, is evacuated through an outlet 79 at the top. bottom of the oven.
- one gas flow brings the carrier gas
- a second gas flow brings a carbon gas such as propane or acetylene
- All elements of the annealing chamber inside the oven, i.e. the interior walls 75, the substrate holders for holding the substrates in a horizontal position and vertically superimposed, and the gas included in the chamber annealing are at the same temperature during use of the oven, with the exception of exterior elements such as the exterior wall 76 and the ends of the gas inlet pipes.
- the temperature difference between the end 74 of the top of the oven and the end 78 of the bottom of the oven is minimal, typically a few degrees °C, for example less than 3 degrees for a temperature in the oven between 800 and 1200°C.
- the substrates are heated primarily by conduction from the oven walls.
- the gas flows are injected at the same temperature as the temperature inside the oven.
- Such an oven makes it possible to simultaneously process a large number of substrates thanks to the vertical superposition arrangement.
- such an oven makes it possible to carry out the step of removing the native oxide layer, the step of depositing the silicon carbide layer and the step of removing the carbon layer in the same chamber, which avoids a risk of contamination during transfer between two different enclosures. Transfer stages between different enclosures adapted to the respective stages are avoided, thus avoiding cooling between stages, the need for labor for the transfer and thus a loss of time and efficiency.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Drying Of Semiconductors (AREA)
- Carbon And Carbon Compounds (AREA)
Abstract
Description
Claims
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR2211212A FR3141557A1 (fr) | 2022-10-27 | 2022-10-27 | Procédé de formation d’une couche de carbure de silicium |
| PCT/FR2023/051674 WO2024089359A1 (fr) | 2022-10-27 | 2023-10-25 | Procédé de formation d'une couche de carbure de silicium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP4609430A1 true EP4609430A1 (fr) | 2025-09-03 |
Family
ID=84360091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP23805643.6A Withdrawn EP4609430A1 (fr) | 2022-10-27 | 2023-10-25 | Procédé de formation d'une couche de carbure de silicium |
Country Status (7)
| Country | Link |
|---|---|
| EP (1) | EP4609430A1 (fr) |
| JP (1) | JP2026512973A (fr) |
| KR (1) | KR20250099107A (fr) |
| CN (1) | CN119948616A (fr) |
| FR (1) | FR3141557A1 (fr) |
| TW (1) | TW202427568A (fr) |
| WO (1) | WO2024089359A1 (fr) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7024668B2 (ja) * | 2018-09-05 | 2022-02-24 | 株式会社Sumco | Soiウェーハ及びその製造方法 |
| FR3091011B1 (fr) * | 2018-12-21 | 2022-08-05 | Soitec Silicon On Insulator | Substrat de type semi-conducteur sur isolant pour des applications radiofréquences |
| FR3104322B1 (fr) * | 2019-12-05 | 2023-02-24 | Soitec Silicon On Insulator | Procédé de formation d'un substrat de manipulation pour une structure composite ciblant des applications rf |
-
2022
- 2022-10-27 FR FR2211212A patent/FR3141557A1/fr active Pending
-
2023
- 2023-10-25 EP EP23805643.6A patent/EP4609430A1/fr not_active Withdrawn
- 2023-10-25 JP JP2025524333A patent/JP2026512973A/ja active Pending
- 2023-10-25 WO PCT/FR2023/051674 patent/WO2024089359A1/fr not_active Ceased
- 2023-10-25 CN CN202380069331.8A patent/CN119948616A/zh active Pending
- 2023-10-25 KR KR1020257009760A patent/KR20250099107A/ko active Pending
- 2023-10-26 TW TW112141010A patent/TW202427568A/zh unknown
Also Published As
| Publication number | Publication date |
|---|---|
| WO2024089359A1 (fr) | 2024-05-02 |
| TW202427568A (zh) | 2024-07-01 |
| FR3141557A1 (fr) | 2024-05-03 |
| CN119948616A (zh) | 2025-05-06 |
| JP2026512973A (ja) | 2026-04-22 |
| KR20250099107A (ko) | 2025-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6375738B1 (en) | Process of producing semiconductor article | |
| EP4128328B1 (fr) | Procede de fabrication d'une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic | |
| FR3103961A1 (fr) | Procede de fabrication d’une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic | |
| FR3104318A1 (fr) | Procédé de formation d'un support de manipulation à haute résistivité pour substrat composite | |
| FR3085538A1 (fr) | Tranche soi et son procede de production | |
| EP4066275B1 (fr) | Procede de fabrication d'une structure composite comprenant une couche mince en sic monocristallin sur un substrat support en sic | |
| EP2110458B1 (fr) | Four de traitement thermique avec chauffage inductif | |
| FR2542500A1 (fr) | Procede de fabrication d'un dispositif semiconducteur du type comprenant au moins une couche de silicium deposee sur un substrat isolant | |
| FR3068506A1 (fr) | Procede pour preparer un support pour une structure semi-conductrice | |
| JP7153582B2 (ja) | 成膜方法及び成膜装置 | |
| WO2024089359A1 (fr) | Procédé de formation d'une couche de carbure de silicium | |
| FR2516097A1 (fr) | Procede de deposition de silicium par plasma | |
| EP4070369B1 (fr) | Procédé de formation d'un substrat de manipulation pour une structure composite ciblant des applications rf et substrat de manipulation | |
| EP3568505B1 (fr) | Chambre de traitement pour un reacteur de depot chimique en phase vapeur (cvd) et procede de thermalisation mis en oeuvre dans cette chambre | |
| FR3147427A1 (fr) | Procédé de fabrication d’un substrat | |
| WO2025068410A1 (fr) | Procede de traitement d'un substrat de carbure de silicium | |
| JP4570186B2 (ja) | プラズマクリーニング方法 | |
| EP4634969A1 (fr) | Procédé de stabilisation d'une surface en un matériau semiconducteur | |
| FR3148671A1 (fr) | Procédé de fabrication d’une pluralité de substrats de carbure de silicium polycristallin | |
| EP1566468A2 (fr) | Procédé pour la fabrication de circuits intégrés et dispositif correspondant. | |
| FR3138239A1 (fr) | Procédé de fabrication d’un substrat support pour application radiofréquences | |
| JP3486292B2 (ja) | 金属メッシュヒータのクリーニング方法 | |
| TW202614158A (zh) | 區域選擇性碳部分間隙填充製程 | |
| WO2025195677A1 (fr) | Procede de traitement d'un substrat presentant une face arriere en carbure de silicium polycristallin | |
| FR2916302A1 (fr) | Procede de fabrication de substrat pour circuit integre, et substrat pour circuit integre |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: UNKNOWN |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
| 17P | Request for examination filed |
Effective date: 20250520 |
|
| AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
| DAV | Request for validation of the european patent (deleted) | ||
| DAX | Request for extension of the european patent (deleted) | ||
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 20251205 |