EP4315409A1 - Architecture de circuit intégré hybride - Google Patents

Architecture de circuit intégré hybride

Info

Publication number
EP4315409A1
EP4315409A1 EP21933454.7A EP21933454A EP4315409A1 EP 4315409 A1 EP4315409 A1 EP 4315409A1 EP 21933454 A EP21933454 A EP 21933454A EP 4315409 A1 EP4315409 A1 EP 4315409A1
Authority
EP
European Patent Office
Prior art keywords
wafer
component chip
component
contact pad
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21933454.7A
Other languages
German (de)
English (en)
Inventor
Florian G. Herrault
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HRL Laboratories LLC
Original Assignee
HRL Laboratories LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HRL Laboratories LLC filed Critical HRL Laboratories LLC
Priority claimed from US17/214,374 external-priority patent/US11527482B2/en
Publication of EP4315409A1 publication Critical patent/EP4315409A1/fr
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other

Definitions

  • This presentation relates to electronic assemblies; in particular electronic assemblies comprising one or more microelectronic components integrated into a microelectronic wafer fabricated separately.
  • Electronic assemblies, or hybrid circuits comprise microelectronic circuits fabricated separately and assembled together so as to form a single component, which can itself be encapsulated in an electronic circuit package.
  • Assembling microelectronic circuits fabricated separately allows one to, for example, test all the microelectronic circuits separately, prior to assembling them, which, in turn enables improved fabrication yields of the final component. This capability is particularly significant if some of the microelectronic circuits fabricated separately are difficult and/or expensive to manufacture.
  • Assembling microelectronic circuits fabricated separately also allows one to combine microelectronic circuits, which themselves employ different materials and different manufacturing processes, into a single final component. This capability can lead to higher circuit performance.
  • US Patent number 8,617,927 and US Patent number 9,214,404 which are hereby incorporated by reference in their entirety, disclose a method and apparatus for mounting microelectronic chips to a thermal heat sink.
  • the chips are arranged in a desired configuration with their active faces all facing a common direction and with their active faces defining a common planar surface for all of said chips.
  • a metallic material is applied to the chip, preferably by electroplating to backsides of the chips, the metallic material being electro-formed thereon and making void-free contact with the backsides of the chips.
  • US Patent number 9,508,652 which is hereby incorporated by reference in its entirety, discloses a method for wafer level packaging that includes forming one or more die, forming a plated metal ring (PMR) on each die, forming a cover wafer (CW), the CW having one or more plated seal rings, forming a body wafer (BW), the BW having cavities and a metal layer on a first side of the BW, aligning a respective die to the CW so that a PMR on the respective die is aligned to a respective plated seal ring (PSR) on the CW, bonding the PMR on the respective die to the respective PSR, aligning the BW to the CW so that a respective cavity of the BW surrounds each respective die bonded to the CW and so that the metal layer on the BW is aligned with at least one PSR on the CW, and bonding the metal layer on the first side of the BW to the PSR on the CW.
  • Each PMR has a first
  • An electroplated metallic layer is disposed on the metallic membrane layer.
  • Multiple interconnects can be formed in parallel using manufacturing techniques compatible with wafer level fabrication of the interconnects.
  • the interconnects preferably follow a smooth curve to electrically connect adjacent pads and following that smooth curve they bridge over the intervening electrically conductive heat sink material in a predictable fashion.
  • US Patent number 9,337,124 which is hereby incorporated by reference in its entirety, discloses a method for forming a wafer level heat spreader that includes providing a mesh wafer, the mesh wafer having a plurality of openings and mesh regions between the openings, bonding the mesh wafer to a backside of an integrated circuit (IC) wafer, the IC wafer comprising a plurality of circuits; and electroplating a heat sink material through the plurality of openings and onto to the backside of the IC wafer.
  • IC integrated circuit
  • Embodiments of the presentation comprise an electronic assembly or hybrid circuit where a microelectronic circuit in a wafer is connected to a microelectronic circuit in a chip; the chip being embedded in a metal-filled cavity of the wafer, wherein the microelectonic circuit in the wafer and the microelectonic circuit in the chip have contact pads on opposite surfaces of the assembly, and wherein a conductor connects saidcontact pads.
  • an embodiment of this presentation comprises an electronic assembly (for example 10), with: a carrier wafer (for example 12) having a top wafer surface (for example 14) and a bottom wafer surface (for example 16); an electronic integrated circuit being formed in the carrier wafer (for example 12) and comprising a first integrated circuit contact pad (for example 18) on the top wafer surface (for example 14); said carrier wafer (for example 12) comprising a through-wafer cavity (for example 20) having walls (for example 22) that join said top wafer surface (for example 14) to said bottom wafer surface (for example 16); a first component chip (for example 24) having a first component chip top surface (for example 26), a first component chip bottom surface (for example 28) and first component chip side surfaces (for example 30), the first component chip (for example 24) being held in said through-wafer cavity (for example 20) by direct contact of at least a side surface (for example 30) of said first component chip (for example 24)
  • said carrier wafer (for example 12) and said first component chip (for example 24) have a same thickness, and wherein said first conductor (for example 36, 38; 37, 32) comprises a via (for example 38) traversing said first component chip (for example 24).
  • said first conductor (for example 36, 38; 37, 32) comprises a metal strip or wire (for example 36) connecting said first integrated circuit contact pad (for example 18) to a top portion of said via (for example 38) traversing said first component chip (for example 24).
  • said carrier wafer (for example 12) and said first component chip (for example 24) have a same thickness, wherein said atttachment metal (for example 32) fills said at least a portion of said through-wafer cavity (for example 20) along the full height of said through-wafer cavity (for example 20); and wherein said first conductor (for example 36, 38; 37, 32) comprises said attachment metal (for example 32).
  • said first conductor (for example 36, 38; 37, 32) comprises a metal strip or wire (for example 37) connecting said first integrated circuit contact pad (for example 18) to a top portion of said attachment metal (for example 32).
  • said attachment metal covers at least a portion of said first component chip bottom surface (for example 28) and said first component contact pad (for example 34).
  • said atttachment metal fills said at least a portion of said through-wafer cavity (for example 20) along the full height of said through-wafer cavity (for example 20); wherein said first conductor (for example 36, 38; 37, 32) comprises a metal strip or wire (for example 37) connecting said first integrated circuit contact pad (for example 18) to a top portion of said attachment metal (for example 32).
  • said attachment metal covers at least a portion of said first component chip bottom surface (for example 28) and said first component contact pad (for example 34).
  • said first conductor for example 36, 38; 37, 32
  • said attachment metal for example 32
  • said attachment metal covers at least a portion of said first component chip bottom surface (for example 28), a bottom portion of said via (for example 40) traversing said first carrier wafer (for example 12).
  • said carrier wafer for example 12
  • said first component chip for example 24
  • the attachment metal for example 32
  • said first component chip for example 24
  • said first conductor for example 36, 38; 37, 32
  • said first conductor (for example 36, 38; 37, 32) comprises a metal strip or wire (for example 36) connecting said first integrated circuit contact pad (for example 18) to a top portion of said via (for example 38) traversing said first component chip (for example 24).
  • the walls (for example 22) of the through-wafer cavity (for example 20) are covered with a dielectric layer (42).
  • the carrier wafer (for example 12) and the first component chip (for example 24) are made of different materials.
  • the first component chip (for example 24) is an integrated circuit chip comprising one or more transistors.
  • the electronic assembly comprises a second component chip (for example 24') also held in said through-cavity (for example 20) by direct contact of at least a side surface (for example 30') of said second component chip (for example 24') with said attachment metal (for example 32); said second component chip (for example 24') comprising at least one second component contact pad (for example 34') on one of a top surface (for example 26') and a bottom surface (for example 28') of the second component chip (for example 24'); the electronic integrated circuit formed in the carrier wafer comprising a second integrated circuit contact pad (for example 18'; 18) on one of the top wafer surface (for example 14) and the bottom wafer surface (for example 16); wherein a second conductor (for example 36', 38'; 32, 37) connects the second integrated circuit contact pad (for example 34') and the second component contact pad (for example 18', 18).
  • a second conductor for example 36', 38'; 32, 37
  • At least one of the first component chip (for example 24) and the second component chip (for example 24') is thinner than the wafer, and the attachment metal (for example 32) holds the first and second component chips (for example 24, 24') such that the first and second component chip top surfaces (for example 26, 26') are flush with the top wafer surface.
  • Figure 1 is a cross-section of an electronic assembly according to an embodiment of this presentation.
  • Figure 2 is a cross-section of an electronic assembly according to an embodiment of this presentation.
  • Figure 3 is a cross-section of an electronic assembly according to an embodiment of this presentation.
  • Figure 4 is a cross-section of an electronic assembly according to an embodiment of this presentation.
  • Figure 5 is a cross-section of an electronic assembly according to an embodiment of this presentation.
  • Figure 6 is a cross-section of an electronic assembly according to an embodiment of this presentation.
  • Figure 7 is an elevation view of a component chip that can be used in an electronic assembly according to an embodiment of this presentation.
  • Figures 8 A to 8C illustrate steps of a method of manufacturing an electronic assembly according to embodiments of this presentation.
  • Figures 9A to 9C illustrate steps of a method of manufacturing an electronic assembly according to embodiments of this presentation.
  • any element in a claim that does not explicitly state "means for” performing a specified function, or “step for” performing a specilic function, is not to be interpreted as a "means” or “step” clause as specified in 35 U.S.C. Section 112, Paragraph 6.
  • the use of "step of' or “act of in the claims herein is not intended to invoke the provisions of 35 U.S.C. 112, Paragraph 6.
  • An electronic assembly according to embodiments of this presentation integrates high-performance integrated circuits, such as GaN RF MMICs, into carrier wafers having integrated circuits, such as silicon-based integrated circuits, in a manner that is inexpensive and has high manufacturing yields and short manufacturing cycles.
  • the high performance integrated circuit or component can comprise Ill-Nitride transistors or integrated circuits and they can be integrated, eventually together with resistors, inductors, capacitors and matching networks, into the carrier wafers.
  • Figure 1 illustrates a cross-section view of an electonic assembly 10 according to embodiments of this presentation, comprising: a carrier wafer 12 having a top wafer surface 14 and a bottom wafer surface 16; an electronic integrated circuit (not shown) being formed in the carrier wafer and comprising at least one first integrated circuit contact pad 18 on the top wafer surface 14.
  • carrier wafer 12 comprises at least one through-wafer cavity 20 having walls 22 that join top wafer surface 14 to bottom wafer surface 16.
  • a first component chip 24 having a top surface 26, a bottom surface 28 and side surfaces 30, is held in the through-wafer cavity 20 by an attachment material 32 that attaches at least one wall 22 of the through-wafer cavity 20 to at least one of the bottom surface 28 and a side surface 30.
  • attachment material 32 is a metal and it holds the first component chip (24) in said through-wafer cavity (20) by being in direct contact with at least a side surface (30) of the first component chip (24).
  • the electronic integrated circuit of carrier wafer 12 can be formed within the top wafer surface 14 using known integrated circuit manufacturing processes, including but not limited to photolithography, epitaxial growth, oxidization of exposed layers, etc...
  • the carrier wafer 12 and the first component chip 24 have a same thickness.
  • attachment metal 32 can fill cavity 20, thus attaching most of the side surfaces of first component chip 24 to the walls 22 of through-wafer cavity 20.
  • standard thickness it is meant that a difference in thickness between the carrier wafer and the component chip is negligible.
  • the first component chip 24 comprises at least one first component contact pad 34 on the first component chip bottom surface 28, and a first conductor 36, 38 connects the first integrated circuit contact pad 18 to the first component contact pad 34.
  • the first conductor 36, 38 comprises a via 38 that traverses the first component chip 24 from its top surface 26 to its bottom surface 28, where via 38 contacts the contact pad 34.
  • the first conductor 36, 38 further comprises a metal strip or wire 36 that connects the first integrated circuit contact pad 18 to a top portion of via 38 on the first component chip top surface 26.
  • the metal strip or wire 36 is formed using a top metal fabrication process compatible with the fabrication process of the electronic integrated circuit of carrier wafer 12 (e.g. CMOS).
  • This fabrication process can comprise passivating the top surface of the assembly, mask etching contact openings and forming the metal strip or wire 36 by masking and sputtering.
  • the first component chip 24 can comprise at least one vertical transistor that has top contact pads (not shown) on top surface 26, for example connected to the gate and source of the transistor, and wherein contact pad 34 is connected to the drain of the transistor.
  • Figure 2 illustrates an electronic arrangement 10' according to an embodiment of this presentation, that is identical to the embodiment in Figure 1 except that the first component chip 24 does not comprise via 38.
  • the attachment metal 32 fills at least a portion of cavity 20 along all the height of cavity wall 22 such that a top portion of the attachment metal 32 is flush with the top surface 14 of carrier wafer 12.
  • Attachment metal 32 also covers at least a portion of the bottom side 28 of component chip 24, and touches the contact pad 34.
  • a metal strip or wire 37 connects the contact pad 18 to the top portion of the attachment metal 32 that is flush with the top surface 14 of carrier wafer 12.
  • Metal strip or wire 37 can be formed, in the same way as metal strip or wire 36, using a top metal fabrication process compatible with the fabrication process of the electronic integrated circuit of carrier wafer 12.
  • the top portion of metal 32 being "flush" with the top wafer surface 14 is to be understood as meaning that the two surfaces are in a same plane, or have, with respect to each other, a small or negligible height difference.
  • the attachment metal 32 can extend along portions of the bottom surface 16 of the carrier wafer 12 as well as portions of the bottom surface 28 of component chip 24. Metal etching can be used to separate portions of the attachment metal 32 on the bottom surfaces of arrangement 10', so as to electrically isolate said portions from each other.
  • component chip 24 can also be thinner than carrier wafer 12, as illustrated for example in Figure 6 hereafter.
  • Figure 3 illustrates an electronic arrangement 10" according to an embodiment of this presentation, that is identical to the embodiment in Figure 1 except that the first component chip 24 is thinner than the carrier wafer 12.
  • the contact metal 32 can attach component chip 24 by direct contact with one or more side surfaces 30 and walls 22 of the through wafer cavity 20.
  • attachment metal 32 holds the first component chip 24 such that the first component chip top surface 26 is flush with the top wafer surface 14.
  • the first component chip top surface 26 being "flush" with the top wafer surface 14 is to be understood as meaning that the two surfaces are in a same plane, or have, with respect to each other, a small or negligible height difference, such as resulting from the process of permanently attaching first component chip 24 to the walls 22 of through wafer cavity 20 while both the first component chip top surface 26 and the top wafer surface 14 are attached temporarily to a same handle wafer, for example according to a process as illustrated hereafter.
  • a small or negligible height difference such as resulting from the process of permanently attaching first component chip 24 to the walls 22 of through wafer cavity 20 while both the first component chip top surface 26 and the top wafer surface 14 are attached temporarily to a same handle wafer, for example according to a process as illustrated hereafter.
  • the conductor that connects the top integrated circuit contact pad 18 to the bottom component chip contact pad 34 comprises as in Figure 1 a via 38 that traverses the first component chip 24.
  • Attachment metal 32 fills at least a portion of through-wafer cavity so as to directly contact at least a portion of the walls 30 of component chip 24, but it can optionally also contact at least a portion of the bottom surface 28 of component chip 24 (and contact at least a portion of contact pad 34), as illustrated in Figure 3.
  • Figure 4 illustrates an electronic arrangement 10"' according to an embodiment of this presentation, that is identical to the embodiment in Figure 2 except that, in order to connect the top integrated circuit contact pad 18 to the bottom component chip contact pad 34, carrier wafer 12 comprises a via 40 connecting contact pad 18 to the bottom surface 16 of carrier wafer 12. Further, the attachment metal 32 fills at least a portion of cavity 20 and covers a portion of bottom surface 16 such that it contacts both a bottom portion of via 40 and bottom contact pad 34. Optionally and as illustrated in Figure 4, the first component chip 24 is thinner than the carrier wafer 12.
  • Figure 5 illustrates an electronic arrangement 100 according to an embodiment of this presentation, that is identical to the embodiment in Figure 1 except that it comprises a second component chip 24' having a top surface 26', a bottom surface 28', side walls 30', a bottom contact pad 34' and a via 38' connecting the contact pad 34' to the top surface 26' held in through- wafer cavity 20.
  • carrier wafer 12 comprises a second top contact pad 18' connected to the electronic integrated circuit (not shown) formed in the carrier wafer, and a conductor 36' similar to conductor 36 connects integrated circuit contact pad 18' to a top portion of via 38' and, through the via, to component contact pad 34'.
  • component chip 24' is held in through-wafer cavity 20 by direct contact with attachment metal 32.
  • Attachment metal 32 can fill a portion or the totality of the space between the walls 22 of cavity 20 and the walls of the component chip (Fig. 1) or chips (Fig. 5) in the cavity.
  • the component chips 24, 24' have the same thickness as carrier wafer 12, but they can optionally be thinner than the carrier wafer 12.
  • Figure 6 illustrates an electronic arrangement 100' according to an embodiment of this presentation, that is identical to the embodiment in Figure 2 except that it comprises a second component chip 26' held in through-wafer cavity' 20, having a top surface 26', a bottom surface 28', side walls 30' and a bottom contact pad 34', but no via 38'.
  • the attachment metal 32 fills at least a portion of cavity 20 along all the height of cavity wall 22 such that a top portion of the attachment metal 32 is flush with the top surface 14 of carrier wafer 12.
  • Attachment metal 32 also covers at least a portion of the bottom sides 28 and 28' of component chips 24 and 24', and touches the contact pads 34 and 34'.
  • a metal strip or wire 37 connects the contact pad 18 to the top portion of the attachment metal 32 that is flush with the top surface 14 of carrier wafer 12, thus contacting top contact pad 18 to bottom pads 34 and 34'.
  • the component chips 24, 24' can also comprise top contact pads 102, 102' connected to a top contact pad 104 of carrier wafer 12 using a metal line or wire 106. Such top contact connections can also be present in the embodiments of Figures 1-5, as illustrated for example in Figures 3 and 4. [0060].
  • the walls 22 of the through- wafer cavity 20 can be covered with a dielectric 42, as illustrated in Figure 6.
  • the carrier wafer 12 and the component chip 24 are made of different materials.
  • the carrier wafer can be a silicon wafer, with an integrated circuit made using known CMOS technology
  • the component chip 24 can comprise a III-V material substrate with one or more III-V HEMT transistors.
  • Figure 7 is a schematic elevation view of a component chip 24 according to embodiments of this presentation, comprising three vertical HEMT transistors 108 having each a trench gate electrode 110, top surface source regions 112 on both side of the gate trench, and a bottom surface drain region 114.
  • contact pad 34 is in electrical contact with drain region 114.
  • Contact pads for the gate and source of component chip 24 can be present on top surface 26 but are not illustrated in Figure 7. Such top contact pads can be such as contact pads 102 or 102' of Figures 3, 4 or 6.
  • Component chip 24 can also comprise passive circuit elements (not shown).
  • Figures 8 A to 8C illustrate steps of a method of manufacturing an electronic assembly according to embodiments of this presentation.
  • first steps of the method comprise: providing a first component chip 24 having a first component chip top surface 26, a first component chip bottom surface 28 and first component chip side surfaces/walls 30; first component chip 24 comprising at least one first component contact pad 34 on the first component chip bottom surface 28, and also comprising a via 38 providing an electrical path between the first component chip top surface 26 and the first component contact pad 34.
  • the method further comprise providing a handle wafer 44 having a top surface 46; and attaching, for example using a temporary adhesive layer 50, the top surface 26 of component chip 24 (flipped upside down) to the top surface 46 of the handle wafer 44.
  • the method further comprise, still refering to Figure 8A, providing a carrier wafer 12 having a top wafer surface 14 and a bottom wafer surface 16; forming in the carrier wafer 12 an electronic integrated circuit 48 (for example using known photolithography manufacturing processes) having a first integrated circuit contact pad 18 on the top wafer surface 14; forming in the carrier wafer a through-wafer cavity 20 having walls 22 that join the top wafer surface 14 to the bottom wafer surface 16; and attaching the top wafer surface 14 of carrier wafer 12 (flipped upside down) to the top surface 46 of handle wafer 44 such that first component chip 24 is arranged within the through- wafer cavity 20.
  • wafer 12 can be thinned, for example at this stage, by polishing bottom surface 16.
  • the method further comprises filling at least a portion of the through-wafer cavity 20 with an electrically conductive attachment material 32, preferably metal, so as to hold the first component chip 24 in the through- wafer cavity 20 by direct contact of at least one side surface 30 of the first component 24 with the attachment metal 32.
  • attachment material 32 is a metal
  • at least a portion of the space in cavity 20, between the component chip walls 30 and the cavity walls can be filled using an electrometallurgy process (electroforming or electroplating or electrodeposition). If electroforming is used, a film of metal can be deposited on the walls 22 of the through- cavity 20 and on the exposed surfaces of component chip 24 before said electroforming.
  • a layer of dielectric can be deposited on the walls 22.
  • attaching component chip 24 to the walls 22 of the through wafer cavity when both the top surfaces 14, 26 of the carrier wafer 12 and the component chip 24 are temporarily attached to surface 46 of handle wafer 44 allows ensuring that the top surfaces 14, 26 of the carrier wafer 12 and the component chip 24 are flush.
  • the method further comprises detaching the handle wafer 44 from the first component chip top surface 26 and the top wafer surface 14; and (after flipping the carrier wafer 12 and attached component chip 24), forming a conductor, such as a metal line or strip 36, between the first integrated circuit contact pad 18 and a top portion of via 38.
  • a conductor such as a metal line or strip 36
  • metal line or strip 36 can be manufactured using top metal manufacturing process steps of the manufacturing process steps used to make integrated circuit 48.
  • Figures 9 A to 9C illustrate steps of a method of manufacturing an electronic assembly according to embodiments of this presentation.
  • first steps of the method comprise: providing a first component chip 24 having a first component chip top surface 26, a first component chip bottom surface 28 and first component chip side surfaces/walls 30; first component chip 24 comprising at least one first component contact pad 34 on the first component chip bottom surface 28, and also comprising a via 38 providing an electrical path between the first component chip top surface 26 and the first component contact pad 34.
  • the method further comprise providing a handle wafer 44 having a top surface 46; and attaching, for example using a temporary adhesive layer 50, the top surface 26 of component chip 24 (flipped upside down) to the top surface 46 of the handle wafer 44.
  • the method further comprise, still refering to Figure 9A, providing a carrier wafer 12 having a top wafer surface 14 and a bottom wafer surface 16; forming in the carrier wafer 12 an electronic integrated circuit 48 (for example using known photolithography manufacturing processes) having a first integrated circuit contact pad 18 on the top wafer surface 14; forming in the carrier wafer a through- wafer cavity 20 having walls 22 that join the top wafer surface 14 to the bottom wafer surface 16; and attaching the top wafer surface 14 of carrier wafer 12 (flipped upside down) to the top surface 46 of handle wafer 44 such that first component chip 24 is arranged within the through-wafer cavity 20.
  • an electronic integrated circuit 48 for example using known photolithography manufacturing processes
  • the method further comprises filling at least a portion of the through-wafer cavity 20 with an electrically conductive attachment material 32, preferably metal, so as to hold the first component chip 24 in the through- wafer cavity 20 by direct contact of at least one side surface 30 of the first component 24 with the attachment metal 32, and also as to contact bonding pad 34 with conductive attachment material 32.
  • an electrically conductive attachment material 32 preferably metal
  • attachment material 32 is a metal
  • at least a portion of the space in cavity 20, between the component chip walls 30 and the cavity walls can be filled using an electrometallurgy process.
  • attaching component chip 24 to the walls 22 of the through wafer cavity 20 when both the top surfaces 14, 26 of the carrier wafer 12 and the component chip 24 are temporarily attached to surface 46 of handle wafer 44 allows ensuring that the top surfaces 14, 26 of the carrier wafer 12 and the component chip 24 are flush.
  • conducting material 32 preferably fills cavity 20 such that a surface of conductive material 32 is flush with top surface 14 of carrier wafer 12.
  • wafer 12 can be thinned, for example at this stage, by polishing bottom surface 16.
  • the method further comprises detaching the handle wafer 44 from the first component chip top surface 26 and the top wafer surface 14; and (after flipping the carrier wafer 12 and attached component chip 24), forming a conductor, such as a metal line or strip 37, between the first integrated circuit contact pad 18 and the surface of conductive material 32 that is flush with top surface 14 of carrier wafer 12.
  • a conductor such as a metal line or strip 37
  • metal line or strip 37 can be manufactured using top metal manufacturing process steps of the manufacturing process steps used to make integrated circuit 48.
  • Component chips 24, 24' are preferably pre-tested to verify their functionality before assembly. As a result, the yield of a final devices comprising a plurality of component chips 24, 24' is improved compared to a component manufacturing the circuits in components chips 24, 24'; on a same wafer.
  • a component chip 24 (comprising a single chip or a plurality of component chips 24, 24', etc., as outlined above) in a metal-filled cavity allows to significantly drain any chip-produced heat, which in return limits significantly any size change due to a temperature change, and allows any mechanical strain due to such size change to remain moderate, even though metal is not resilient.
  • material 32 can also be non-metallic, in which case it can be chosen to be a material with greater pliability, although at the expense of having a reduced thermal conductivity.
  • component chip 24 can comprise a GaN, InP or GaAs component and it can be fabricated on a substrate such as Si, SiGe, InP, GaAs, Alumina, or diamond.
  • the integrated circuit 48 of carrier wafer 12 can comprise metal routing and passive components fabricated at the wafer scale.
  • conductors 36, 37 can be made out of thin films, thick, plated interconnects, multi-layers, etc.
  • the interconnections can for example be made using the back-end steps of a CMOS manufacturing process.
  • any of the component chip 24 and the carrier wafer 12 can comprise integrated cicuitry, including active and/or passive circuitry, on both their top and bottom surfaces, thus allowing the manufacture of compact assemblies.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un ensemble électronique comportant une tranche porteuse dotée d'une surface supérieure de tranche et d'une surface inférieure de tranche; un circuit intégré électronique étant formé dans la tranche porteuse et comportant une plage de contact de circuit intégré sur la surface supérieure de tranche; ladite tranche porteuse comportant une cavité traversant la tranche dotée de parois qui joignent ladite surface supérieure de tranche à ladite surface inférieure de tranche; une puce de composant dotée d'une surface supérieure de puce de composant, d'une surface inférieure de puce de composant et de surfaces latérales de puce de composant, la puce de composant étant maintenu dans ladite cavité traversant la tranche par contact direct d'au moins une surface latérale de ladite puce de composant avec un métal de fixation qui remplit au moins une partie de ladite cavité traversant la tranche; ladite puce de composant comportant au moins une plage de contact de composant sur ladite surface inférieure de puce de composant; et un conducteur reliant ladite plage de contact de circuit intégré et ladite plage de contact de composant.
EP21933454.7A 2021-03-26 2021-03-26 Architecture de circuit intégré hybride Pending EP4315409A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/214,374 US11527482B2 (en) 2017-12-22 2021-03-26 Hybrid integrated circuit architecture
PCT/US2021/024519 WO2022203690A1 (fr) 2021-03-26 2021-03-26 Architecture de circuit intégré hybride

Publications (1)

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EP4315409A1 true EP4315409A1 (fr) 2024-02-07

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EP (1) EP4315409A1 (fr)
CN (1) CN117043929A (fr)
WO (1) WO2022203690A1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1880417A2 (fr) * 2005-05-11 2008-01-23 STMicroelectronics SA Microplaquette de silicium ayant des plages de contact inclinees et module electronique comprenant une telle microplaquette
JP5758592B2 (ja) * 2010-06-16 2015-08-05 株式会社メムス・コア 露光による実装体及び多品種実装体の露光による製造方法
US20140264808A1 (en) * 2013-03-15 2014-09-18 Andreas Wolter Chip arrangements, chip packages, and a method for manufacturing a chip arrangement
WO2019125587A1 (fr) * 2017-12-22 2019-06-27 Hrl Laboratories, Llc Architecture de circuit intégré hybride
KR102582422B1 (ko) * 2018-06-29 2023-09-25 삼성전자주식회사 재배선층을 갖는 반도체 패키지

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WO2022203690A1 (fr) 2022-09-29
CN117043929A (zh) 2023-11-10

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