Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
  • H01L29/76—Unipolar devices, e.g. field effect transistors
  • H01L29/772—Field effect transistors
  • H01L29/78—Field effect transistors with field effect produced by an insulated gate
  • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
  • H01L29/78651—Silicon transistors
  • H01L29/78654—Monocrystalline silicon transistors
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
  • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
  • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
  • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
  • H01L29/51—Insulating materials associated therewith
  • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
  • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
  • H01L29/66007—Multistep manufacturing processes
  • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
  • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
  • H01L29/66409—Unipolar field-effect transistors
  • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
  • H01L29/66742—Thin film unipolar transistors
  • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates

Definitions

• the present invention relates to a negative-capacitance field-effect transistor (NC-FET) comprising a semiconductor-on-insulator type substrate.
• NC-FET negative-capacitance field-effect transistor
• FDSOI Semiconductor on insulator type substrates, in particular those totally depleted, known by the acronym FDSOI, from the Anglo-Saxon term “Fully Depleted Silicon On Insulator”, are frequently used in the field of microelectronics, in particular for manufacturing transistors.
• An FDSOI substrate successively comprises a support substrate, a buried oxide layer (often designated by the acronym BOX, for "Buried OXide”) and an ultrathin layer of monocrystalline silicon, which is the active layer, i.e. say in or on which electronic components are intended to be formed.
• BOX buried oxide layer
• ultrathin it is meant in the present text that the thickness of the silicon layer is less than or equal to 20 nm. The great thinness of the active layer, and, where appropriate, of the oxide layer, allow the active layer of a transistor formed from this substrate to be completely depleted.
• the threshold voltage (VT, “threshold voltage” in English), that is to say the minimum voltage to be applied to the front face gate and the source to make the on-transistor can be controlled by applying a bias voltage (Vbb “back bias voltage” in English) to a gate on the rear face.
• NC-FET negative capacitance field effect transistor
• Figure 1 illustrates such a transistor.
• the NC-FET transistor successively comprises from its base (or rear face) towards its surface (or front face), a substrate 1, a dielectric layer (BOX) 4 and an active layer 3a, a region 3b of which forms the channel of the transistor 3b .
• Channel 3b is covered by a gate insulation layer 30, on which a ferroelectric layer 5 is arranged.
• Electrode 20 of gate 10 is placed above said ferroelectric layer 2.
• the electrodes 21 and 22 of the source 11 and of the drain 12 are arranged on the two respective sides of the stack comprising the gate 10.
• An object of the invention is to design an NC-FET transistor which allows better control of the electric current in the active layer, faster switching of the transistor, and improved coupling with the gate on the rear face, while presenting a simple structure and can be manufactured with existing processes.
• the invention proposes an NC-FET transistor comprising a semiconductor-on-insulator type substrate for a fast-switching field-effect transistor, successively comprising, from its base to its surface:
• NC-FET transistor • an active layer of a semiconductor material, adapted to form the channel of the transistor, arranged in direct contact with the ferroelectric layer, said NC-FET transistor further comprising a channel arranged in the active layer, a source and a drain arranged in the active layer on either side of the channel, and a gate arranged on the channel, insulated from said channel by a gate dielectric.
• Direct contact between two layers means direct contact over the extent of the interface between the layers concerned.
• the proposed architecture makes it possible to integrate in the ferroelectric layer, which forms the electrically insulating layer of the semiconductor-on-insulator substrate:
• the ferroelectric layer has a thickness comprised between 1 and 30 nm, and more advantageously comprised between 1 and 10 nm.
• the ferroelectric layer has a relative dielectric permittivity greater than 10 and particularly advantageously a relative dielectric permittivity greater than 20.
• the ferroelectric layer comprises hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, hafnium aluminate or an alloy comprising one or more of said materials
• the active layer has a thickness between 1 nm and 100 nm.
• the active layer comprises silicon, germanium, silicon-germanium alloy, gallium arsenide, indium phosphide, gallium-indium arsenide, graphene, or tungsten.
• the invention also relates to a method for manufacturing a negative-capacitance field-effect transistor, said method being mainly characterized in that it comprises the following steps:
• each ferroelectric layer being arranged at the bonding interface
• said at least one ferroelectric layer is formed by deposition of thin atomic layers or by pulsed laser ablation.
• the method comprises a heat treatment of said at least one ferroelectric layer before bonding.
• the heat treatment is carried out at a temperature of between 500°C and 1000°C.
• the heat treatment is carried out for a period of less than two hours.
• the formation of the zone of weakness comprises an implantation of hydrogen and/or helium atoms in the donor substrate.
• the method comprises, before bonding, one or more surface treatments of said at least one ferroelectric layer, said treatments comprising cleaning, plasma treatment and/or mechanical-chemical polishing.
• the method comprises, after the transfer step, annealing at a temperature less than or equal to 1000°C.
• Figure 1 is a schematic sectional view of a known type NC-FET transistor.
• FIG. 2 illustrates a semiconductor-on-insulator type substrate according to one embodiment of the invention.
• FIG. 3 is a schematic sectional view of a negative-capacitance field-effect transistor according to the invention.
• FIGS. 4A-4D illustrate steps for manufacturing an NC-FET transistor from a semiconductor-on-insulator type substrate in which a semiconductor layer is transferred onto a support substrate comprising a ferroelectric layer according to one embodiment of the invention.
• FIGS. 5A-5D illustrate steps for manufacturing an NC-FET transistor from a semiconductor-on-insulator type substrate in which a ferroelectric layer is deposited on a donor substrate and said ferroelectric layer and a semiconductor layer are transferred onto a support substrate according to a second embodiment of the invention.
• FIGS. 6A-6E illustrate steps for manufacturing an NC-FET transistor from a semiconductor-on-insulator type substrate in which a first ferroelectric layer is deposited on a donor substrate and said first ferroelectric layer and a layer semiconductor are transferred onto a support substrate comprising a second ferroelectric layer according to a third embodiment of the invention.
• Figure 2 illustrates an embodiment of an FDSOI substrate for an NC-FET transistor according to the invention.
• the FDSOI substrate comprises a support substrate 1 made of a semiconductor material, a ferroelectric layer 2 arranged on the support substrate, and an active layer 3 arranged on the ferroelectric layer.
• a support substrate 1 made of a semiconductor material
• a ferroelectric layer 2 arranged on the support substrate
• an active layer 3 arranged on the ferroelectric layer.
• on is meant a relative position of the layers by considering the layers from the base of the support substrate towards the surface on the side of the active layer.
• the layers are arranged in direct contact over the extent of their interfaces.
• the support substrate is monocrystalline.
• the support substrate may be polycrystalline, subject to being compatible with the processes implemented on the manufacturing lines of semiconductor substrates, in particular in terms of geometry of the support substrate and absence of contaminants.
• the support substrate can be made of silicon, but other semiconductor materials can be used.
• the ferroelectric layer has a relative dielectric permittivity greater than 10, preferably greater than 20.
• the ferroelectric layer can be a layer of hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, hafnium aluminate or an alloy comprising one or more of said materials.
• the ferroelectric layer has a thickness comprised between 1 and 30 nm, and more advantageously comprised between 1 and 10 nm.
• the active layer is a single-crystal semiconductor layer, suitable for forming a channel in a reverse-biased transistor.
• the active layer is preferably a layer of silicon, germanium, a silicon-germanium alloy, gallium arsenide, indium phosphide, gallium-indium arsenide, graphene or tungsten disulphide.
• the active layer typically has a thickness of between 1 nm and 100 nm.
• the ferroelectric layer which has dielectric properties, therefore replaces the BOX layer in the FDSOI substrate.
• Said ferroelectric layer thus makes it possible to delimit the channel of a transistor formed from the active layer of this substrate so that it is completely stripped.
• the ferroelectric layer simultaneously makes it possible to use the ferroelectric polarization effect in order to control the active layer very quickly.
• the ferroelectric layer combines two functions: electrical insulation of the active layer with respect to the support substrate and ferroelectric polarization at the rear of the active layer.
• FIG. 3 is a schematic sectional view of a negative-capacitance field-effect transistor based on an FDSOI substrate comprising a buried ferroelectric layer according to the invention.
• Said transistor comprises successively from its base (or rear face) towards its surface (or front face), a support substrate 1, a ferroelectric layer 2 and an active layer 3a, a region 3b of which forms the channel of the transistor.
• the channel is covered by a gate insulation layer 30 on which is placed the electrode 20 of the gate 10.
• the electrodes 21 and 22 of the source 11 and of the drain 12 are arranged on the two respective sides of the stack comprising the gate 10.
• the transistor includes a gate on the rear face (not shown) to modulate the threshold voltage.
• Said grid can be placed at a distance from the stack or be integrated into the support substrate.
• a negative bias voltage Vbb is applied to the back gate to increase the threshold voltage and reduce the leakage current, which minimizes power consumption during the off state ( or passive) of the transistor.
• a positive voltage Vbb is applied which lowers the threshold voltage and increases the current passing.
• a positive voltage Vbb results in a polarization of the ferroelectric layer such that the positive charges are localized on the upper surface of said ferroelectric layer, in contact with the channel, and greatly reduce the threshold voltage.
• a negative voltage Vbb switches the polarization of the ferroelectric layer so as to obtain negative charges at the interface between the ferroelectric layer and the channel of the transistor, which substantially increases the threshold voltage.
• the ferroelectric layer makes it possible to amplify the effect of voltage Vbb.
• the threshold voltage increases abruptly from a high value to a low value, so the slope under the threshold is steep. The steeper the slope below the threshold, the faster the switching between the ON and OFF states.
• a positive voltage Vbb is applied to the rear gate during the off state of the transistor, and a negative voltage Vbb in the conductive state.
• the on-off current ratio of the transistor is proportional to the switching speed. In an NC-FET this ratio can reach values greater than 10 5 .
• Transistors of the NC-FET type are particularly interesting for very large-scale integration applications (VLSI "Very-Large-Scale Integration” in English), such as high-performance, ultra-low-power microprocessors. [Wu et al.]
• the voltage Vbb on the back gate has an effect on the threshold voltage VT through a capacitive divider including the capacitance of the gate insulation layer, the capacitance of the depleted active layer and the capacitance of the BOX.
• the BOX layer absorbs a large part of the voltage Vbb. Only a small fraction of the voltage Vbb (approximately equal to the ratio between the thicknesses of the gate insulation layer and the BOX) is therefore used for the modulation of the threshold voltage.
• the fact that the substrate comprises a single ferroelectric dielectric layer makes it possible to greatly reduce the voltage absorbed by the dielectric layer compared to a known NC-FET transistor.
• Steps of a first embodiment are illustrated in Figures 4A - 4D.
• the starting point is a semiconductor support substrate 1 and a semiconductor donor substrate 8.
• the donor substrate may comprise silicon, germanium, a silicon-germanium alloy, gallium arsenide, indium phosphide, gallium-indium arsenide, graphene or tungsten disulphide.
• the donor substrate may be a solid substrate consisting of one of the materials belonging to the preceding list, or comprise a stack of at least two different materials, at least one of which is part of the preceding list, a layer to be transferred to be formed in said material.
• a zone of weakness 7 is formed in the donor substrate 8, so as to delimit a semiconductor layer 3.
• the zone of weakness 7 is formed in the donor substrate 8 at a predetermined depth which corresponds substantially to the thickness of the semiconductor layer 3 intended to form the channel.
• the semiconductor layer 3 typically has a thickness of between 1 nm and 100 nm.
• the zone of weakness 7 is created by implanting hydrogen and/or helium atoms in the donor substrate.
• This treatment may include, by way of illustrative and non-limiting example, chemical cleaning or plasma activation.
• a ferroelectric layer 2 is deposited on the surface of the support substrate 1.
• the ferroelectric layer 2 has a relative dielectric permittivity greater than 10, preferably greater than 20, and a thickness comprised between 1 and 30 nm, and more advantageously comprised between 1 and 10 nm.
• Filing techniques may include, by way of illustrative and non-limiting example, atomic thin layer deposition techniques (ALD, acronym of the Anglo-Saxon term “Atomic Layer Deposition”) or pulsed laser ablation (PLD, acronym of the Anglo-Saxon term Saxon “Pulsed Laser Deposition”).
• Said heat treatment is advantageously carried out at a temperature of between 500° C. and 1000° C. and advantageously for a period of less than two hours.
• a surface treatment of the ferroelectric layer is then carried out to prepare said surface for bonding by molecular adhesion.
• This treatment may comprise, without limitation, one or more stages of cleaning and/or plasma treatment and/or mechanical-chemical polishing.
• the donor substrate 8 is then bonded to the support substrate 1.
• the ferroelectric layer 2 is thus arranged at the bonding interface between the support substrate 1 and the donor substrate 8.
• a detachment of the donor substrate is caused along the embrittlement zone, so as to transfer the semiconductor layer 3 onto the support substrate 1 comprising the ferroelectric layer 2.
• Figures 5A-5D illustrate steps of a second embodiment of the fabrication process of the FDSOI substrate.
• a ferroelectric layer 2 is deposited on the donor substrate 8 as illustrated in FIG. 5A.
• Deposition techniques may include, by way of illustrative and non-limiting example, atomic thin film deposition (ALD) or pulsed laser ablation (PLD) techniques.
• ALD atomic thin film deposition
• PLD pulsed laser ablation
• the ferroelectric layer 2 has a relative dielectric permittivity greater than 10, preferably greater than 20, and a thickness comprised between 1 and 30 nm, and more advantageously comprised between 1 and 10 nm.
• Said heat treatment is advantageously carried out at a temperature of between 500° C. and 1000° C. and advantageously for a period of less than two hours.
• an embrittlement zone 7 is then formed in the donor substrate 8 so as to delimit a semiconductor layer 3 covered with the ferroelectric layer 2.
• the semiconductor layer 3 has a thickness comprised between 1 nm and 100 nm.
• Weakening zone 7 is formed in donor substrate 8 at a depth which corresponds to the thickness of semiconductor layer 3 plus the thickness of ferroelectric layer 2.
• weakening zone 7 is created by implantation of hydrogen and/or helium atoms in the donor substrate.
• the weakened zone 7 can be formed in the donor substrate 8 before the deposition of the ferroelectric layer 2. Said ferroelectric layer 2 is then deposited. It may be useful or necessary to apply a heat treatment after deposition of the ferroelectric layer 2 in order to eliminate volatile products which may interfere with the bonding on the support substrate.
• a surface treatment of the ferroelectric layer is then carried out to prepare said surface for bonding by molecular adhesion.
• This treatment may comprise, without limitation, one or more stages of cleaning and/or plasma treatment and/or mechanical-chemical polishing.
• This treatment may include, by way of illustrative and non-limiting example, chemical cleaning and/or plasma activation.
• the donor substrate 8 is then bonded to the support substrate 1.
• the ferroelectric layer 2 is thus arranged at the bonding interface between the support substrate 1 and the donor substrate 8.
• a detachment of the donor substrate is caused along the embrittlement zone, so as to transfer the semiconductor layer 3 and the ferroelectric layer 2 onto the support substrate 1 .
• Figures 6A-6E illustrate a third embodiment of the FDSOI substrate manufacturing process.
• a first ferroelectric layer 2a is deposited on the support substrate 1 as illustrated in FIG. 6A.
• the ferroelectric layer 2a has a relative dielectric permittivity greater than 10, preferably greater than 20, and a thickness comprised between 0.5 and 15 nm, and more advantageously comprised between 0.5 and 5 nm.
• a second ferroelectric layer 2b is deposited on the donor substrate 8 as illustrated in FIG. 6B.
• the ferroelectric layer 2b has a relative dielectric permittivity greater than 10, preferably greater than 20, and a thickness comprised between 0.5 and 15 nm, and more advantageously comprised between 0.5 and 5 nm, the sum of the thicknesses of the layers 2a , 2b advantageously being between 1 and 30 nm, preferably between 1 and 10 nm.
• the deposition techniques may include, by way of illustrative and non-limiting example, atomic thin film deposition (ALD) or pulsed laser ablation (PLD) techniques.
• ALD atomic thin film deposition
• PLD pulsed laser ablation
• the first ferroelectric layer 2a and the second ferroelectric layer 2b can be deposited by identical or different techniques.
• a heat treatment can then be applied to each of the substrates. Said heat treatment is advantageously carried out at a temperature of between 500° C. and 1000° C. and advantageously for a period of less than two hours.
• the heat treatments of the first ferroelectric layer 2a and of the second ferroelectric layer 2b can be identical or different.
• an embrittlement zone 7 is then formed in the donor substrate 8 so as to delimit a semiconductor layer 3 comprising the ferroelectric layer 2b.
• the semiconductor layer 3 has a thickness of between 1 nm and 100 nm.
• Weakening zone 7 is formed in donor substrate 8 at a depth which corresponds to the thickness of semiconductor layer 3 plus the thickness of ferroelectric layer 2.
• weakening zone 7 is created by implantation of hydrogen and/or helium atoms in the donor substrate.
• the weakened zone 7 can be formed in the donor substrate 8 before the deposition of the ferroelectric layer 2b.
• said ferroelectric layer 2b is deposited. It may be useful or necessary to apply a heat treatment after deposition of the ferroelectric layer 2b in order to eliminate volatile products which may interfere with bonding to the substrate.
• a surface treatment can be applied to each of the substrates.
• the surface treatment may include, without limitation, one or more cleaning and/or plasma treatment and/or mechanical-chemical polishing steps.
• the treatments can be identical or different for the first ferroelectric layer 2a and for the second ferroelectric layer 2b.
• the donor substrate 8 comprising the ferroelectric layer 2b is then glued onto the support substrate 1 comprising the ferroelectric layer 2a.
• the ferroelectric layers 2a and 2b are thus superimposed, together forming a ferroelectric layer 2 at the bonding interface between the support substrate 1 and the donor substrate 8.
• a detachment of the donor substrate is caused along the embrittlement zone, so as to transfer the semiconductor layer 3 and the ferroelectric layer 2b onto the support substrate 1 comprising the ferroelectric layer 2a.
• the layer transfer process is however not limited to the Smart CutTM process; thus, it may consist, for example, in bonding the donor substrate to the support substrate via the ferroelectric layer(s) and then in thinning the donor substrate by its face opposite the support substrate to the obtaining the desired thickness for the semiconductor layer. In this case, it is not necessary to form an embrittlement zone in the donor substrate.
• one or more steps of annealing the FDSOI substrate can be carried out at temperatures preferably less than or equal to 1000°C.
• This annealing has the effect of stabilizing the adhesion between the ferroelectric layer and the transferred semiconductor layer, as well as the characteristics of the ferroelectric material, such as its dielectric constant.
• the annealing can be carried out in a single step, for example a gradual rise in temperature between 200°C up to 1000°C, then a plateau at 1000°C for a period of 1-2 hours, followed by a descent to temperature ambient, this example being given for purely illustrative and non-limiting purposes.
• the annealing comprises several distinct steps.
• a first annealing is carried out at 500-800°C in an oven with a plateau of 2-5 hours at 800°C.
• This step is followed by rapid thermal annealing (RTA, acronym for the Anglo-Saxon term “Rapid Thermal Annealing”) at 1000° C. for a period of between 30 seconds and a few minutes.
• RTA rapid thermal annealing
• a gate dielectric layer 30 is deposited on an area of active layer 3 intended to form channel 3b of the transistor.
• the thickness and the material of said dielectric layer are chosen to satisfy the pre-established electrical conditions in the specifications of the transistor, for example the value of the dielectric capacity and the minimum thickness from which tunnel currents occur.
• such a layer can be formed from silicon oxide or another oxide having good electrical insulation.
• a gate electrode 20 of electrically conductive material is then formed on dielectric layer 30.
• a source electrode 21 and a drain electrode 22 of electrically conductive material are formed directly on active layer 3, so that the gate dielectric layer is arranged between the source electrode 21 and the drain electrode 22.
• the source, channel and drain regions are formed by a step of doping the active layer in the areas intended to form the respective electrodes. The formation of the source electrode and the drain electrode can be carried out before or after the deposition of the dielectric and the gate electrode.
• a plurality of transistors can be produced by depositing a plurality of dielectric layers and a plurality of drain, source and gate electrodes on a single substrate having dimensions greater than an NC-FET transistor to be formed. The substrate is then cut in order to separate the individual NC-FET transistors.

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• 2021
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