Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/26—Bombardment with radiation
  • H01L21/263—Bombardment with radiation with high-energy radiation
  • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
  • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
  • H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
  • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
  • H01L21/76—Making of isolation regions between components
  • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
  • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
  • H01L21/76243—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques

Definitions

• the present invention relates generally to integrated circuits, and more particularly to the manufacture of a device of silicon on insulator type (“Silicon on Insulate (SOI)”) comprising a layer of semiconductor material on a layer of material insulating.
• SOI silicon on Insulate
• SOI type devices are more particularly intended to be used to produce devices of the fully depleted type of charge carrier in the channel area also called “fully depleted” devices, in which the thickness of the semiconductor substrate containing silicon , also called active layer, defines among other things the threshold voltage of MOS type transistors and is of great importance.
• a major difficulty in using "fully depleted” assemblies is the production of thin layers of semiconductor substrate containing silicon on a layer of insulating material with good control and sufficient reproducibility of the thickness of this layer. active between two different manufacturing batches.
• "fully depleted" structures would require active layers with a thickness of the order of 5 to 30 nanometers depending on the threshold voltage that is to be obtained and the dimensions of the gates of the transistors.
• the ideal thickness of silicon is of the order of 15 nm for a threshold voltage of approximately 0.35 volts. Any defect in the flatness of the active layer as well as any difference in thickness of the active layer between two manufacturing batches leads to a corresponding variation in the threshold voltage. In general, on the same active layer, the flatness defect is small (of the order of a few%), but from one batch to another, the difference in thickness can be much greater.
• a first method of manufacturing SOI type devices consists in forming a layer of
• this method due to the fact that the thicknesses of the silicon layers and of the silicon oxide layers buried are determined by the implantation process, that is to say a massive implantation of oxygen under high energy and at a dose high, it is difficult to achieve thicknesses of less than 50 nm for the thin layer of residual silicon.
• a second process known under the name of the "BESOI technique” consists in forming an SOI type device by forming on a surface of a first silicon substrate a thin film of SiO 2, then in joining this first substrate, by the thin film of Si ⁇ 2, to a second silicon substrate and finally to eliminate by grinding and mechanical polishing part of one of the silicon substrates to form a thin layer of silicon above the layer of silicon oxide buried .
• the silicon oxide layer on the first silicon substrate is formed by a succession of steps which are: the oxidation of the surface of this first substrate followed by an attack on the oxide layer formed to obtain the desired thickness.
• This process only allows layers of silicon oxide buried and layers of silicon on the silicon oxide buried relatively thick due to poor control of the etching process.
• the thin layers obtained by this process have poor uniformity following the use of mechanical steps which generally generate a relief on the surface of the active layer.
• a third process known under the name of "SMARTCUT Technology” consists in forming by oxidation on a first silicon substrate, a thin layer of silicon oxide and then in implanting, under the thin layer of silicon oxide, H ions in this first silicon substrate to form, within the latter, a plane of cavities.
• This first substrate is then joined, by the thin layer of silicon oxide, to a second substrate of previously oxidized silicon.
• the assembly thus formed is then subjected to a heat treatment which aims to transform the plane of cavities into a cutting plane.
• This process makes it possible to recover on the one hand an SOI assembly and, on the other hand, a reusable silicon substrate.
• This process requires the implantation of a high dose of hydrogen atoms.
• the surface of the thin silicon layer obtained is also damaged.
• the use of this technique generally does not make it possible to obtain thicknesses of thin layer of silicon of less than approximately 50 nm.
• the thickness of the active silicon layer formed is determined by the implantation of the hydrogen allowing the cutting of the initial substrate and then the final polishing of this layer.
• the flatness defect generated by this process is approximately 5 nm whatever the thickness of the final layer.
• the variation in thickness from one plate to another can be of the order of 25% to 40% of the average thickness of a batch of plates, for example for nominal thicknesses less than 50 nm ce which constitutes a significant handicap when making complex circuits due to the difference in threshold voltage resulting from the difference in thickness.
• the present invention provides a method for manufacturing an SOI assembly which makes it possible to obtain semiconductor substrates containing silicon, resting on a layer of insulating material, very thin, including for thicknesses of insulated semiconductor less at 50 nm, of very good uniformity and having very good reproducibility from an SOI type device comprising a layer of semiconductor material on a layer of insulating material.
• this method of manufacturing a device of silicon on insulator (SOI) type comprising a layer of semiconductor material on a layer of insulating material comprises:
• a first phase comprising the following stages: a) formation in the upper part of a first initial semiconductor substrate of a first layer of insulating material above a cutting plane of this first substrate, b) contact of the first layer of insulating material with the insulating upper part of a second initial substrate, so as to form a layer of single insulating material, c) cut at the cutting plane, so as to obtain a semiconductor substrate intermediate on the layer of single insulating material and then
• a second phase comprising the formation in the intermediate semiconductor substrate of a layer of additional insulating material adjoining the layer of single insulating material and surmounted by an upper layer of final semiconductor substrate.
• the cutting plane can be formed before or after the first layer of insulating material.
• This first layer of insulating material can in particular be formed by oxidation, nitriding, or deposition.
• the second initial substrate can be of any electrical nature. If it is insulating, for example made of glass, it will therefore not be necessary to form an insulating upper part. If the second initial substrate is semiconductor, the insulating upper part may in particular be formed by oxidation, nitriding or deposition.
• One of the advantages of the proposed method is that the implantation of the species used to generate the layer of additional insulating material adjoining the layer of single insulating material makes it possible to position with great precision, and in a completely reproducible manner, the desired species with respect to the entry surface of the ion beam in the intermediate semiconductor substrate.
• the only variation generated by this process is a variation in positioning of the implanted species which depends only on the implanted species and the energy used during implantation.
• the position of the species implanted in the intermediate semiconductor substrate therefore does not depend on the thickness of this substrate, but only on the implantation energy for a given species to be implanted.
• the implantation energy being relatively simple to control, it thus becomes extremely easy to control the implantation depth of the ionic species.
• the reproducibility of the process comes from the fact that all the implantations, for a given species and for a given energy, will take place at the same depth, which makes it possible to obtain an upper layer of perfectly reproducible final semiconductor substrate, whatever or the difference in thickness of the intermediate semiconductor substrates of different initial SOI type devices subject to implantation.
• This technique therefore offers an improvement in the control of the thickness of the active layer with remarkable reproducibility and extreme reliability.
• the invention is also remarkable in that it uses in the first phase a phase of the “SMARTCUT technology” type, and that it makes it possible to remedy the main drawback of this technique (inability to obtain particularly thin thicknesses of the substrate of silicon and significant dispersion of the thicknesses obtained) by combining it with the second phase of formation of an additional insulating layer.
• the formation in the intermediate semiconductor substrate of this layer of additional insulating material is carried out using an implantation of oxygen and / or nitrogen in the intermediate semiconductor substrate, followed by treatment thermal.
• the implantation of oxygen and / or nitrogen is carried out with an energy greater than 2 keN.
• the implantation of oxygen and / or nitrogen is carried out at doses of between 10 16 atoms / cm 2 and 10 20 atoms / cm 2 .
• the thickness of the layer of final semiconductor substrate is greater than 5 nm and is more particularly between 5 nm and 30 nm.
• the layer of additional insulating material comprises silicon oxide and / or silicon nitride.
• the first. initial semiconductor substrate comprises pure monocrystalline silicon, germanium, silicon and germanium alloys of the Si ⁇ _ ⁇ Ge ⁇ type (0 ⁇ x ⁇ l) or silicon and germanium alloys containing carbon of the Sii type Ge C (0 ⁇ x ⁇ 0.95 and 0 ⁇ y ⁇ 0.95).
• the invention also relates to an integrated circuit comprising an SOI type device obtained by the method described above.
• This electronic circuit can comprise at least one electronic component chosen from the following list: capacitor, transistor, power diode or high voltage.
• FIGS. 1 to 10 are views in cross section of the SOI type device during the first phase of an implementation of the method of the invention; - Figures 3 to 10 are cross-sectional views of the SOI type device during the second phase of an implementation of the method of the invention.
• FIG. 1 shows a first initial semiconductor substrate 0.
• This first initial semiconductor substrate can comprise any type of semiconductor material, and can in particular comprise monocrystalline silicon, germanium, alloys, silicon alloys
• Sii j. " ⁇ - ⁇ -Ge ⁇ ⁇ (0 ⁇ x ⁇ l) or silicon alloys Sii x ⁇ ⁇ _-.-, y-Ge ⁇ -. C, y, (0 ⁇ x ⁇ 0.95 and
• a section plane is formed, for example by implantation of H + ions, shown in dotted lines in the figure, and defining a layer 1 of the first initial semiconductor substrate 0. upper part of the first initial semiconductor substrate 0 to form a first layer of insulating material 3a above the cutting plane.
• the upper part of a second initial semiconductor substrate 5 is likewise oxidized to form a second layer of insulating material 3b.
• the two initial semiconductor substrates are then brought into contact with their layer of insulating material 3a and 3b to form a layer of single insulating material, as illustrated in FIG. 2.
• FIG. 3 illustrates the SOI type device at the end of the first phase of the process.
• This device comprises the intermediate semiconductor substrate 1 on the layer of single insulating material 3, which rests on the second initial semiconductor substrate 5.
• the first phase of the process is therefore a phase of the "SMARTCUT technology" type.
• FIG. 4 also illustrates an SOI type device at the end of the first phase of the method, the device comprising the semi-substrate intermediate conductor 2 on the layer of single insulating material 4, which rests on the second initial semiconductor substrate 6.
• the devices of FIGS. 3 and 4 although obtained by the same first phase of the process, have different thicknesses of the intermediate semiconductor substrates 1 and 2.
• the difference in thickness between the intermediate semiconductor substrates 1 and 2 is represented in the figures by the distance ⁇ .
• an implantation of the species used to generate the layer of additional insulating material is carried out within the intermediate semiconductor substrates 1 and 2, the species being chosen from oxygen and / or nitrogen.
• Figures 5 and 6 show the profile of the implantation peaks 7 and 8 of the desired species within the intermediate semiconductor substrates 1 and 2. These implantation peaks 7 and 8 are positioned according to the method at the same depth x in the substrate and this, whatever the thickness of the intermediate semiconductor substrates 1 and 2. The peaks 7 and 8 are therefore located in the substrates 1 and 2 at a difference in depth ⁇ relative to the layers of material single insulator 3 and 4. These implantations of nitrogen and / or oxygen atoms are preferably carried out for doses of between 10 1 f. atoms / cm 9 and 1090 n atoms / c at an energy greater than 2 keN.
• the lowest energy is used for thicknesses of the semiconductor substrate thick on the order of 50 nm and can reach several hundred keN for thicknesses on the order of 500 nm. These relatively large doses and these energies also make it possible to precisely position the implantation peaks 7 and 8 in the intermediate semiconductor substrates 1 and 2.
• the implanted species is activated so as to create a layer of additional insulating material by reaction of the implanted species on the species composing the substrates 1 and 2.
• the implanted species is oxygen and / or nitrogen.
• the layer of additional insulating material thus formed will therefore consist of silicon oxide and / or silicon nitride.
• the activation step will include a heat treatment of the assembly thus formed.
• Figures 7 and 8 show the profile of the layers of additional insulating material 9 and 10 obtained after the heat treatment.
• the heat treatment makes it possible to obtain the formation in the intermediate semiconductor substrates 1 and 2 of layers of additional insulating material 9 and 10.
• These layers of additional insulating material 9 and 10 are produced in the same way and with identical implantation parameters. , they are therefore formed at the same depth P in the intermediate semiconductor substrates 1 and 2.
• FIGS. 9 and 10 show a cross-sectional view of the SOI type devices obtained at the end of the second phase of the process and show the final semiconductor substrates 11 and 12 formed from the initial semiconductor substrates 1 and 2, these final semiconductor substrates 11 and 12 being of thickness P greater than 5 nm, and preferably between 5 nm and 30 nm, said final semiconductor substrates 11 and 12 having the same thickness P for the two assemblies used.
• Two SOI type devices are thus obtained, each comprising a final semiconductor substrate, respectively 11 and 12, and preferably consisting of silicon, resting on a layer of insulating material, respectively 13 and 14, said layer of insulating material being composed of the layer of single insulating material, respectively 3 and 4, and of the layer of additional insulating material, respectively 7 and 8, the two assemblies having the same thickness P of final semiconductor substrate, respectively 11 and 12.
• the substrates thus obtained are therefore perfectly reproducible and particularly suitable for use for the production of "fully depleted” devices.

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• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
• Thin Film Transistor (AREA)

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  • 2000-06-23 FR FR0008094A patent/FR2810793B1/fr not_active Expired - Fee Related
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