EP4302328A1 - Module électronique comprenant un support de circuit, une puce semi-conductrice et un dissipateur thermique - Google Patents

Module électronique comprenant un support de circuit, une puce semi-conductrice et un dissipateur thermique

Info

Publication number
EP4302328A1
EP4302328A1 EP22723578.5A EP22723578A EP4302328A1 EP 4302328 A1 EP4302328 A1 EP 4302328A1 EP 22723578 A EP22723578 A EP 22723578A EP 4302328 A1 EP4302328 A1 EP 4302328A1
Authority
EP
European Patent Office
Prior art keywords
circuit carrier
electronics assembly
heat sink
thick
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22723578.5A
Other languages
German (de)
English (en)
Inventor
Wolfgang Feil
Stefan Kiefl
Karl-Heinz Schaller
Stefan Stegmeier
Heinz WÖLLMER
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of EP4302328A1 publication Critical patent/EP4302328A1/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3672—Foil-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/071—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other

Definitions

  • the present invention relates to an electronic assembly with at least one circuit carrier, at least one semiconductor chip and at least one heat sink, the electronic assembly being provided for installation in a superordinate designated device. Furthermore, the invention relates to a device with such an electronic construction group.
  • a heat sink is connected over a large area to a flat circuit carrier, and the circuit carrier is in turn connected flat on its opposite side to the semiconductor chips mounted on it.
  • the main surfaces of the heat sink, circuit carrier and semiconductor chip are parallel to one another, and there is a main heat dissipation path that is perpendicular to these main surfaces.
  • One advantage of this conventional horizontal structure is that the surface connection of the semiconductor chip to the circuit board and from the circuit board to the heat sink means that an effective Ver heat transfer can be realized, and with a correspondingly small thickness and large area of the circuit carrier and an effective heat conduction through this is gege ben. At the same time, a good breakdown strength can be achieved.
  • the total installation space available is limited. For example, only a limited number of slots, each with a limited size, are available in a control cabinet for the installation of such assemblies. Especially in the case of devices with electronic power assemblies, it is difficult to achieve reliable heat dissipation while still keeping the installation space small, since the performance of such assemblies and thus the heat released is increasing.
  • the object of the invention is therefore to specify an electronic assembly which overcomes the disadvantage mentioned.
  • an electronic module is to be made available which requires comparatively little space within the installation level of a higher-level device and which can nevertheless be effectively cooled.
  • a wide- re task is to specify a higher-level device with such an electronic assembly.
  • the electronic assembly according to the invention has a circuit carrier, at least one semiconductor chip and at least one heat sink. It has a flat basic shape with a main level and is intended in particular for installation in a superordinate device.
  • the at least one circuit carrier is essentially oriented parallel to the main plane and carries one or more semiconductor chips to which it is connected over a large area.
  • At least one heat sink is arranged in a first edge region of the planar electronics assembly.
  • the at least one circuit carrier has at least one thick-film conductor track between the region of the at least one semiconductor chip and the first edge region, which is part of a main cooling path that runs essentially parallel to the main plane of the electronic assembly.
  • the electronics assembly comprises a plurality of circuit carriers
  • all the circuit carriers present should in particular be oriented parallel to the main plane.
  • the semiconductor chips that are connected over an area to the respective circuit carrier are then also oriented parallel to this main plane.
  • the at least one heat sink is arranged in an edge area of this multi-layer structure. The mediated by the heat sink dissipation of heat to the external environment takes place predominantly in this first edge area and not on the entire surface of the building group. It should not be ruled out that parts of the heat sink could spread over a larger part of the surface. surface of the assembly.
  • the sub-elements relevant for the all-clear signal to the external environment e.g. cooling ribs, cooling webs, cooling fins, cooling needles or comparable structures
  • the main heat dissipation path mentioned is formed within the assembly group. It is essential in connection with the present invention that this main heat dissipation path lies essentially parallel to the main plane of the assembly and not, as in the prior art described, perpendicular to the layer structure. Said main heat dissipation path can also be made up of a number of sub-paths, in particular if the assembly has a number of semiconductor chips, from which the heat has to be passed on to a common heat sink in each case. However, the partial paths assigned to the respective semiconductor chips can then lead to a common heat dissipation path.
  • this common heat dissipation path mainly runs within the main level of the assembly. Furthermore, it should not be ruled out in this context that the individual partial paths (in the area next to the semiconductor chips) and also the common heat dissipation path formed from them have smaller local partial sections with a heat flow direction that is perpendicular to the main plane.
  • the primary direction of heat dissipation i.e. the net transport direction for the heat dissipated
  • the primary direction of heat dissipation is characterized by an overall predominant directional component within the main plane mentioned. A small angle in the net transport direction and the main plane of up to 10°, for example, should in principle not be ruled out.
  • a thick-film conductor track should generally be understood to mean a conductor track that has a layer thickness of at least 300 ⁇ m.
  • the layer thickness is the dimension of the conductor track perpendicular to the main plane.
  • such a layer thickness can be above 1 mm, for example in an advantageous range between 1 mm and 4 mm.
  • This thick-film conductor track can in particular be formed from a metallic material, for example copper, aluminum, molybdenum or an alloy of one or more of the metals mentioned. In general, a copper-based thick-film conductor track is particularly preferred.
  • each of the existing semiconductor chips is connected to an assigned heat sink via such a thick-film conductor track.
  • a thermal conduction path is provided by this associated thick-film conductor track, which thermally conductively connects the region of the respective semiconductor chip to the region of the associated heat sink and lies parallel to the main plane (namely in the plane of the respective circuit carrier). Due to the particularly high layer thickness of this conductor track, effective heat transport is achieved within the main plane, so that the heat generated in the area of the semiconductor chip can be effectively passed on to the first edge area and can be released from there by the heat sink to the outside environment.
  • thick-film conductor tracks there can be a total of several such thick-film conductor tracks in the assembly. In addition to their function as a heat path, these thick-film conductor tracks can also be used for an electrical connection of the respective semiconductor chip. However, this is not mandatory. This theoretically possible dual functionality can be used either for all or for just a part of the existing thick-film conductor tracks - depending on the requirements for the electrical connection. But at least it is advantageously fulfilled one of the existing circuit carriers has a dual function in that it provides both the electrical connection and the all-clear for the associated semiconductor chip.
  • An essential advantage of the configuration according to the invention is that due to the heat dissipation path lying within the main plane, installation in a higher-level device is made possible, in which case the electronic assembly protrudes from a base support of the device.
  • the main plane of the electronics assembly is then not oriented parallel to an installation plane of the device, as in the prior art, but extends away from the associated installation location, in particular at a vertical or oblique angle.
  • Due to the heat dissipation path lying within the plane of the assembly group effective heat dissipation is made possible in this arrangement, specifically by a heat sink which is located in particular in an edge region of the assembly remote from the installation location.
  • the device according to the invention has a base support and one or more electronic assemblies according to the invention.
  • An installation level is defined by the base support, a sub-area of which is designed as an installation space for the respective associated electronics assembly.
  • the respective electronics assembly stands out from the base support in such a way that the main plane of the electronics assembly forms an angle of at least 30° to the installation plane of the base support.
  • the respective electronic assembly is essentially chen vertically from the base support.
  • the heat sink can in particular form a heat dissipation surface which is oriented at an angle of at least 30° to the first main surface.
  • this heat dissipation surface is essentially perpendicular to the main plane of the assembly.
  • this heat dissipation surface is not to be understood as meaning a planar surface of the heat sink, but rather an envelope through which the heat flow dissipated to the environment passes perpendicularly.
  • the heat sink is not just designed, but has surface-enlarging structures, such as cooling ribs, cooling webs, cooling fins, cooling needles or the like, in order to improve heat dissipation to the environment.
  • the heat sink can have a plurality of cooling ribs, which in particular extend parallel to the main plane of the assembly and thus conduct the heat even further in the direction of the main heat dissipation path.
  • the cooling body can also be designed as a cooling star with oblique and in particular branched cooling structures.
  • the electronics assembly can be designed as a power electronics assembly.
  • at least one of the existing semiconductor chips is in the form of a high-performance electronic component.
  • a power diode and/or an IGBT a bipolar transistor with an insulated gate electrode
  • IGBT a bipolar transistor with an insulated gate electrode
  • the electronics module can have a plurality of semiconductor chips that are arranged on the same circuit carrier. These semiconductor chips can be arranged next to one another or one behind the other with respect to the main heat dissipation path, with combinations of these two variants of the arrangement also being possible.
  • a plurality of such semiconductor chips can optionally also be electrically connected to one another by the associated thick-film conductor track.
  • a common emitter circuit can be implemented between a power diode and an IGBT.
  • a number of components can also be electrically connected to one another in the manner of a half bridge or a full bridge by one or more thick-film conductor tracks, with a common heat dissipation path being formed at the same time.
  • the at least one thick-film conductor track is generally advantageously thermally coupled to the associated heat sink.
  • this thermal coupling is designed in such a way that between the respective semiconductor chip and the associated heat sink, the heat dissipation path that predominates overall runs via the associated thick-film conductor track.
  • the thermal connection of at least one of the existing thick-film conductor tracks to the heat sink is mediated by a large-area insulation layer.
  • “Large area” should be understood to mean an insulation layer that has an area that is at least as large as the area of the associated thick-film conductor track.
  • the area of a thick-film conductor track can generally be above 1 cm 2 , for example, in particular in the range of at least 5 cm 2 .
  • the width of a thick film conductive line can generally be 1 cm or more. With this dimensioning, a particularly effective heat transport to the heat sink is advantageously ensured.
  • the layer thickness can be less than 1 mm, in particular in a range between 25 ⁇ m and 500 ⁇ m. High dielectric strengths can be achieved with such layer thicknesses. Due to the comparatively large area, an effective thermal coupling can be achieved at the same time, despite the typically rather low thermal conductivity of electrically insulating materials. Suitable materials for such an electrically insulating coupling layer are generally organic polymers, in particular polyimides or epoxides, which can optionally also have fillers made from other materials, in particular ceramic fillers to set a desired thermal expansion coefficient.
  • such a large-area insulation layer can be arranged, for example, between a thick-film conductor track of a circuit carrier and a flat side element of a heat sink.
  • such a large-area insulation layer can also lie within a circuit carrier in order to achieve electrical decoupling between two thick-film conductor tracks lying one on top of the other. Then one of these thick film conductive lines can be connected to the semiconductor chip and the other can be connected to the heatsink, with the insula ons slaughter an electrical insulation between the heatsink and the semiconductor chip is achieved, with nevertheless comparatively good thermal coupling due to the large area and the small layer thickness of the insulating layer.
  • the at least one circuit carrier can thus comprise a plastic-based dielectric layer.
  • This can in particular be an internal layer of a multi-layer circuit carrier, which is sandwiched between electrically conductive layers and in particular thick-layer conductor tracks.
  • a circuit carrier with a polyimide-based dielectric layer is available, for example, from Dupont under the name ODBC (for "organic direct-bond copper" substrate).
  • Dielectric layers have the advantage that the organic layer can compensate for mechanical stresses much better than a ceramic layer due to the thick conductor tracks ruptures or cracks in the circuit carrier.
  • the dielectric layer does not have to consist exclusively of an organic plastic, but can advantageously be based on such a material. It can in particular consist of a composite material made of an organic polymer and one or more other components.
  • the at least one circuit carrier can also be formed by a metallic leadframe.
  • a metallic leadframe can again particularly preferably be a copper-based leadframe.
  • a leadframe is understood to mean what is known as a connecting frame, ie a solderable metallic conductor carrier in the form of a frame or comb.
  • the structure of such a leadframe can be produced in particular by stamping or laser processing.
  • the leadframe can re have a flat connection area for the respective semiconductor chip and a further flat connection area for the further thermal connection to the associated heat sink.
  • thick conductor tracks are also present here in the form of the individual webs, which, in addition to the electrical connection, also cause cooling of the associated semiconductor chip with a cooling path within the assembly level.
  • such a leadframe can also be provided with a corresponding electrically insulating layer, at least in the area of the connection point for the heat sink.
  • the at least one semiconductor chip can generally advantageously be connected flat on a first surface to a first circuit carrier and be connected flat on a second, opposite surface to a second circuit carrier or to a metal sheet.
  • the circuit carrier is then embedded in the manner of a sandwich between two thermally conductive structures, each of which brings about heat dissipation with a main heat dissipation direction within the assembly level.
  • This embodiment therefore achieves particularly effective cooling of the semiconductor chip on both sides, with the heat being transported on on both sides parallel to the chip plane.
  • several such semi-conductor chips can be sandwiched between two such heat-conducting elements in a corresponding manner.
  • the distance between the first circuit carrier and the second circuit carrier or the metal sheet is little least 5 gm.
  • This distance can particularly advantageously be in a range between 25 gm and 400 gm. This distance is high enough to ensure a sufficiently high dielectric strength between the opposing metallic elements and low enough to enable sufficiently good thermal coupling of the semiconductor chip on both sides.
  • the space between the first circuit carrier and the second circuit carrier or the metallic sheet metal is filled with an electrically insulating filler.
  • an electrically insulating filler is filled with an electrically insulating filler.
  • Materials that can be used advantageously here are silicone-based materials, typical underfill materials and molding compounds such as Globtop.
  • such a polymer material can in turn be filled with a filler in order to set a predetermined value for the thermal expansion coefficient and in this way to keep thermally induced stresses between the semiconductor chip and the circuit carriers or the metal sheet advantageously low.
  • At least one internal circuit carrier can be connected over a large area on each of its main surfaces to one or more associated semiconductor chips.
  • a sandwich-like structure also results with regard to the internal circuit carrier.
  • This embodiment can be combined particularly advantageously with the previous one, so that there are two levels of semiconductor chips, which are each cooled on both sides (by a common circuit carrier lying on the inside and a separate circuit carrier lying on the outside).
  • This Big Mac-like structure made up of a total of At least five layers can be constructed in particular essentially symmetrically with respect to the internal circuit carrier.
  • the internal circuit carrier thickens in its cross-section in the direction of the first edge region of the electronic assembly.
  • the thermal connection of the internal circuit carrier to the heat sink located there can be further improved.
  • the internal circuit carrier can have a T-shaped profile, with the thermal connection to the heat sink being realized in the area of the crossbar of the T-profile.
  • the heat sink can be divided into at least two mechanically separate partial elements.
  • the dividing line between these partial elements can in particular run centrally through the main plane of the assembly.
  • each half of the sandwich can then be assigned its own partial element of the cooling body. In this way, thermally induced mechanical stresses in the area of the heat sink (or between it and the adjacent elements) can be effectively reduced.
  • the heat sink can be divided into a head element and a further element with two side parts, the head element being arranged in the first edge region and the side parts extending parallel to the main plane and to a certain extent enveloping the other elements of the layered structure.
  • the term structure and thedekör pers can also be a gap between the heat sink and the at least one thick-film conductor track can be filled with a filling material.
  • a filling material for example using metal foams as a filler, using springs between the individual elements, as well as branches between the individual thick-film conductor tracks or the formation of a stack in which the total thickness of a thick-film conductor track is made up of several sub-layers.
  • the base support can run parallel to the rear wall of a switch cabinet or can also be provided by this rear wall itself.
  • the device can be a switching device and/or a control device, which can be designed in particular for controlling an electric drive.
  • it can be a control device for an industrial application, in particular for an industrial production plant, which has one or more electronic construction groups according to the invention.
  • the individual electronic assemblies can at least in part preferably be power modules which are provided for modular installation in the installation level of the device, for example converter modules.
  • the respective electronics module can have corresponding connecting elements, for example plug-in pins for plugging into a slot on the base support.
  • the superordinate device can optionally also have a cooling device, a housing and/or one or more busbars.
  • FIG. 1 shows a schematic sectional view of an electronics assembly according to the prior art
  • FIG. 2 shows an electronic assembly according to a first example of the invention in a schematic longitudinal section
  • Figure 3 shows a top view of an inner thick film conductor track of Figure 2;
  • FIGS 4 and 5 show schematic longitudinal sections of electronic assemblies according to further examples of the invention
  • Figure 6 shows a top view of the third circuit carrier of Figure 5 and
  • FIGS 7 to 9 show further variants for the structure of the heat sink pers in such electronic assemblies.
  • FIG. 1 shows a schematic sectional view of an electronic assembly according to the prior art, which is typical of the basic structure of common power electronic assemblies.
  • two semiconductor chips 20 are connected over the entire area to a circuit carrier 10 and cast on their outside with a casting compound 25 .
  • the circuit carrier 10 is connected on its opposite main surface to a heat sink 30, which has cooling fins for dissipating heat to the outside environment.
  • a flat electronic construction group 1 is given overall, the main level of which lies within the xy plane here.
  • the direction of the main heat dissipation path H is perpendicular to this plane, ie in the z-direction.
  • such a subassembly In order to ensure heat dissipation on a side that is exposed to the outside, such a subassembly according to the prior art is installed flat in a mounting location 110 of a superordinate device.
  • the installation plane is then also within the xy plane, and the main cooling path H is oriented essentially perpendicularly to the installation plane.
  • the size of the installation space required is typically even even larger than the lateral dimensions of the elements shown here, because additional space must usually be provided within the xy plane for the load connections and control lines, which are not shown here for the sake of clarity. Overall, such a hori zontal electronic module requires a lot of space within the installation level of a higher-level device.
  • FIG. 2 shows an electronic assembly 1 according to a first example of the invention.
  • a schematic longitudinal section is shown, which runs perpendicularly to a main plane P of the electronics assembly, which is designed to be flat.
  • the electronics assembly shown includes three circuit carriers 10a, 10b and 10c, which are each parallel to the main plane P with their main surfaces. They are sandwiched one on top of the other.
  • the two outer circuit carriers 10a and 10c are each fitted with two semiconductor chips, namely in this example each with a power diode 21 and an IGBT 22.
  • the two outer circuit carriers 10a and 10c are formed from multilayer thick copper substrates in this example. They therefore have thick-film conductor tracks 11 and 13 made of copper, although in principle other metallic materials can also be used for the thick-film conductor tracks.
  • each of the two circuit carriers 10a and 10c has an inner 11 and an outer thick-film layer 13 and an organic dielectric layer 12 in between.
  • the two semiconductor chips 21, 22 on each circuit carrier 10a and 10c are therefore arranged on an internal thick-film conductor track 11 and connected to it, for example, by soldering, sintering, diffusion soldering or gluing. As a result, an electrical contact is established on the one hand and a thermal connection is mediated on the other.
  • the power diode 21 and the associated IGBT 22 are connected by the respective inner thick-film conductor track 11 according to Art connected to a common emitter circuit.
  • the remaining contacts of the IGBT are connected to associated connection elements 22b, two of which are arranged one behind the other in the y-direction (not shown here) and which can be designed as pins for plugging into a higher-level device.
  • the second contact of the respective power diode 21 is connected via a connecting element 21a to a central thick-film conductor track 16 of the internal second circuit carrier 10b.
  • the IGBTs 22 are also coupled to the central thick-film conductor track 16 via associated connecting elements 22a.
  • all four semiconductor chips 20, 21 are thermally coupled to the parallel to the main plane P running thick film interconnects 11 and 16 mixed.
  • the inner thick-film conductor tracks 11 are in turn thermally coupled to the respective outer thick-film conductor track 13 via the thin dielek tric layer of the respective circuit carrier.
  • a heat sink 30 is arranged in this first edge region RI.
  • This heat sink has, for example, a plurality of cooling fins that also run parallel to the main plane.
  • the (enveloping) outer surface of the heat sink represents a heat dissipation surface E, through which a main heat dissipation path H passes for the dissipation of heat to the external environment. Overall, this main heat dissipation path is essentially parallel to the main plane P of the assembly.
  • the electronics assembly can be installed upright, ie with a connection in its narrow second edge region R2, in a superordinate device.
  • a part of a base support 100 is shown only extremely schematically in FIG.
  • the described upright arrangement means that the mounting space 110 within the mounting plane G running in the xy plane requires only a relatively small lateral area.
  • the connection to the base support 100 can be achieved, for example, by plugging in the pins 22b.
  • a plurality of semiconductor chips 21, 22 are embedded between a total of three circuit carriers 10a, 10b, 10c in the manner of a multilayer sandwich.
  • this is not absolutely necessary in order to realize the advantages of the invention.
  • the only important thing is that, at least for a semiconductor chip with at least one thick-film conductor track of an associated circuit carrier, heat is transported parallel to the assembly level and thus away from the mounting location 110 in the higher-level device.
  • the sandwich-like structure in the example of Figure 2 has the advantage that the individual semiconductor chips due to their double-sided coupling to the adjacent thick-film conductor tracks 11, 16 can be given the warning even more effectively.
  • the distance d between these opposing thick-film conductor tracks 11 and 16 is advantageously at least 10 mpi, so that voltage flashovers are avoided.
  • the intermediate space formed can optionally be filled with an electrically insulating filler, which is not shown here.
  • FIG. 3 shows a schematic top view of one of the inner thick-film conductor tracks 11 from the example in FIG. 2 with the power diode 21 arranged thereon and the IGBT 22 .
  • the position of the associated connection elements 21a, 22a for connection to the central thick-film conductor track and the additional connection elements 22b of the IGBT are indicated.
  • the section line II-II corresponds to the position of the cross section in FIG. 2.
  • the two semiconductor chips 21, 22 are arranged next to one another in the z-direction, so that they lie one behind the other with respect to the main heat dissipation path.
  • FIG. 4 shows an electronic assembly 1 according to a further example of the invention in a schematic longitudinal section.
  • the basic arrangement of the semiconductor chips 21, 22 and their embedding between a total of three circuit carriers 10a, 10b, 10c is similar to the example in FIG
  • the two circuit carriers 10a and 10c on the outside are essentially formed here by the material of the thick-film conductor tracks 11 . They can therefore be configured as copper leadframes, for example.
  • the heat sink has two flat side parts 30b, which extend parallel to the thick-film conductor tracks 11, in addition to the head part 30a largely adopted from FIG.
  • the heat transport between the thick-film conductor tracks 11 and the side parts 30b of the heat sink is mediated here by an insulating layer 40, so that the heat sink is electrically insulated from the conductor tracks. Due to the large area and the low layer thickness of the insulating layer 40 is still a good thermal connection to the side elements of the heat sink and thus in turn an effective main heat dissipation path H parallel to the main plane P of the construction group achieved.
  • FIG. 5 shows an electronic assembly 1 according to a further example of the invention in a schematic longitudinal section.
  • the layer structure of the assembly and also the structure of the heat sink are similar to the previous example in Figure 4.
  • each of the two circuit carriers 10a and 10c is equipped with a power diode 21 and an IGBT 22, although these two components are in are arranged adjacent to each other in the y-direction (not shown), so that only one component per circuit carrier is visible in the sectional view of FIG.
  • the top view of FIG. 6 illustrates how the two components 21 and 22 are arranged next to one another on the respective circuit carrier (here, for example, the third circuit carrier 10c) with respect to the main heat dissipation direction z.
  • FIG. 7 shows an electronic assembly 1 according to a further example of the invention in a schematic longitudinal section.
  • the structure is largely similar to that in the example in FIG is composed.
  • the two sub-elements are connected via a coupling layer 50, which lies in the yz plane and is suitable for reducing thermally induced mechanical stresses between the two sub-elements.
  • FIG. 8 shows an electronic assembly 1 according to a further example of the invention in a schematic longitudinal section.
  • the structure is largely similar to that in the example in FIGS. 5 and 6.
  • the heat sink is composed of two partial elements 31a and 31b.
  • the internal second circuit carrier is not widened quite as much in a T-shape in the direction of the head part of the heat sink, but is only slightly thickened here towards the edge region RI.
  • the two partial elements of the heat sink therefore each have an additional step in this area.
  • FIG. 9 shows an electronic assembly 1 according to a further example of the invention in a schematic longitudinal section.
  • the structure is largely similar to the example in Figures 5 and 6.
  • the structure of the heat sink is varied in such a way that there is an additional division into a head part 30a and a separate part element 30c, with the part element 30c having a U -shaped cross-sectional profile and wraps the other elements of the layered structure.
  • the thermally conductive connection between the sub-element 30c and the head part 30a of the heat sink is realized here by a coupling layer 50 made of a thermally conductive paste.
  • the flat side parts are connected by an insulator layer 40 to the adjacent thick-film conductor tracks.
  • This type of division of the heat sink can also contribute to reducing thermally induced mechanical stresses within the electronic assembly 1.
  • the various shown variants for the arrangement of the semiconductor chips, the structure of the individual circuit carriers and the structure of the heat sink can of course be combined with one another, and the invention is not limited to the exemplary embodiments shown. All examples illustrate the general concept of how a space-saving upright installation in a compact installation space of a superordinate device is made possible by creating an effective heat dissipation path within the assembly level.
  • connection elements pins

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un module électronique (1) comprenant au moins un support de circuit (10a, 10b, 10c), au moins une puce semi-conductrice (20a, 20b) et au moins un dissipateur thermique (30), ledit module électronique (1) ayant une forme de base plane avec un plan principal (P) et étant prévu en particulier pour être monté dans un dispositif supérieur, ledit au moins un support de circuit (10a, 10b, 10c) étant orienté parallèlement au plan principal (P) et portant une ou plusieurs puces semi-conductrices (20a, 20b), à laquelle ou auxquelles il est relié à plat, ledit au moins un dissipateur thermique (30) étant disposé dans une première zone de bord (RI) du module électronique plan (1), et ledit au moins un support de circuit (10a, 10b, 10c) comprenant, entre la zone de ladite au moins une puce semi-conductrice (20a, 20b) et la première zone de bord (RI), au moins une piste conductrice à couche épaisse (11, 13, 16) qui fait partie d'une voie de dissipation de chaleur principale (H) qui s'étend sensiblement parallèlement au plan principal (P). L'invention concerne en outre un dispositif pourvu d'un tel module électronique (1).
EP22723578.5A 2021-04-27 2022-04-19 Module électronique comprenant un support de circuit, une puce semi-conductrice et un dissipateur thermique Pending EP4302328A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP21170578.5A EP4084058A1 (fr) 2021-04-27 2021-04-27 Module électronique pourvu de porte-circuit, de puce à semi-conducteur et de dissipateur thermique
PCT/EP2022/060219 WO2022228930A1 (fr) 2021-04-27 2022-04-19 Module électronique comprenant un support de circuit, une puce semi-conductrice et un dissipateur thermique

Publications (1)

Publication Number Publication Date
EP4302328A1 true EP4302328A1 (fr) 2024-01-10

Family

ID=75728552

Family Applications (2)

Application Number Title Priority Date Filing Date
EP21170578.5A Withdrawn EP4084058A1 (fr) 2021-04-27 2021-04-27 Module électronique pourvu de porte-circuit, de puce à semi-conducteur et de dissipateur thermique
EP22723578.5A Pending EP4302328A1 (fr) 2021-04-27 2022-04-19 Module électronique comprenant un support de circuit, une puce semi-conductrice et un dissipateur thermique

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP21170578.5A Withdrawn EP4084058A1 (fr) 2021-04-27 2021-04-27 Module électronique pourvu de porte-circuit, de puce à semi-conducteur et de dissipateur thermique

Country Status (3)

Country Link
EP (2) EP4084058A1 (fr)
CN (1) CN117203760A (fr)
WO (1) WO2022228930A1 (fr)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6075288A (en) * 1998-06-08 2000-06-13 Micron Technology, Inc. Semiconductor package having interlocking heat sinks and method of fabrication
JP5422466B2 (ja) * 2010-04-01 2014-02-19 日立オートモティブシステムズ株式会社 電力変換装置
DE102015216047A1 (de) * 2015-08-21 2017-02-23 Continental Automotive Gmbh Schaltungsträger, Leistungselektronikanordnung mit einem Schaltungsträger
DE102019111366B3 (de) * 2019-05-02 2020-05-14 Fachhochschule Kiel Kompaktes Leistungselektronik-Modul mit vergrößerter Kühlfläche
EP3751602A1 (fr) * 2019-06-11 2020-12-16 Siemens Aktiengesellschaft Substrat métallique isolé pour un groupe électronique de puissance

Also Published As

Publication number Publication date
WO2022228930A1 (fr) 2022-11-03
EP4084058A1 (fr) 2022-11-02
CN117203760A (zh) 2023-12-08

Similar Documents

Publication Publication Date Title
DE19617055C1 (de) Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise
EP0221399B1 (fr) Module semi-conducteur de puissance
EP2308274B1 (fr) Circuit imprimé avec composant électronique
EP2008305A2 (fr) Module composant électronique
DE102014101238A1 (de) In Leiterplatten eingebettetes Leistungsmodul
WO2009132922A2 (fr) Module de circuit à substrat présentant des composants dans plusieurs plans de contact
DE102007005233A1 (de) Leistungsmodul
DE102015224422A1 (de) Elektronische Schaltungseinheit
DE102015108909A1 (de) Anordnung mehrerer Leistungshalbleiterchips und Verfahren zur Herstellung derselben
DE102016214607B4 (de) Elektronisches Modul und Verfahren zu seiner Herstellung
DE212021000482U1 (de) Leistungshalbleitermodul
DE102011078806B4 (de) Herstellungsverfahren für ein leistungselektronisches System mit einer Kühleinrichtung
WO2018001883A1 (fr) Module de puissance
EP2006910B1 (fr) Module électronique de puissance
EP4302328A1 (fr) Module électronique comprenant un support de circuit, une puce semi-conductrice et un dissipateur thermique
DE102016112602A1 (de) Niederinduktives Leistungsmoduldesign
DE102019116021B4 (de) Flexible Leiterplatte mit thermisch leitender Verbindung zu einer Wärmesenke
EP3384527A1 (fr) Module électronique de puissance
EP2887392A2 (fr) Module électronique de puissance et procédé de fabrication d'un module électronique de puissance
DE102014203310A1 (de) Elektronikmodul
EP2964004A2 (fr) Agencement de composant electronique
DE102022113643A1 (de) Elektrisches Modul
DE102021113302A1 (de) Board mit Zinnen
DE102022208367A1 (de) Leistungsmodul
WO2024033302A1 (fr) Ensemble carte de circuit imprimé

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20231005

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR