EP4290751A1 - Dispositif de commande et procédé de commande pour dispositif de conversion de courant - Google Patents

Dispositif de commande et procédé de commande pour dispositif de conversion de courant Download PDF

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Publication number
EP4290751A1
EP4290751A1 EP22749403.6A EP22749403A EP4290751A1 EP 4290751 A1 EP4290751 A1 EP 4290751A1 EP 22749403 A EP22749403 A EP 22749403A EP 4290751 A1 EP4290751 A1 EP 4290751A1
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EP
European Patent Office
Prior art keywords
phase side
fet
side fet
phase
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP22749403.6A
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German (de)
English (en)
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EP4290751A4 (fr
Inventor
Tetsuji Suzuki
Yoshihito Kumamoto
Takanori Wakamatsu
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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Application filed by Meidensha Corp, Meidensha Electric Manufacturing Co Ltd filed Critical Meidensha Corp
Publication of EP4290751A1 publication Critical patent/EP4290751A1/fr
Publication of EP4290751A4 publication Critical patent/EP4290751A4/fr
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters

Definitions

  • the present invention relates to a control device for a power conversion device such as an inverter/converter using power MOSFETs etc. in a main control circuit, which is applied to drive of an electric vehicle such as a battery forklift.
  • the present invention relates to a control device and a control method having FET arm gate drive circuits provided with FETs in upper and lower phase arms and configured to store (accumulate) gate drive energy of the upper phase side FET arms in capacitors of bootstrap circuits and drive the FET gates.
  • FIG. 1 illustrates an overall configuration of an inverter for driving a motor of an electric vehicle having a battery as a power source (power supply).
  • a reference sign 50 is a battery for the power supply.
  • a protective fuse 51, a main contactor (MC) 52 for shutting off the power supply in an abnormal condition and an electrolytic capacitor C21 for smoothing the power supply are connected in series.
  • a charging resistor (a first charging resistor) R1 for charging the electrolytic capacitor 21 with charge (electric charge) with a long time constant is connected.
  • a series circuit of a P-channel charging FET 53 and a charging resistor (a second charging resistor) R3 for charging the electrolytic capacitor C21 with charge with a charging time constant that is shorter than that of the charging resistor R1 is connected to the charging resistor R1 in parallel.
  • a discharging resistor R2 for discharging charge of the electrolytic capacitor C21 when the battery 50 is OFF (when the battery 50 is disconnected) is connected between a common connection point (a positive electrode end P3 of the electrolytic capacitor C21) of the charging resistor R1 and the charging resistor R3 and a negative electrode end (N) of the electrolytic capacitor C21.
  • an inverter 54 (a power conversion unit) in which upper phase side EFTs 54U, 54V and 54W and lower phase side FETs 54X, 54Y and 54Z are three-phase bridge-connected is connected.
  • Each of the FETs 54U, 54V, 54W, 54X, 54Y and 54Z is composed of, for instance, an N-channel MOSFET.
  • a series circuit of a resistor 55U and a resistor 55X is connected to a series circuit of the U-phase FET 54U and the X-phase FET 54X in parallel.
  • a common connection point of the resistor 55U and the resistor 55X is connected to a common connection point of the U-phase FET 54U and the X-phase FET 54X.
  • a series circuit of a resistor 55V and a resistor 55Y is connected to a series circuit of the V-phase FET 54V and the Y-phase FET 54Y in parallel.
  • a common connection point of the resistor 55V and the resistor 55Y is connected to a common connectionpoint of the V-phase FET 54V and the Y-phase FET 54Y.
  • a series circuit of a resistor 55W and a resistor 55Z is connected to a series circuit of the W-phase FET 54W and the Z-phase FET 54Z in parallel.
  • a common connection point of the resistor 55W and the resistor 55Z is connected to a common connection point of the W-phase FET 54W and the Z-phase FET 54Z.
  • AC sides u, v and w of the inverter 54 are connected to a motor 56.
  • Vp4 indicates a voltage dividing point voltage of the resistor 55U and the resistor 55X
  • Vp5 indicates a voltage dividing point voltage of the resistor 55V and the resistor 55Y
  • Vp6 indicates a voltage dividing point voltage of the resistor 55W and the resistor 55Z
  • FIG. 2 illustrates, as an example, a configuration of U-phase and X-phase FET arm gate drive circuits.
  • a reference sign 60 denotes a high withstand voltage IC (or a high voltage IC) (High Voltage Integrated Circuit; hereinafter, referred to as HVIC) for driving gates of the U-phase FET 54U and the X-phase FET 54X.
  • HVIC High Voltage Integrated Circuit
  • a reference sign 62 denotes a level shifter that increases a level of a gate control signal (HIN) of a high side circuit side which is input from a high side input terminal 61H.
  • An internal circuit 63 at the high side is connected to an output side of the level shifter 62.
  • a totem-pole circuit in which two n-channel FETs 64Ha and 64Hb are cascaded (cascade-connected) is connected to an output side of the internal circuit 63.
  • a reference sign 63L denotes an internal circuit at a low side which inputs a gate control signal (LIN) of a low side circuit side which is input from a low side input terminal 61L.
  • a totem-pole circuit in which two n-channel FETs 64La and 64Lb are cascaded (cascade-connected) is connected to an output side of the internal circuit 63L.
  • a resistor 65H is connected between the high side input terminal 61H and a ground (an earth) .
  • a resistor 65L is connected between the low side input terminal 61L and the ground.
  • a reference sign 70 denotes a gate power supply that outputs a gate power supply of, e.g. 14V.
  • a capacitor C31 an upper phase side gate drive power supply capacitor (a bootstrap capacitor)
  • a capacitor C32 a lower phase side gate drive power supply capacitor
  • One end (at the diode D1 side) of the capacitor C31 is connected to a ground side end of the totem-pole circuit configured by the FETs 64Ha and 64Hb.
  • One end (at the diode D2 side) of the capacitor C32 is connected to a ground side end of the totem-pole circuit configured by the FETs 64La and 64Lb and the negative electrode end (N) of the battery 50 (not shown) .
  • An output end (a common connection point of the FETs 64Ha and 64Hb) of the totem-pole circuit configured by the FETs 64Ha and 64Hb is connected to the gate of the U-phase FET 54U via a resistor R11.
  • the ground side end of the totem-pole circuit configured by the FETs 64Ha and 64Hb is connected to a source of the U-phase FET 54U via a resistor R12.
  • a resistor R14 is connected between the gate and the source of the U-phase FET 54U.
  • a cathode of a diode D3 is connected to a common connection point of the ground end of the totem-pole circuit configured by the FETs 64Ha and 64Hb and the resistor R12.
  • An anode of the diode D3 is connected to the negative electrode end (N) of the battery 50 (to the source of the X-phase FET 54X).
  • the battery 50 is configured to be freely connectable and disconnectable.
  • FET arm gate drive circuits for V-phase and Y-phase and FET arm gate drive circuits for W-phase and Z-phase are also configured in the same manner as that in Fig. 2 .
  • the battery 50 is connected, a key switch (not shown) is tuned on and the electrolytic capacitor C21 is charged, and after the main contactor 52 is turned on, drive of the inverter 54 is started. Sequence up to the start of the drive of the inverter 54 will be described below.
  • a path of the battery 50 ⁇ a cable ⁇ the main contactor 52 -> the electrolytic capacitor C21 becomes a circuit composed of LRC by an inductor of the cable, a cable resistance and a battery internal equivalent resistance, as shown in Fig. 3 .
  • gate drive power supply energy is not stored (accumulated) in the upper phase side FET arm gate drive circuit (e.g. the U-phase FET arm gate drive circuit in Fig. 2 ) of the inverter 54. That is, in Fig. 5 showing a relationship between a stray capacitance (or a parasitic capacitance) of each terminal of the U-phase FET 54U and the U-phase FET arm gate drive circuit, since a charge-pump operation (a charging operation of the capacitor C31) has not been performed even once, at this time point, an output of the totem-pole circuit configured by the FETs 64Ha and 64Hb for driving the high side arm in the HVIC 60 is OFF at both of a source side and a sink side.
  • the upper phase side FET arm gate drive circuit e.g. the U-phase FET arm gate drive circuit in Fig. 2
  • a charge-pump operation a charging operation of the capacitor C31
  • Fig. 5 same elements or components as those of Fig. 2 are denoted by the same reference signs, but the diode D3, the resistors R13 and R15, the level shifter 62 and the resistors 65H and 65L in the HVIC 60 in Fig. 2 are omitted.
  • Crss of the U-phase FET 54U indicates a drain-gate capacitance (a feedback capacitance or a reverse transfer capacitance), and Cgs of the U-phase FET 54U indicates a gate-source capacitance (an input capacitance).
  • the high side arm driving FETs 64Ha and 64Hb of the HVIC 60 are in the OFF state. Therefore, if a gate-source voltage Vgs is charged with charge (electric charge) due to noise etc. from the outside in this state, there is no means to prevent malfunction other than the discharge capability of the resistor R14 between the gate and the source of the U-phase FET 54U.
  • the gate drive power supply capacitor C32 is charged by a circuit of the gate power supply 70 -> the diode D2 ⁇ the capacitor C32 ⁇ 0V. This charging is always performed because a continuously charging circuit is configured regardless of ON/OFF of the main circuit FET.
  • either the upper FET or the lower FET (64Ha or 64Hb) of the totem-pole output of the upper phase side FET arm gate drive circuit is turned on or off according to the operation.
  • a drain-source voltage of the lower phase side FET (the X-phase FET 54X) when the lower phase side FET (the X-phase FET 54X) is turned on during the inverter operation abruptly becomes zero volt from a voltage value (Vp4) applied by the voltage dividing resistors (the potential dividing resistors) 55U and 55X of Fig. 1 .
  • Crss the drain-gate capacitance
  • Cgs the gate-source capacitance
  • the above-described gate drive power supply energy (charge voltage of the capacitor C31) of the U-phase FET 54U exists, and regarding the output of the totem-pole circuit configured by the U-phase arm drive FETs 64Ha and 64Hb of the HVIC 60, the output is operated (sink-operated) in an OFF direction in the gate drive circuit. Therefore, the charge (the electric charge) charged in Cgs is discharged to (by or through) the resistor R11 + the resistor R12, then the charge of Cgs is not charged. Thus, the gate-source voltage Vgs does not rise, then the U-phase FET 54U does not shift to ON-operation.
  • Vgs is the above (5).
  • a metal base board (a metal base substrate) whose back surface is a metal plate is used, in addition to these capacitances between the FET terminals, capacitances between the base metal and the terminals affect the characteristics.
  • Batt indicates the battery 50 of Fig. 1
  • C4 indicates the electrolytic capacitor C21 of Fig. 1 .
  • the U-phase FET 54U and the X-phase FET 54X are mounted on the metal base board (the metal base substrate) in parallel by soldering.
  • C1 and C5 are gate-source capacitances of the U-phase FET 54U and the X-phase FET 54X
  • C2 and C6 are drain-gate capacitances of the U-phase FET 54U and the X-phase FET 54X
  • C3 and C7 are output capacitances of the U-phase FET 54U and the X-phase FET 54X.
  • C8 to C12 are capacitances formed by dielectric constant (or permittivity) of an insulating layer(s) between the base metal (aluminium) and patterns, and these capacitances affect the characteristics.
  • the upper phase side FET (the U-phase FET 54U) is turned on (ON-operated), and consequently, the short-circuit current passes through the upper and lower FETs for a short period of time.
  • Fig. 6 showing a flow chart of the conventional process
  • the battery 50 of Fig. 1 is connected to the circuit before step S1.
  • the key switch is turned on.
  • step S2 a judgment is made as to whether or not the voltage of the positive electrode end P3 of the electrolytic capacitor C21 of Fig. 1 is 63V or less. If the judgment result is YES, at step S3, a quick charging process (the charging FET 53 is turned on) is performed.
  • step S4 a judgment is made as to whether or not the voltage of the positive electrode end P3 is 5V or less and also its state continues for 0.6 seconds. If the judgment result of step S4 is YES, at step S5, a predetermined quick charging error process (process in which the main circuit FET (s) of the inverter and the electrolytic capacitor C21 are judged to be short-circuited, and this abnormal state is notified to a host controller (not shown)) is performed.
  • a predetermined quick charging error process process in which the main circuit FET (s) of the inverter and the electrolytic capacitor C21 are judged to be short-circuited, and this abnormal state is notified to a host controller (not shown)
  • step S4 If the judgment result of step S4 is NO or after the process of step S5, at step S6, a judgment is made as to whether or not the voltage of the positive electrode end P3 is 63V or less and also its state continues for 3.6 seconds.
  • step S7 a predetermined quick charging error process (process in which an error state is notified to the host controller (not shown)) is performed.
  • step S8 a judgment is made as to whether or not the voltage of the positive electrode end P3 is 3V or less and also its state continues for 15 seconds.
  • step S9 the upper and lower phase FETs are judged to be short-circuited.
  • step S10 the main contactor 52 of Fig. 1 is turned on, and after the turning-on of the main contactor 52, at step S11, the operation of the inverter 54 is started.
  • the upper and lower phase arms are driven for the first time by the operation of the inverter at step S11, and by turning-on of the lower phase side arm FET (the X-phase FET 54X), the gate drive power supply capacitor (the capacitor C31) of the upper phase side FET arm gate drive circuit is charged with charge (electric charge), then operation of the upper phase arm becomes possible.
  • the lower phase side arm FET the X-phase FET 54X
  • the gate drive power supply capacitor (the capacitor C31) of the upper phase side FET arm gate drive circuit is charged with charge (electric charge), then operation of the upper phase arm becomes possible.
  • Fig. 7 is a time chart showing operation waveform of only a set of upper and lower arms of the U-phase and the X-phase. Capacitances of these U-phase FET and X-phase FET are shown in Fig. 8 .
  • Fig. 8 Batt indicates the battery 50 of Fig. 1
  • C4 indicates the electrolytic capacitor C21 of Fig. 1 .
  • C1 indicates the gate-source capacitance of the U-phase FET 54U
  • C5 indicates the gate-source capacitance of the X-phase FET 54X
  • C2 indicates the drain-gate capacitance of the U-phase FET 54U
  • C6 indicates the drain-gate capacitance of the X-phase FET 54X
  • C3 indicates the drain-source capacitance of the U-phase FET 54U
  • C7 indicates the drain-source capacitance of the X-phase FET 54X.
  • Vds is the drain-source voltage (voltage between Vp3 and Vp4) of the U-phase FET.
  • operation of the X-phase FET is illustrated as a relay S1 (SW).
  • (a) is a voltage Vp3 of the positive electrode end P3 of the electrolytic capacitor C21, which corresponds to voltage Vp3 in Fig. 8 .
  • Vp3 increases as shown in Fig. 7(a) .
  • This time t3 is an execution time of the process at step S3 in Fig. 6 .
  • This time t4 is an execution time of the process at step S10 in Fig. 6 .
  • the X-phase gate signal (the PWM signal) is input, and the gate of the X-phase FET 54X is ON as shown in Fig. 7 (g) . Therefore, the U-phase gate drive power supply capacitor C31 is charged, and as shown in Fig. 7(e) , the power supply voltage of the U-phase gate drive circuit rises.
  • the drain-source ON-resistance slightly lowers, and consequently, as shown in Fig. 7(j) , the short-circuit current flows along a path of the drain of the U-phase FET 54U ⁇ the source of the U-phase FET 54U ⁇ the drain of the X-phase FET 54X ⁇ the source of the X-phase FET 54X.
  • Fig. 7 shows the time chart of only the set of upper and lower arms of the U-phase and the X-phase
  • the inverter has three sets of upper and lower arms of the U-phase and the X-phase, the V-phase and the Y-phase and the W-phase and the Z-phase, and these all show the operation as in Fig. 7 .
  • the conventional control method shown in Figs. 6 and 7 has a drawback of causing a malfunction due to the high voltage applied to the upper phase side FET then leading to the short circuit of the upper and lower phase arms.
  • Patent Document 1 describes a technique in which a driving transistor is separately provided, a voltage drop of a capacitor of a bootstrap circuit during a long-time intermittent driving operation is predicted by fluctuation (variation) of voltage of a separately provided capacitor, and an output terminal in a high impedance state is made to be low by the driving transistor.
  • this technique of Patent Document 1 it is necessary to use elements by a large number of circuit configurations.
  • Patent Document 2 describes a configuration in which a capacitor of a bootstrap circuit is charged at startup.
  • this configuration is applied to a case where voltage at a time of start is high, and as a problem, there is a risk that a malfunction will occur due to high voltage.
  • the present invention is an invention that solves the above problems, and an obj ect of the present invention is to provide a control device and a control method of a power conversion device which are capable of preventing the drawback of causing the malfunction due to the high voltage applied to the upper phase side FET and leading to the short circuit of the upper and lower phase arms.
  • the power conversion device includes : a power conversion unit in which an upper phase side FET and a lower phase side FET are bridge-connected between positive and negative electrode ends of a DC power supply; an electrolytic capacitor connected to a series circuit of the upper phase side FET and the lower phase side FET of the power conversion unit in parallel; a main contactor interposed on an electric path connecting the positive electrode end of the DC power supply and a positive electrode end of the electrolytic capacitor; a first charging resistor connected to the main contactor in parallel for charging the electrolytic capacitor with a set charging time constant; a series circuit of a charging FET connected to the first charging resistor in parallel and configured to be ON-controlled after a set time after a key switch is turned on and a second charging resistor set to a charging time constant that is shorter than that of the first charging resistor; an upper phase side FET arm gate drive circuit configured to drive a gate of the upper phase side FET of the power conversion unit; a lower
  • the charge voltage value of the electrolytic capacitor in the precharging period is set so that each parasitic capacitance generated between a metal base substrate and terminals of the upper phase side FET and the lower phase side FET of the power conversion unit when the upper phase side FET and the lower phase side FET are mounted on the metal base substrate is taken into consideration, and a voltage generated between the gate and a source of the upper phase side FET when an instantaneous voltage is applied between a drain and the source of the upper phase side FET is calculated, then a voltage value transiently applied to the gate-source voltage Vgs via each parasitic capacitance becomes low in a sufficiently large range as compared with a voltage value at which failure detection by continuation of low voltage between the drain and the source for a certain time is operated.
  • the power conversion device includes: a power conversion unit in which an upper phase side FET and a lower phase side FET are bridge-connected between positive and negative electrode ends of a DC power supply; an electrolytic capacitor connected to a series circuit of the upper phase side FET and the lower phase side FET of the power conversion unit in parallel; a main contactor interposed on an electric path connecting the positive electrode end of the DC power supply and a positive electrode end of the electrolytic capacitor; a first charging resistor connected to the main contactor in parallel for charging the electrolytic capacitor with a set charging time constant; a series circuit of a charging FET connected to the first charging resistor in parallel and configured to be ON-controlled after a set time after a key switch is turned on and a second charging resistor set to a charging time constant that is shorter than that of the first charging resistor; an upper phase side FET arm gate drive circuit configured to drive a gate of the upper phase side FET of the power conversion unit; a lower phase side FET arm gate
  • the charging voltage value of the electrolytic capacitor in the precharging period is set by taking into consideration each stray capacitance (or each parasitic capacitance) in the state in which the FETs are mounted on the metal base substrate and by calculating the gate-source voltage of the upper phase side FET when an instantaneous voltage is applied between the drain and the source of the upper phase side FET, setting accuracy of the charging voltage value of the electrolytic capacitor can be increased, and erroneous failure detection can be avoided.
  • a power conversion device such as an inverter/converter using power MOSFETs etc. in a main control circuit is configured so that especially when a power supply voltage is high, an occurrence of a malfunction (an unintended ON-operation) of an upper phase side FET of a main circuit is prevented.
  • an FET gate drive circuit(s) is configured so that when resuming operation of the inverter/converter (the power conversion device) after continuation of a long-time stop period of the inverter/converter (the power conversion device), the above malfunction is prevented.
  • a value of resistance of the resistor R1 which is a first charging resistor in Fig. 1 , is set so that in a precharging period until the key switch is turned on after the battery 50 is brought to the connecting state, when the upper phase side FET, e.g. the U-phase FET 54U, is controlled to be OFF and the lower phase side EFT, e.g. the X-phase FET 54X, is controlled to be ON, a charge voltage value of the electrolytic capacitor C21 is set so as to be able to limit the gate-source voltage of the U-phase FET 54U to voltage at which the U-phase FET 54U is not turned on.
  • the upper phase side FET e.g. the U-phase FET 54U
  • the lower phase side EFT e.g. the X-phase FET 54X
  • the X-phase FET 54X) of the inverter 54 when the upper phase side FET and the lower phase side EFT are mounted on the metal base substrate is taken into consideration, and a voltage generated between the gate and the source of the upper phase side FET when an instantaneous voltage is applied between the drain and the source of the upper phase side FET is calculated, then a voltage value transiently applied to the gate-source voltage Vgs via each parasitic capacitance becomes low in a sufficiently large range as compared with a voltage value at which failure detection by continuation of low voltage between the drain and the source for a certain time is operated.
  • step S24 a judgment is made as to whether or not the voltage of the positive electrode end P3 is 5V or less and also its state continues for 0.6 seconds. If the judgment result of step S24 is YES, at step S25, a predetermined quick charging error process (process in which the main circuit FET (s) of the inverter and the electrolytic capacitor C21 are judged to be short-circuited, and this abnormal state is notified to a host controller (not shown)) is performed.
  • a predetermined quick charging error process process in which the main circuit FET (s) of the inverter and the electrolytic capacitor C21 are judged to be short-circuited, and this abnormal state is notified to a host controller (not shown)
  • step S27 a predetermined quick charging error process (process in which an error state is notified to the host controller (not shown)) is performed.
  • step S28 a judgment is made as to whether or not the voltage of the positive electrode end P3 is 3V or less and also its state continues for 15 seconds.
  • step S30 the gate of the lower phase side FET, e.g. the X-phase FET 54X, is ON-controlled (is controlled to be on) only for Zmsec, and after that, at step S31, the gate of the X-phase FET 54X is OFF-controlled (is controlled to be off).
  • the gate of the lower phase side FET e.g. the X-phase FET 54X
  • step S32 a judgment is made as to whether or not the voltage Vp3 of the positive electrode end P3 of the electrolytic capacitor C21 is 63V or less. If the judgment result is YES, at step S33, the charging FET 53 of Fig. 1 is turned on again, and the quick charging of the electrolytic capacitor C21 is performed.
  • step S34 If the judgment result of step S34 is NO or after the process of step S35, at step S36, the main contactor 52 of Fig. 1 is turned on, and after the turning-on of the main contactor 52, at step S37, the inverter 54 is operated.
  • Fig. 12 shows operation waveform of each part of only a set of upper and lower arms of the U-phase and the X-phase when the process along the flow chart of Fig. 10 is performed.
  • the charging resistor R1 is set so that the precharging voltage value of the electrolytic capacitor C21 of Fig. 1 becomes low, as shown in Fig. 12(a), (b) and (c) , voltage waveforms move (increase) at Vp3, Vds and Vp4 that are lower than the voltage waveforms shown by broken lines according to the conventional control method.
  • Fig. 12 (g) the gate of the X-phase FET 54X is ON-controlled. With this, current flows along the path shown by a broken arrow in Fig. 4 , and the upper phase (U-phase) side gate drive power supply capacitor (the capacitor C31) is charged, then as shown in Fig. 12(e) , the power supply voltage of the U-phase gate drive circuit rises.
  • the U-phase FET 54U is ON-controlled, and as shown in Fig. 12 (b) , the drain-source voltage Vds of the U-phase FET 54U correctly becomes zero (normal ON-operation is performed).
  • the upper phase (U-phase) side FET arm gate drive circuit (the high side totem-pole circuit of the HVIC 60 in Fig. 5 ) performs an OFF-output operation (sink-operation), and the gate-source voltage (charge of the input capacitance Cgs) of the U-phase FET 54U is discharged through the resistor R11, the lower side FET of the high side totem-pole circuit and the resistor R12 of Fig. 5 .

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)
  • Power Conversion In General (AREA)
EP22749403.6A 2021-02-04 2022-01-06 Dispositif de commande et procédé de commande pour dispositif de conversion de courant Pending EP4290751A4 (fr)

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CA3207445C (fr) 2024-01-16
CN116868496A (zh) 2023-10-10
CN116868496B (zh) 2024-03-08
EP4290751A4 (fr) 2024-04-10
JP7060120B1 (ja) 2022-04-26
US20240039425A1 (en) 2024-02-01
WO2022168524A1 (fr) 2022-08-11
JP2022119285A (ja) 2022-08-17
US11973439B2 (en) 2024-04-30

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