Classifications

• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/185—Joining of semiconductor bodies for junction formation
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/185—Joining of semiconductor bodies for junction formation
  • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/02002—Preparing wafers
  • H01L21/02005—Preparing bulk and homogeneous wafers
  • H01L21/02008—Multistep processes
  • H01L21/0201—Specific process step
  • H01L21/02016—Backside treatment
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
  • H01L21/048—Making electrodes
  • H01L21/0485—Ohmic electrodes
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
  • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
  • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
  • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
  • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/838—Bonding techniques
  • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
  • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
  • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
  • H01L2224/83909—Post-treatment of the layer connector or bonding area
  • H01L2224/83948—Thermal treatments, e.g. annealing, controlled cooling
• • H—ELECTRICITY
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  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/102—Material of the semiconductor or solid state bodies
  • H01L2924/1025—Semiconducting materials
  • H01L2924/10251—Elemental semiconductors, i.e. Group IV
  • H01L2924/10253—Silicon [Si]
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
  • H01L2924/10—Details of semiconductor or other solid state devices to be connected
  • H01L2924/102—Material of the semiconductor or solid state bodies
  • H01L2924/1025—Semiconducting materials
  • H01L2924/1026—Compound semiconductors
  • H01L2924/1027—IV
  • H01L2924/10272—Silicon Carbide [SiC]

Definitions

• the present invention relates to the field of semiconductor materials for microelectronic components. It relates in particular to a structure comprising a single-crystal semiconductor layer and a semiconductor support substrate, assembled at an electrically conductive bonding interface. The invention also relates to a method of manufacturing such a structure.
• a semiconductor structure by transferring a useful semiconductor layer, of small thickness and of high crystalline quality, onto a semiconductor support substrate of lower crystalline quality.
• a well-known thin film transfer solution is the Smart CutTM process, based on light ion implantation and assembly by direct bonding at a bonding interface.
• the semiconductor structure can also provide advantageous properties, for example linked to the thermal or electrical conductivity or the mechanical compatibility of the support substrate.
• the bonding interface must have a resistivity as low as possible, preferably lower than 1 mohm.cm 2 , or even less than 0.1 mohm.cm 2 .
• Some solutions of the state of the art propose direct bonding semiconductor on semiconductor, between the useful layer and the support substrate, to establish vertical electrical conduction. It can nevertheless be difficult to obtain a good quality of interface via such a bonding.
• the present invention relates to an alternative solution to those of the state of the art, and aims to remedy all or part of the aforementioned drawbacks. It relates in particular to a structure comprising a monocrystalline semiconductor useful layer and a semiconductor support substrate, assembled at an electrically conductive bonding interface. The invention also relates to a method of manufacturing such a structure.
• the invention relates to a semiconductor structure comprising a useful layer of monocrystalline semiconductor material, extending along a main plane, a support substrate of semiconductor material, and an interface zone between the useful layer and the substrate. support, extending parallel to the main plane.
• the structure is remarkable in that the interface zone has nodules: - electrical conductors, comprising a metallic material forming an ohmic contact with the useful layer and with the support substrate, having a thickness, along an axis normal to the main plane, less than or equal to 30 nm,
• disjoint nodules being separated from each other by regions of direct contact between the useful layer and the support substrate.
• the useful layer and the support substrate are formed from the same semiconductor material and have an identical type of doping
• the semiconductor material of the useful layer is chosen from silicon carbide, silicon, gallium nitride and germanium;
• the semiconductor material of the support substrate is chosen from silicon carbide, silicon, gallium nitride and germanium, and has a monocrystalline, polycrystalline or amorphous structure;
• the metallic material of the nodules is chosen from tungsten, titanium, nickel, aluminium, molybdenum, niobium, tantalum, cobalt and copper;
• the nodules have a resistivity of less than 0.1 mohm.cm 2 , preferably less than or equal to 0.01 mohm.cm 2 , so as to obtain a resistivity of the interface zone of less than 0.1 mohm.cm 2 , preferably less than or equal to 0.01 mohm.cm 2 ; • the nodules have a thickness less than or equal to 20 nm, or even less than or equal to 1 Onm.
• 1 / invention also relates to a power component produced on and / or in the useful layer of a semiconductor structure as above, and comprising at least one electrical contact on and / or in the support substrate, at the level of a rear face of the semiconductor structure.
• the invention relates to a method for manufacturing a structure as above, comprising the following steps a) supplying a useful layer of monocrystalline semiconductor material having a free face to be assembled, b) supplying of a support substrate made of semiconductor material having a free face to be assembled, c) the deposition of a film made of a metallic material capable of forming an ohmic contact with the useful layer and with the support substrate and having a thickness less than or equal to 20 nm, on the free face to be assembled of the useful layer and/or on the free face to be assembled of the support substrate, under a controlled non-oxidizing atmosphere, d) the formation of an intermediate structure, comprising a direct assembly of the faces free to assemble respectively of the useful layer and of the support substrate, under a non-oxidizing controlled atmosphere, the intermediate structure including an encapsulated film resulting from the film(s) deposited during step c), e) the re bakes the intermediate structure at a temperature greater than or equal to a critical temperature, so as to cause the segment
• the useful layer and the support substrate are formed from the same semiconductor material and have an identical type of doping
• step a) comprises an implantation of light species in a donor substrate, to form a buried fragile plane which delimits, with a front face of the donor substrate, the useful layer;
• step a) comprises the formation of the donor substrate by epitaxy of a donor layer on an initial substrate, the implantation being carried out subsequently, in the donor layer;
• step d) comprises, after the direct assembly giving rise to a bonded assembly comprising the donor substrate and the support substrate, a separation at the level of the buried fragile plane, to form on the one hand the intermediate structure comprising the useful layer , the encapsulated film and the support substrate, and on the other hand, the rest of the donor substrate;
• the manufacturing method comprises, prior to step c) of deposition, a step c′) of deoxidizing the free face to be assembled of the useful layer and/or the free face to be assembled of the support substrate;
• step c) • the deposition of step c) and the direct assembly of step d) are carried out in the same equipment;
• the thickness of the film deposited in step c) is less than or equal to 10 nm, or even less than or equal to 5 nm, or even less than or equal to 2 nm;
• steps c) and d) are carried out under vacuum
• step c) of deposition is carried out at room temperature, by a spraying technique;
• the semiconductor material of the useful layer is chosen from silicon carbide, silicon, gallium nitride and germanium;
• the semiconductor material of the support substrate is chosen from silicon carbide, silicon, gallium nitride and germanium, and has a monocrystalline, polycrystalline or amorphous structure;
• the metallic material of the film is chosen from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt, copper;
• the critical temperature is between 500° C. and 1800° C., depending on the nature of the metallic material of the encapsulated film and of the semiconductor material(s) of the useful layer and of the support substrate.
• FIG. 1 shows a structure according to the invention
• FIG. 2a to 2e show steps of a manufacturing method according to the invention
• FIGS. 3a to 3d present variants of steps of a manufacturing method in accordance with the invention.
• FIG. 4 shows a current curve as a function of the applied voltage, measured from two electrodes produced on a structure in accordance with the invention, the current path crossing the interface zone of said framework;
• FIG. 4 also presents a current/voltage curve for a solid substrate and for a bonded structure not in accordance with the invention, by way of comparison.
• FIG. 5 shows a graph linking the resistivity of the nodules in the interface zone of a structure according to the invention, and the coverage rate of said nodules, to obtain different levels of resistivity of the zone of interface.
• FIG. 6 presents a graph of current as a function of voltage, illustrating the evolution of the resistivity of the interface zone as a function of the thickness of the film of metallic material deposited before the formation of the intermediate structure.
• the same references in the figures may be used for elements of the same type.
• the figures are schematic representations which, for the purpose of readability, are not to scale.
• the thicknesses of the layers along the z axis are not to scale with respect to the lateral dimensions along the x and y axes; and the relative thicknesses of the layers between them are not observed in the figures.
• the invention relates to a semiconductor structure 100 comprising a useful layer 10 made of monocrystalline semiconductor material, a support substrate 30 made of semiconductor material, and an interface zone 20 between the useful layer 10 and the support substrate 30 ( figure 1).
• the interface zone 20 extends parallel to the main plane
• the semiconductor structure 100 is in the form of a circular wafer with a diameter between 100mm and 450mm, and a total thickness typically between 300 microns and 1000 microns. It is understood that, in this case, the support substrate 30 and the useful layer 10 also have such a circular shape.
• the (circular) front 100a and rear 100b faces of the wafer extend parallel to the main plane (x,y).
• the semiconductor material of useful layer 10 can be chosen from among silicon carbide, silicon, gallium nitride and germanium.
• the development of components on the useful layer 10 requires a high crystalline quality of said layer 10: it is therefore chosen monocrystalline, with a grade of quality, a type and a level of doping adapted to the intended application.
• the semiconductor material of support substrate 30 can be chosen from among silicon carbide, silicon, gallium nitride and germanium. It preferably has a lower level of quality, essentially for economic reasons, and a monocrystalline, polycrystalline or amorphous structure. Its type and level of doping are chosen to meet the intended application.
• the interface zone 20 of the semiconductor structure 100 according to the invention is remarkable in that it comprises electrically conductive nodules 21. Each of these nodules 21 comprises a metallic material capable of forming an ohmic contact with the useful layer 10 and with the support substrate 30.
• the metallic material of the nodules 21 may be chosen from tungsten, titanium, nickel, aluminum, molybdenum, niobium, tantalum, cobalt and copper. As is known to those skilled in the art, not all of these materials are capable of forming an ohmic contact with all the semiconductor materials stated as capable of forming the useful layer 10 and/or the support substrate 30. The metallic material nodules 21 will therefore be chosen according to the nature of the useful layer 10 and of the support substrate 30. A few specific examples will be described later.
• the nodules 21 of the interface zone 20 also have a thickness, along a z axis normal to the main plane (x,y), low or even very low: typically less than or equal to 30 nm, less than or equal to 20 nm, less than or equal to lOnm, or even less than or equal to 5 nm.
• the nodules 21, distributed in the interface zone 20, are separate or joined; the disjoint nodules are mostly separated from each other by regions 22 in which the useful layer 10 is directly in contact with the support substrate 30, in other words, in which there is a direct connection between the semiconductor materials of the layer useful 10 and of the support substrate 30. These regions 22 will be referred to below as direct contact regions 22.
• cavities of nanometric thickness in these contact regions 22 may possibly exist, in certain cases of semiconductor structure 100, cavities of nanometric thickness in these contact regions 22, but said cavities occupy less 20%, or even less than 10%, or even even less than 5% of the surface along the main plane (x,y) occupied by the contact regions 22. Their thickness is moreover less than that of the nodules 21.
• the semiconductor structure 100 guarantees excellent electrical conductivity between the useful layer 10 and the support substrate 30, via its interface zone 20.
• the direct contact regions 22 may possibly allow electrical conduction but less efficiently than the nodules 21.
• these direct contact regions 22 ensure the mechanical continuity of the interface zone 20 and provide excellent mechanical strength between the useful layer 10 and the support substrate 30.
• the quality of the useful layer 10 is therefore not affected by any holes or interface defects; note that the aforementioned cavities, when they are present, have dimensions and a density which do not negatively impact the quality and the mechanical strength of the useful layer 10.
• the rate of coverage of the nodules 21 is typically between 1% and 70%, preferably between 10% and 60%.
• the nodules 21 have a resistivity of less than 0.1 mohm.cm 2 , or even less than or equal to 0.01 mohm.cm 2 .
• a resistivity in ohm.cm 2 for the nodules 21 or more generally for the interface zone 20 due to their very small thickness.
• the resistivity of the nodules 21 In the resistivity of the nodules 21, the resistivity of the metallic material forming the nodules 21, the specific resistance of the contact between the nodules 21 and the useful layer 10, and the specific resistance of the contact between the nodules 21 and the support substrate 30 are integrated. It is these contact resistances that dominate the overall vertical resistance. Consequently, it is appropriate to speak of surface resistivity in ohm.cm 2 .
• the specific contact resistances may be different, depending on the nature and/or the doping of the respective materials of the useful layer 10 and of the support substrate 30.
• the specific contact resistance of a nickel nodule (Ni ) with silicon carbide (SiC) having an N type doping level (nitrogen or phosphorus dopant) of 4E15/cm 3 will be of the order of 3mQ.cm 2 , whereas for an N doping level of lE19 /cm 3 , it will be approximately 0.003mQ.cm 2 .
• the graph of FIG. 5 shows the evolution of the resistivity of the interface zone 20, as a function of the resistivity of the nodules 21 and of their coverage rate in the median plane P.
• the targeted resistivity of the interface zone 20, for power applications is less than or equal to 1 mohm.cm 2 , or even less than or equal to 0.1 mohm.cm 2 .
• the useful layer 10 and the support substrate 30 are formed from the same semiconductor material and have an identical type of doping, to allow effective vertical electrical conduction between the components which will be produced in and/or on the useful layer 10 and the components and/or the electrode which will be produced on the rear face 30b of the support substrate 30 of the structure 100.
• a semiconductor structure 100 in accordance with the present invention comprises a useful layer 10 of high quality monocrystalline silicon carbide;
• high quality we typically mean a SiC with less than 1 micro-hole per cm2 (“micropipe”, MP), less than 500 screw dislocations per cm2 (“threading screw dislocation”, TSD), less than 5000 edge dislocations per cm2 (“threading edge dislocation”, TED), less than 1000 basal plane dislocations per cm 2 (“basal plane dislocation”, BPD) and less than 1 stacking fault/cm (“stacking fault”, SF).
• the SiC of the useful layer 10 has an N-type doping at 8 ⁇ 10 18 /cm 3 .
• Semiconductor structure 100 also comprises a support substrate 30 made of low-quality monocrystalline or polycrystalline silicon carbide, having an N-type doping with a resistivity of the order of 20 m ⁇ .cm.
• the nodules 21 are made of tungsten (W); they have a thickness of the order of 5 nm, and a coverage rate of between 15% and 25%.
• the resistivity of the interface zone 20 of such a structure 100 is of the order of 0.05 mohm.cm 2 , ie less than or equal to 0.1 mohm.cm 2 .
• a semiconductor structure 100 in accordance with the present invention comprises a useful layer 10 of high quality monocrystalline silicon carbide, having a P-type doping at lxl0 19 /cm 3 , and a support substrate 30 of silicon low quality monocrystalline or polycrystalline, having a P-type doping at 5x10 19 /cm 3 .
• Nodules 21 of interface zone 20 are made of titanium (Ti); they have a thickness of the order of 6 nm, and a coverage rate of between 30% and 40%.
• the resistivity of interface zone 20 of such a structure 100 is less than 1 mohm.cm 2 .
• a semiconductor structure 100 in accordance with the invention comprises a useful layer 10 of silicon high-quality monocrystalline, having an N-type doping at 5 ⁇ 10 19 /cm 3 , a support substrate 30 made of low-quality monocrystalline or polycrystalline silicon, having an N-type doping at 5 ⁇ 10 19 /cm 3 .
• the nodules 21 are made of aluminum (Al); they have a thickness of the order of 3 nm, and a coverage rate of between 5% and 15%.
• the resistivity of interface zone 20 of such a structure 100 is less than 1 mohm.cm 2 .
• Power components can in particular be produced on and/or in the useful layer 10 of a semiconductor structure 100 according to the invention. These components may in particular comprise at least one electrical contact on and/or in the support substrate 30, at the level of a rear face 100b of the semiconductor structure 100.
• these power components may comprise transistors, diodes, thyristors or passive components (capacitors, inductors%), etc.
• the invention also relates to a method of manufacturing a semiconductor structure 100 as previously described.
• the manufacturing method firstly comprises a step a) of supplying the useful layer 10 of monocrystalline semiconductor material (FIG. 2a).
• the useful layer 10 has a free face 10a intended to be assembled, during a subsequent step of the process, also called front face 10a; it also has a rear face 10b opposite its front face 10a.
• the useful layer 10 results from the transfer of a surface layer of a donor substrate 1, in particular a layer transfer based on the Smart Cut process.
• Step a) can thus comprise an implantation of light species, for example hydrogen, helium or a combination of these two species, in a donor substrate 1, to form a buried fragile plane 11 which delimits, with a front face 10a of the donor substrate 1, useful layer 10 (FIG. 3a).
• light species for example hydrogen, helium or a combination of these two species
• step a) comprises the formation of the donor substrate 1 by epitaxy of a donor layer 1′ on an initial substrate, prior to the implantation of the light species (FIG. 3b).
• This variant makes it possible to form a donor layer l' having the structural and electrical characteristics required for the intended application.
• an excellent crystalline quality can be obtained by epitaxy, and an in situ doping of the donor layer 1' can be precisely controlled.
• the implantation of light species to form the buried fragile plane 11 is then carried out in the donor layer 1'.
• the useful layer 10 provided in step a) can of course be formed using other known thin layer transfer techniques.
• the manufacturing method according to the invention then comprises a step b) of supplying a support substrate 30 made of semiconductor material (FIG. 2b).
• the support substrate 30 has a free face 30a intended to be assembled during a subsequent step of the method, also called front face 30a; it also has a rear face 30b.
• the useful layer 10 may be formed of one or more materials chosen from among silicon carbide, silicon, gallium nitride and germanium; and the support substrate 30 may be formed of one or more materials chosen from silicon carbide, silicon, gallium nitride and germanium, preferably of lesser quality, monocrystalline, polycrystalline or even amorphous.
• the useful layer 10 and the support substrate 30 are formed from the same semiconductor material and have an identical type of doping (N or P).
• the manufacturing method then comprises a step c) of depositing a film 2 of a metallic material on the free face to be assembled 10a of the useful layer 10 or on the free face to be assembled 30a of the support substrate 30 or, as is illustrated in Figure 2c on the two free faces to be assembled 10a, 30a.
• the metallic material is chosen for its ability to form an ohmic contact with the useful layer 10 and with the support substrate 30. It may be chosen from the following non-exhaustive list of materials: tungsten, titanium, nickel, aluminium, molybdenum, niobium, tantalum, cobalt, copper, depending on the nature of the useful layer 10 and the support substrate 30.
• the film 2 has a thickness less than or equal to 20 nm, preferably less than or equal to 10 nm, or even less than or equal to 5 nm.
• the film 2 deposited may have a thickness of the order of 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 8 nm, 1 Onm or 15 nm.
• the total thickness deposited that is to say the sum of the thicknesses of film 2 deposited on one and the other free faces 10a, 30a is preferably less than or equal to 20 nm, or even less than or equal to 10 nm.
• the total thickness of film 2 deposited is imperatively kept low, so as to allow segmentation of the film in the form of nodules 21, at a later stage of the process.
• the deposition of the film 2 is carried out under a controlled non-oxidizing atmosphere. It is important that the metal film 2 does not undergo oxidation or is not degraded by pollution from the surrounding atmosphere. Typically, the deposition of step c) is carried out under a high vacuum, of the order of 10 6 Pa or less.
• step c) is carried out at room temperature or at low temperature, advantageously by a sputtering deposition technique using, to bombard the metal target, a neutral element or one whose residual presence in the metal deposited is not troublesome (Ar, Si, N).
• the manufacturing method according to the invention comprises, prior to step c) of deposition, a step c′) of deoxidation of the free face to be assembled 10a of the useful layer 10 and/ or of the free face to be assembled 30a of the support substrate 30.
• a step c′ of deoxidation of the free face to be assembled 10a of the useful layer 10 and/ or of the free face to be assembled 30a of the support substrate 30.
• Such a step makes it possible to remove the native oxide potential present at the surface of the useful layer 10 and/or of the support substrate 30, which facilitates the formation of an ohmic contact with the metallic material, at a later stage of the process.
• Deoxidation can be carried out by wet chemical treatment (removal by HF attack for example) or dry (dry etching or annealing under a reducing atmosphere).
• the manufacturing method then comprises a step d) of forming an intermediate structure 150, which step comprises direct assembly of the free faces to be assembled 10a, 30a respectively of the useful layer 10 and of
• This direct assembly is preferably carried out by bonding by molecular adhesion, consisting of bringing the faces to be assembled 10a, 30a into contact, under a controlled non-oxidizing atmosphere. It could be a direct bonding between the useful layer 10 and the film 2, when the latter has only been deposited on the support substrate 30, or a direct bonding between the support substrate 30 and the film 2, when the latter has only been deposited on the useful layer 10, or even by direct bonding between two films 2, when they have been deposited on the useful layer 10 and on the support substrate 30.
• the direct assembly is preferably carried out under a controlled atmosphere and in particular under a high vacuum, of the order of 10 6 Pa or less.
• step c) and the direct assembly of step d) are linked together without breaking the vacuum, in-situ or in multi-chamber equipment.
• Mention will be made, by way of example, of the BV7000 Atomic Diffusion Bonding equipment from the company Canon, in which it is possible to carry out successively a metal deposition and a direct bonding, while maintaining a controlled atmosphere.
• step d) comprising the direct assembly of the free face to be assembled 10a of the useful layer 10 on the free face to be assembled 30a of the support substrate 30 , gives rise to a bonded assembly 200 including the donor substrate 1, the substrate support 30, and the bonding interface 15 (FIG. 3c).
• Step d) further comprises a separation at the level of the buried fragile plane 11, to form on the one hand the intermediate structure 150 comprising the useful layer 10, the film(s) 2 and the support substrate 30, and on the other hand, the rest of the donor substrate l'' (FIG. 3d).
• Such a separation can be carried out during a heat treatment capable of causing cavities and microcracks to grow, induced by the implanted species, in the buried fragile plane 11.
• the separation can also be carried out by applying a mechanical stress, or even by the combination of thermal and mechanical stresses, as is well known with reference to the Smart Cut process.
• Sequences of cleaning, smoothing, polishing or etching of the face 10b separated from the useful layer 10 and/or of the face separated 'a from the rest of the donor substrate '' can be carried out so as to restore a good surface quality, particularly in terms of roughness, defects and other contaminations .
• the intermediate structure 150 has a front face 10b on the side of the useful layer 10, a rear face 30b on the side of the support substrate 30 , and an encapsulated film 2' between the useful layer 10 and the support substrate 30.
• the encapsulated film 2' corresponds to the film 2 when the latter has only been deposited on one of the free faces to be assembled 10a, 30a, or corresponds to the two films 2 deposited respectively on the useful layer 10 and on the support substrate 30.
• the manufacturing method according to the invention then comprises a step e) of annealing the intermediate structure 150 to a temperature greater than or equal to a critical temperature, so as to cause the segmentation of the encapsulated film 2' in the form of nodules 21 electrical conductors and form the interface zone 20 (FIG. 2e).
• Step e) results in the formation of the semiconductor structure 100.
• the critical temperature is the temperature from which the contact between the metal of the encapsulated film 2′ and the semiconductor of the useful layer 10 and of the support substrate 30 becomes ohmic, on the one hand: for example, between 400° C and 650°C for the Al/Si couple, between 950°C and 1100°C for the Ni/SiC couple, etc.
• the critical temperature must on the other hand be sufficient to allow the bonding of the direct contact regions 22, between the nodules 21.
• the system including the encapsulated film 2' and the semiconductor surfaces of the useful layer 10 and of the support substrate 30 in contact with said film 2' will optimize its surface energy by agglomerating the film encapsulated 2' in the form of nodules 21 establishing an ohmic contact with the semiconductor surfaces, and creating direct contact regions 22 between the semiconductor surfaces respectively of the useful layer 10 and of the support substrate 30.
• the encapsulated film 2' is extremely thin, metallic materials known to be stable at low or medium temperature only, can be used in semiconductor structures 100 in accordance with the invention capable of undergoing high-temperature treatments. (900°C-1100°C), even very high (1200°C-1800°C) temperatures: indeed, due to their agglomeration in the form of nodules 21 of low dimensions and of very low thickness, they do not cause deterioration of the structure 100 and in particular of the useful layer 10. Mention will be made, for example, of the case of nodules 21 made of nickel or titanium in a structure 100 comprising a useful layer 10 and a support substrate 30 made of SiC and intended to undergo epitaxy at a temperature between 1600° C. and 1800° C.
• the manufacturing method as described therefore makes it possible to obtain a semiconductor structure 100 providing vertical electrical conduction between the useful layer 10 and the support substrate 30, via an interface zone 20.
• the very fine nodules 21 are largely part made of metal and therefore have a very low resistivity.
• the presence of direct contact regions 22 between the disjoint nodules 21 avoids any problem of mechanical strength or more generally of reliability of the useful layer 10 and/or of the components which will be produced on or in the latter.
• the invention is based on an assembly via a metal film 2, the increase in the interface resistivity, linked to the direct bonding of semiconductor materials whose crystallographic nature is different, is not problematic for the vertical electrical conduction in the structure 100, the nodules 21 guaranteeing said conduction.
• the donor substrate 1 is in SiC 4H, monocrystalline of high quality and has a diameter of 150 mm.
• the donor substrate 1 is N-doped, with a resistivity of the order of 20 mohm.cm. It is implanted through its front face, the “C” type face, with hydrogen ions at a dose of 5 E 16/cm2 and an energy of 95keV. Around the implantation depth, a buried fragile plane 11 is thus defined, delimiting with the front face 10a of the donor substrate 1, the useful layer 10.
• the support substrate 30 is made of monocrystalline 4H SiC of lesser quality, of the same diameter as the donor substrate 1. It is N-doped, with a resistivity of the order of 20 mohm.cm.
• the two 1.30 substrates undergo cleaning sequences to remove particles and other surface contamination.
• the sequences are preferably chosen so that the surfaces of the substrates 1.30 do not undergo oxidation (absence of native oxide).
• the 1.30 substrates are introduced into a first deposition chamber, integrated with direct bonding equipment.
• a film 2 of tungsten with a thickness of 0.5 nm is deposited on each of the front faces 10a, 30a (free faces to be assembled) of the substrates 1.30, under vacuum, at 10 6 Pa and room temperature, by sputtering.
• the substrates 1,30 are introduced into a second bonding chamber, to be assembled at their front faces 10a,30a, by bringing the films 2 deposited respectively on the donor substrate 1 and on the support substrate 30 into direct contact.
• the atmosphere in the bonding chamber is the same as that in the deposition chamber, which avoids any oxidation or passivation of the surface of the films 2.
• the bonded assembly 200 comprises the donor substrate 1 bonded to the support substrate 30 via a bonding interface 15, and the encapsulated film 2' formed from the two films 2 deposited and buried between the two substrates 1,30.
• the encapsulated film 2' has a thickness of the order of 1 nm.
• the bonded assembly 200 is subjected to a heat treatment to cause separation at the level of the buried fragile plane 11, at a temperature of approximately 900° C., for 30 minutes.
• the intermediate structure 150 is then obtained including a useful layer 10 having a thickness of 500 nm, placed on the encapsulated film 2′, itself placed on the support substrate 30. Cleaning and polishing sequences are applied so as to to restore the correct level of defectivity and roughness to the surface 10b of the useful layer 10.
• the structure 100 according to the invention is obtained: the interface zone 20 is formed and the nodules 21 in tungsten, separated by regions of direct contact 20 between useful layer 10 and support substrate 30, give structure 100 excellent vertical electrical conductivity, almost identical to that of a solid SiC substrate having a resistivity of 20 mohm.cm.
• FIG. 4 illustrates the current curves as a function of the voltage I(V) for simple components comprising two metal contact electrodes.
• the measurement of I(V) is made at the level of two electrodes between which the current path crosses the interface zone 20.
• the interface zone 20 has a lower resistivity or equal to 0.1 mohm.cm 2 .
• the nodules 21 in this structure 100 have a thickness of the order of 5 nm and an average diameter of the order of 20 nm.
• the rate of coverage of the nodules 21, in a median plane of the interface zone 20 is of the order of 20%.
• the graph of FIG. 4 shows, by way of comparison, under the name “bonding not in accordance with the invention”, the I(V) curve of a structure based on direct SiC/SiC bonding with high doping (implantation nitrogen) of the assembled surfaces, the SiC substrates having the same resistivity as in the aforementioned structure 100.
• the improvement in terms of resistivity of the interface zone provided by the present invention is clearly apparent in Figure 4. Under the same experimental conditions as those described previously, it was observed that the resistivity of the interface zone 20 could be further reduced with a thickness of encapsulated film 2' of the order of 2 nm, or even 3 nm.
• Figure 6 shows the impact on the I(V) curve, of thicknesses ranging from 0.4 nm to 2 nm of the encapsulated film 2': the I(V) curve for an encapsulated film 2' with a thickness of 2 nm is very close from that obtained with a massive SiC substrate.

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