EP4053992B1 - High-frequency line connection structure - Google Patents
High-frequency line connection structure Download PDFInfo
- Publication number
- EP4053992B1 EP4053992B1 EP19950886.2A EP19950886A EP4053992B1 EP 4053992 B1 EP4053992 B1 EP 4053992B1 EP 19950886 A EP19950886 A EP 19950886A EP 4053992 B1 EP4053992 B1 EP 4053992B1
- Authority
- EP
- European Patent Office
- Prior art keywords
- signal
- ground
- line
- substrate
- frequency line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P5/00—Coupling devices of the waveguide type
- H01P5/02—Coupling devices of the waveguide type with invariable factor of coupling
- H01P5/022—Transitions between lines of the same kind and shape, but with different dimensions
- H01P5/028—Transitions between lines of the same kind and shape, but with different dimensions between strip lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/04—Fixed joints
- H01P1/047—Strip line joints
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P11/00—Apparatus or processes specially adapted for manufacturing waveguides or resonators, lines, or other devices of the waveguide type
- H01P11/001—Manufacturing waveguides or transmission lines of the waveguide type
- H01P11/003—Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/003—Coplanar lines
- H01P3/006—Conductor backed coplanar waveguides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P3/00—Waveguides; Transmission lines of the waveguide type
- H01P3/02—Waveguides; Transmission lines of the waveguide type with two longitudinal conductors
- H01P3/08—Microstrips; Strip lines
- H01P3/081—Microstriplines
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/0243—Printed circuits associated with mounted high frequency components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/222—Completing of printed circuits by adding non-printed jumper connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
- H05K3/3426—Leaded components characterised by the leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01P—WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
- H01P1/00—Auxiliary devices
- H01P1/20—Frequency-selective devices, e.g. filters
- H01P1/2007—Filtering devices for biasing networks or DC returns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3421—Leaded components
Definitions
- the present invention relates to a high-frequency line connecting structure for mounting a bridge substrate on a printed circuit board, crossing high-frequency lines of the printed circuit board three-dimensionally, and inserting electronic components into the high-frequency lines of the printed circuit board.
- the connections When electrically connecting a plurality of various optoelectronic components on a printed circuit board having a limited area, the connections require a wider bandwidth of DC to 40 GHz. Furthermore, as seen in the recent progress of 1 Tbps optical communication technology, a wider bandwidth of 70 GHz or more is indispensable at the connections.
- the printed circuit board has been established as a platform used when mounting various optoelectronic components, and is widely used as a substrate on which optoelectronic components are to be mounted.
- the printed circuit board is actually used, in order to prevent spatial interference between high-frequency lines and the optoelectronic components, a large number of methods have been adopted to bypass the high-frequency line to the inside of the printed circuit board, that is, an inner layer line.
- an inner layer line In such a structure where the high-frequency lines are bypassed to the inner layer line, the occurrence of an open stub is inevitable due to the structure.
- the effect of open stubs on high frequency characteristics has always been discussed.
- Non-Patent Literature 1 discloses a transition of a stub resonance frequency to a high region by shortening the length of an open stub. By shortening the length of the open stub, the stub resonance frequency can be set to a frequency outside a roll-off frequency of a pass band, which is 20 GHz or more in the example described in Non-Patent Literature 1. However, it is physically difficult to eliminate the stub resonance itself, and the problem of roll-off of the pass characteristics due to the stub resonance remains.
- Non-Patent Literature 2 discloses a method for shortening the length of an open stub by maximizing the machining accuracy of back drilling.
- the method disclosed in Non-Patent Literature 2 requires a high-precision processing technique, which causes a problem that the cost of the printed circuit board increases and the economic efficiency is impaired. Therefore, it has been difficult for the prior art to realize a wide bandwidth of DC to 70 GHz without impairing economic efficiency.
- Fig. 18A is a plan view of a conventional multilayer printed circuit board
- Fig. 18B is a cross-sectional view taken along line A-A' of the multilayer printed circuit board of Fig. 18A
- Two high-frequency lines, a differential microstrip line 101 and a single-phase coplanar line 102, are formed on an upper surface of a multilayer printed circuit board 100.
- the single-phase coplanar line 102 is composed of a signal line 103 and a ground plane 104 formed around the signal line 103.
- a multilayer printed circuit board having a limited area is used, in some cases a plurality of high-frequency lines are provided in this manner.
- the single-phase coplanar line 102 is divided into two parts at a section where the single-phase coplanar 102 intersects with the differential microstrip line 101.
- a structure is provided in which high-frequency signals are relayed by two vertical vias 105 of the multilayer printed circuit board 100 that are formed vertically and an inner layer line 106 of the multilayer printed circuit board 100 formed horizontally. Unnecessary parts of the vertical vias 105 are removed from a rear surface of the substrate by back drilling, which is one of the manufacturing processes of the multilayer printed circuit board.
- holes 107 are formed by back drilling.
- the formation of open stubs 108 is inevitable due to the limitation of machining accuracy.
- the presence of the open stubs 108 induces a resonance phenomenon when a high-frequency signal propagates to the inner layer line 106, affecting the pass characteristics of the single-phase coplanar line 102.
- Fig. 19 is a diagram showing reflection loss characteristics and passage loss characteristics of the single-phase coplanar line 102 of the multilayer printed circuit board 100.
- Reference numeral 200 in Fig. 19 indicates the reflection loss characteristics
- reference numeral 201 indicates the passage loss characteristics. Due to the presence of the open stubs 108, a depression is generated in the passage loss characteristics at a specific resonance frequency (near 25 GHz in the example illustrated in Fig. 19 ), and the characteristics of suppressing the propagation of the high-frequency signal appear.
- the stub length In order to realize a wide bandwidth of DC to 70 GHz, the stub length needs to be processed to 100 ⁇ m or less. However, in order to process the stub length to 100 ⁇ m or less, the accuracy of precision machining to obtain a stub length thinner than one insulating layer constituting the multilayer printed circuit board is required, and therefore it is difficult to shorten the stub length.
- a bridge substrate on which a high-frequency line is formed is mounted on a printed circuit board on which a coplanar line intersecting with a microstrip line is formed, and the coplanar lines divided at the portion where the coplanar line intersects with the microstrip line are connected via the high-frequency line of the bridge substrate, to three-dimensionally cross the microstrip line and the coplanar line.
- the connection portion between the bridge substrate and the printed circuit board is exposed to the air, so that a characteristic impedance of the connection portion increases as an electrical capacitance decreases, and there exists a problem that impedance mismatch between the coplanar line of the printed circuit board and the high frequency line of the bridge substrate occurs.
- a capacitor called a so-called DC block capacitor is inserted in series into the high-frequency line.
- a component as a DC block capacitor is mounted on the printed circuit board using the bridge substrate, since the connection portion between the bridge substrate and the printed circuit board is exposed to the air as described above, there is a problem that impedance mismatch between the coplanar line of the printed circuit board and the high frequency line of the bridge substrate occurs.
- US 2016/0013536 A1 relates to 3-D integrated packages and discloses subject-matter according to the preamble of claim 1.
- US 5,270,673 relates to surface mount microcircuit hybrids.
- US 2019/0148316 A1 relates to high-frequency ceramic boards and high-frequency semiconductor element packages.
- the present invention was contrived to solve the foregoing problems, and an object thereof is to provide a high-frequency line connecting structure capable of suppressing impedance mismatch caused by a connection portion between a bridge substrate and a printed circuit board when connecting a high-frequency line using the bridge substrate.
- Another object of the present invention is to provide a high-frequency line connecting structure capable of suppressing impedance mismatch caused by a connection portion between a bridge substrate and a printed circuit board when mounting a component such as a DC block capacity using the bridge substrate.
- a high-frequency line connecting structure of the present invention is defined according to claim 1.
- a structure is obtained in which, at the contact portions between the signal lead pins and the first signal lines and the contact portions between the ground lead pins and the first grounds, the height of the ground lead pins from the first main surface of the first substrate is made greater than that of the signal lead pins so that the ground lead pins each functioning as a ground of a high-frequency line surround the signal lead pins.
- the present invention can provide a high-frequency line connecting structure capable of realizing low reflection loss characteristics, low passage loss characteristics, and low crosstalk characteristics in a wide bandwidth.
- the present invention can also provide a high-frequency line connecting structure capable of realizing low reflection loss characteristics, low passage loss characteristics, and low crosstalk characteristics in a wide bandwidth by means of a configuration in which an electronic component is inserted in a first high-frequency line of a printed circuit board.
- Fig. 1 is an exploded perspective view showing, from above, a high-frequency line connecting structure according to a first embodiment of the present invention
- Fig. 2 is an exploded perspective view showing the high-frequency line connecting structure from below.
- a printed circuit board 2-2 (first substrate) includes a flat plate-shaped dielectric 2-2-5, a microstrip line 2-2-1 made of a conductor that is formed on an upper surface (first main surface) of the dielectric 2-2-5, signal lines 2-2-3a and 2-2-3b (first signal lines) made of conductors that are formed on the upper surface of the dielectric 2-2-5 along a direction intersecting with the microstrip lines 2-2-1, ground planes 2-2-2a and 2-2-2b (first grounds) made of conductors that are formed on the upper surface of the dielectric 2-2-5 along the signal lines 2-2-3a and 2-2-3b, a ground plane 2-2-4 made of a conductor that is formed on a lower surface (second main surface) of the dielectric 2-2-5
- a plurality of the signal lines 2-2-3a are arranged in parallel.
- a plurality of the ground planes 2-2-2a are arranged on both sides of the signal lines 2-2-3a along the signal lines 2-2-3a.
- a plurality of the signal lines 2-2-3b are arranged in parallel.
- a plurality of the ground planes 2-2-2b are arranged on both sides of the signal lines 2-2-3b along the signal lines 2-2-3b.
- the signal lines 2-2-3a and the signal lines 2-2-3b are divided at the intersections thereof with the microstrip line 2-2-1.
- the ground planes 2-2-2a and the ground planes 2-2-2b are divided at sections which are at the same position in extension direction (X direction in Figs. 1 and 2 ) as the sections where the signal lines 2-2-3a and 2-2-3b are divided.
- ground planes 2-2-2a and 2-2-2b are electrically connected to the ground plane 2-2-4 by the ground vias 2-2-6 formed on the dielectric 2-2-5.
- the signal lines 2-2-3a and 2-2-3b and the ground planes 2-2-2a and 2-2-2b constitute a grounded coplanar line 2-2-7 (first high-frequency line) having the ground plane 2-2-4 on a rear surface of the substrate.
- the grounded coplanar line 2-2-7 is divided at the intersection thereof with the microstrip line 2-2-1.
- a high-frequency line substrate 2-1 (second substrate) for connecting the divided grounded coplanar lines 2-2-7 located on both sides of the microstrip line 2-2-1.
- Fig. 3 is a bottom view of the high-frequency line substrate 2-1. In Fig. 3 , the descriptions of the signal lead pins and the ground lead pins, which will be described later, are omitted in order to facilitate understanding of the configuration of the high-frequency line substrate 2-1.
- the high-frequency line substrate 2-1 includes a flat plate-shaped dielectric 2-1-1, a ground plane 2-1-4 made of a conductor that is formed on a lower surface of the dielectric 2-1-1 facing the printed circuit board 2-2, a dielectric 2-1-7 formed on a lower surface of the ground plane 2-1-4 facing the printed circuit board 2-2, a signal line 2-1-6 (second signal line) made of a conductor that is formed on a lower surface (first main surface) of the dielectric 2-1-7 facing the printed circuit board 2-2, so that the extension direction becomes parallel to the extension direction of the signal lines 2-2-3a and 2-2-3b when the high-frequency line substrate 2-1 is mounted on the printed circuit board 2-2, and a ground plane 2-1-5 (second ground) made of a conductor that is formed on the lower surface of the dielectric 2-1-7 facing the printed circuit board 2-2, along the signal line 2-1-6, so that the extension direction becomes parallel to the extension direction of the ground planes 2-2-2a and 2-2-2b when the
- the high-frequency line substrate 2-1 further includes signal lead pins 2-1-3a and 2-1-3b made of conductors that are connected to both ends of the signal line 2-1-6 respectively so as to be in contact with the signal lines 2-2-3a and 2-2-3b when the high-frequency line substrate 2-1 is mounted on the printed circuit board 2-2, ground lead pins 2-1-2a and 2-1-2b made of conductors that are connected to both ends of the ground plane 2-1-5 respectively so as to be in contact with the ground planes 2-2-2a and 2-2-2b when the high-frequency line substrate 2-1 is mounted on the printed circuit board 2-2, and ground vias 2-1-8 made of conductors that are formed in the dielectric 2-1-7 and connect the ground plane 2-1-4 and the ground plane 2-1-5.
- Examples of the material of the dielectrics 2-1-1, 2-1-7, and 2-2-5 include low-loss ceramics such as alumina.
- a plurality of the signal lines 2-1-6 are arranged in parallel on the lower surface of the high-frequency line substrate 2-1.
- the pitch of the signal lines 2-1-6 in the alignment direction (Y direction in Figs. 1 to 3 ) is the same as the pitch of the signal lines 2-2-3a and 2-2-3b in the alignment direction.
- a plurality of the ground planes 2-1-5 are arranged on both sides of the signal lines 2-1-6 along the signal lines 2-1-6.
- the pitch of the ground planes 2-1-5 in the alignment direction is the same as the pitch of the ground planes 2-2-2a and 2-2-2b in the alignment direction.
- the ground planes 2-1-5 are electrically connected to the ground planes 2-1-4 by the ground vias 2-1-8 formed on the dielectric 2-1-7.
- the signal lines 2-1-6 and the ground planes 2-1-5 constitute a grounded coplanar line 2-1-9 (second high-frequency line) having the ground plane 2-1-4 on the opposite side with the dielectric 2-1-7 therebetween.
- a plurality of the signal lead pins 2-1-3a and 2-1-3b are arranged in parallel along the alignment direction of the signal lines 2-2-3a and 2-2-3b and the alignment direction (Y direction in Figs. 1 to 3 ) of the signal lines 2-1-6.
- the pitch of the signal lead pins 2-1-3a and 2-1-3b in the alignment direction is the same as the pitch of the signal lines 2-2-3a and 2-2-3b and the signal lines 2-1-6 in the alignment direction.
- a plurality of the ground lead pins 2-1-2a and 2-1-2b are arranged in parallel along the alignment direction of the ground planes 2-2-2a and 2-2-2b and the alignment direction (Y direction in Figs. 1 to 3 ) of the ground planes 2-1-5.
- the pitch of the ground lead pins 2-1-2a and 2-1-2b in the alignment direction is the same as the pitch of the ground planes 2-2-2a and 2-2-2b and the ground planes 2-1-5 in the alignment direction.
- Examples of a method for fixing the signal lead pins 2-1-3a and 2-1-3b to the signal lines 2-1-6 and a method for fixing the ground lead pins 2-1-2a and 2-1-2b to the ground planes 2-1-5 include brazing and soldering; needless to say, other fixing methods may be adopted.
- the high-frequency line substrate 2-1 and the printed circuit board 2-2 described above are individually prepared, the high-frequency line substrate 2-1 is mounted on the printed circuit board 2-2.
- Fig. 4 is a perspective view of a high-frequency line connecting structure in which the high-frequency line substrate 2-1 is mounted on the printed circuit board 2-2, and the divided grounded coplanar lines 2-2-7 of the printed circuit board 2-2 are connected by the grounded coplanar line 2-1-9 of the high-frequency line substrate 2-1.
- Fig. 5 is a plan view of the high-frequency line connecting structure of Fig. 4
- Fig. 6 is a side view of the high-frequency line connecting structure of Fig. 4 .
- the surface of the high-frequency line substrate 2-1 on which the signal lines 2-1-6 and the ground planes 2-1-5 are formed is placed face-down so the signal lines 2-1-6 are positioned above the divided sections of the signal lines 2-2-3a and 2-2-3b and the ground planes 2-1-5 are positioned on the divided sections of the ground planes 2-2-2a and 2-2-2b, and then the high-frequency line substrate 2-1 is mounted on the printed circuit board 2-2.
- the high-frequency line substrate 2-1 is mounted on the printed circuit board 2-2 in such a manner that the signal lead pins 2-1-3a and 2-1-3b of the high-frequency line substrate 2-1 and the signal lines 2-2-3a and 2-2-3b of the printed circuit board 2-2 come into contact with each other, and that the ground lead pins 2-1-2a and 2-1-2b of the high-frequency line substrate 2-1 and the ground planes 2-2-2a and 2-2-2b of the printed circuit board 2-2 come into contact with each other.
- the signal lead pins 2-1-3a and 2-1-3b of the high-frequency line substrate 2-1 and the signal lines 2-2-3a and 2-2-3b of the printed circuit board 2-2 are connected by soldering or the like.
- the ground lead pins 2-1-2a and 2-1-2b of the high-frequency line substrate 2-1 and the ground planes 2-2-2a and 2-2-2b of the printed circuit board 2-2 are connected by soldering or the like.
- the signal line 2-2-3a of the printed circuit board 2-2 is electrically connected to the signal line 2-2-3b via the signal lead pin 2-1-3a, the signal line 2-1-6, and the signal lead pin 2-1-3b of the high-frequency line substrate 2-1.
- the ground plane 2-2-2a of the printed circuit board 2-2 is electrically connected to the ground plane 2-2-2b via the ground lead pin 2-1-2a, the ground plane 2-1-5, and the ground lead pin 2-1-2b of the high-frequency line substrate 2-1.
- the microstrip line 2-2-1 and the grounded coplanar line 2-2-7 formed on the upper surface of the printed circuit board 2-2 can be crossed three-dimensionally.
- the shapes of the ground lead pins 2-1-2a and 2-1-2b and of the signal lead pins 2-1-3a and 2-1-3b are determined in such a manner that the height of the ground lead pins 2-1-2a and 2-1-2b from the upper surface of the printed circuit board 2-2 is greater than that of the signal lead pins 2-1-3a and 2-1-3b at the contact portions between the signal lead pins 2-1-3a and 2-1-3b and the signal lines 2-2-3a and 2-2-3b, and the contact portions between the ground lead pins 2-1-2a and 2-1-2b and the ground planes 2-2-2a and 2-2-2b.
- the height of upper surfaces of the signal lead pins 2-1-3a and 2-1-3b at the connection portions between the signal lead pins 2-1-3a and 2-1-3b and the signal lines 2-1-6 is the same as the height of the upper surfaces of the ground lead pins 2-1-2a and 2-1-2b at the connection portions between the ground lead pins 2-1-2a and 2-1-2b and the ground planes 2-1-5.
- the signal lead pins 2-1-3a and 2-1-3b are shaped such that the upper surfaces thereof become lower in height from the high-frequency line substrate 2-1 toward the signal lines 2-2-3a and 2-2-3b, respectively.
- a high-frequency signal propagates from the printed circuit board 2-2 to the high-frequency line substrate 2-1 through the signal lead pin 2-1-3a. Furthermore, a high-frequency signal propagates from the high-frequency line substrate 2-1 to the printed circuit board 2-2 through the signal lead pin 2-1-3b. In such a case, since the signal lead pins 2-1-3a and 2-1-3b are exposed to the air, the capacitance between the signal lead pins 2-1-3a and 2-1-3b and the ground lead pins 2-1-2a and 2-1-2b decreases, and the characteristic impedance of the coplanar line tends to increase.
- the height of the ground lead pins 2-1-2a and 2-1-2b is made greater than that of the signal lead pins 2-1-3a and 2-1-3b.
- the ground lead pins 2-1-2a and 2-1-2b can enclose a line of electric force from the signal lead pins 2-1-3a and 2-1-3b so as not to leak the line of electric force to the adjacent signal lead pins 2-1-3a and 2-1-3b.
- crosstalk between the signal lead pins 2-1-3a and 2-1-3b and the adjacent signal lead pins 2-1-3a and 2-1-3b can be reduced.
- Fig. 7 is a diagram illustrating simulation results of reflection loss characteristics and passage loss characteristics of the grounded coplanar line in the high-frequency line connecting structure of the present embodiment.
- Fig. 8 is a diagram illustrating simulation results of crosstalk characteristics between adjacent channels and passage loss characteristics of the grounded coplanar line in the high-frequency line connecting structure of the present embodiment.
- Reference numeral 700 in Figs. 7 and 8 indicates the reflection loss characteristics
- reference numeral 701 indicates the passage loss characteristics
- Reference numeral 702 of Fig. 8 indicates a crosstalk between adjacent channels occurring when the shape of the ground lead pins 2-1-2a and 2-1-2b is identical to that of the signal lead pins 2-1-3a and 2-1-3b
- reference numeral 703 indicates a crosstalk between adjacent channels in the present embodiment.
- the grounded coplanar lines 2-2-7 divided at the intersection thereof with the microstrip line 2-2-1 are connected via the high-frequency line substrate 2-1. Also in the present embodiment, by making the height of the ground lead pins 2-1-2a and 2-1-2b at the connection portion with the printed circuit board 2-2 greater than that of the signal lead pins 2-1-3a and 2-1-3b, impedance matching can be achieved between the grounded coplanar line 2-2-7 of the printed circuit board 2-2 and the grounded coplanar line 2-1-9 of the high-frequency line substrate 2-1.
- the high-frequency line connecting structure capable of achieving favorable effects as shown in Figs. 7 and 8 and realizing low reflection loss characteristics, low passage loss characteristics, and low crosstalk characteristics in a wide band, can be obtained.
- FIG. 9 is an exploded perspective view showing, from above, a high-frequency line connecting structure according to the second embodiment of the present invention.
- Fig. 10 is an exploded perspective view showing the high-frequency line connecting structure of Fig. 9 from below.
- Fig. 11 is a bottom view of the high-frequency line substrate.
- Fig. 12 is a plan view of the high-frequency line substrate. Note that, in Fig. 11 , the descriptions of the signal lead pins and the ground lead pins are omitted in order to facilitate understanding of the configuration of the high-frequency line substrate. Also in Fig. 12 , the description of the DC block capacitor is omitted in order to facilitate understanding of the configuration of the high-frequency line substrate.
- Fig. 13 is a perspective view of the high-frequency line connecting structure in which a high-frequency line substrate is mounted on a printed circuit board, and a grounded coplanar line of the printed circuit board is connected by a grounded coplanar line of the high-frequency line substrate.
- Fig. 14 is a plan view of the high-frequency line connecting structure of Fig. 13
- Fig. 15 is a side view of the high-frequency line connecting structure of Fig. 13 .
- a printed circuit board 3-2 (first substrate) of the present embodiment includes a flat plate-shaped dielectric 3-2-5, signal lines 3-2-3a and 3-2-3b (first signal lines) made of conductors that are formed on an upper surface (first main surface) of the dielectric 3-2-5, ground planes 3-2-2a and 3-2-2b (first grounds) made of conductors that are formed on the upper surface of the dielectric 3-2-5 along the signal lines 3-2-3a and 3-2-3b, a ground plane 3-2-4 made of a conductor that is formed on a lower surface (second main surface) of the dielectric 3-2-5, and ground vias 3-2-6 made of conductors that connect the ground planes 3-2-2a and 3-2-2b to the ground plane 3-2-4.
- a plurality of the signal lines 3-2-3a are arranged in parallel.
- a plurality of the ground planes 3-2-2a are arranged on both sides of the signal lines 3-2-3a along the signal lines 3-2-3a.
- a plurality of the signal lines 3-2-3b are arranged in parallel.
- a plurality of ground planes 3-2-2b are arranged on both sides of the signal lines 3-2-3b along the signal lines 3-2-3b.
- the signal lines 3-2-3a and the signal lines 3-2-3b are divided at the position where a DC block capacitor is mounted as described hereinafter.
- the ground planes 3-2-2a and the ground planes 3-2-2b are divided at sections which are at the same position in the extension direction (X direction in Figs. 9 to 15 ) as the sections where the signal lines 3-2-3a and 3-2-3b are divided.
- ground planes 3-2-2a and 3-2-2b are electrically connected to the ground plane 3-2-4 by the ground vias 3-2-6 formed on the dielectric 3-2-5.
- the signal lines 3-2-3a and 3-2-3b and the ground planes 3-2-2a and 3-2-2b constitute a grounded coplanar line 3-2-7 (first high-frequency line) having the ground plane 3-2-4 on a rear surface of the substrate.
- the grounded coplanar line 3-2-7 is divided at a section where the high-frequency line substrate is mounted, in order to insert the DC block capacitor in series as described hereinafter.
- the high-frequency line substrate 3-1 (second substrate) includes a flat plate-shaped dielectric 3-1-1, signal lines 3-1-6a and 3-1-6b (second signal lines) made of conductors that are formed on a lower surface (first main surface) of the dielectric 3-1-1 facing the printed circuit board 3-2 so that the extension direction becomes parallel to the extension direction of the signal lines 3-2-3a and 3-2-3b when the high-frequency line substrate 3-1 is mounted on the printed circuit board 3-2, a ground plane 3-1-5 (second ground) made of a conductor that is formed on the lower surface of the dielectric 3-1-1 facing he printed circuit board 3-2 so as to surround the signal line 3-1-6a and 3-1-6b, signal lines 3-1-7a and 3-1-7b (third signal lines) made of conductors that are formed on an upper surface (second main surface) of the dielectric 3-1-1, and a ground plane 3-1-4 (third ground) formed on the upper surface of the dielectric 3-1-1 so as to surround the signal lines 3-1-7a and 3-1-7b.
- the high-frequency line substrate 3-1 further includes signal lead pins 3-1-3a and 3-1-3b made of conductors that are connected to the signal lines 3-1-6a and 3-1-6b respectively so as to be in contact with the signal lines 3-2-3a and 3-2-3b when the high-frequency line substrate 3-1 is mounted on the printed circuit board 3-2, ground lead pins 3-1-2a and 3-1-2b made of conductors that are connected to both ends of the ground plane 2-1-5 respectively so as to be in contact with the ground planes 3-2-2a and 3-2-2b when the high-frequency line substrate 3-1 is mounted on the printed circuit board 3-2, ground vias 3-1-8 made of conductors that are formed on the dielectric 3-1-1 and connect the ground plane 3-1-4 and the ground plane 3-1-5 to each other, vias 3-1-9a and 3-1-9b made of conductors that are formed on the dielectric 3-1-1 and connect the signal lines 3-1-6a and 3-1-6b and the signal lines 3-1-7a and 3-1-7b to each other, and a DC block capacitor 3-1-10 (electronic
- a plurality of the signal lines 3-1-6a are arranged in parallel on the lower surface of the high-frequency line substrate 3-1.
- a plurality of the signal lines 3-1-6b are arranged in parallel.
- the ground planes 3-1-5 are arranged so as to surround the signal lines 3-1-6a and 3-1-6b.
- the signal lines 3-1-6a and the signal lines 3-1-6b are divided in order to mount the DC block capacitor 3-1-10 on the opposite surface.
- the pitch of the signal lines 3-1-6a and 3-1-6b in the alignment direction (Y direction in FIGS. 9 to 15 ) is the same as the pitch of the signal lines 3-2-3a and 3-2-3b in the alignment direction.
- a plurality of the signal lines 3-1-7a are arranged in parallel on the upper surface of the high-frequency line substrate 3-1.
- a plurality of the signal lines 3-1-7b are arranged in parallel.
- the ground planes 3-1-4 are arranged so as to surround the signal lines 3-1-7a and 3-1-7b.
- the signal lines 3-1-7a and the signal lines 3-1-7b are divided in order to mount the DC block capacitor 3-1-10 on the upper surface of the high-frequency line substrate 3-1.
- the pitch of the signal lines 3-1-7a and 3-1-7b in the alignment direction (Y direction in Figs. 9 to 15 ) is the same as the pitch of the signal lines 3-1-6a and 3-1-6b in the alignment direction.
- the ground planes 3-1-5 are electrically connected to the ground planes 3-1-4 by the ground vias 3-1-8 formed on the dielectric 3-1-1.
- Ends of the signal lines 3-1-7a are electrically connected to one of the two parts of the second signal line (signal line 3-1-6a) via the via 3-1-9a formed in the dielectric 3-1-1.
- Ends of the signal lines 3-1-7b are electrically connected to the other one of the two parts of the second signal line (signal line 3-1-6b) via the vias 3-1-9b formed in the dielectric 3-1-1.
- the ground planes 3-1-5 are formed around the signal lines 3-1-6a and 3-1-6b, and the ground planes 3-1-4 are formed around the signal lines 3-1-7a and 3-1-7b.
- the signal lines 3-1-6a and 3-1-7a, the vias 3-1-9a, and the ground planes 3-1-4 and 3-1-5 constitute a pseudo-coaxial line structure 3-1-13a formed along a vertical direction of the high-frequency line substrate 3-1 (dielectric 3-1-1).
- the signal lines 3-1-6b and 3-1-7b, the vias 3-1-9b, and the ground planes 3-1-4 and 3-1-5 constitute a pseudo-coaxial line structure 3-1-13b.
- the signal lines 3-1-6a and 3-1-6b and the ground planes 3-1-5 constitute a grounded coplanar line 3-1-11 (second high-frequency line) having the ground planes 3-1-4 on the opposite side with the dielectric 3-1-1 therebetween.
- the grounded coplanar line 3-1-11 is divided into two in order to insert the DC block capacitor 3-1-10 in series.
- the signal lines 3-1-7a and 3-1-7b and the ground plane 3-1-4 constitute a grounded coplanar line 3-1-12 (third high-frequency line) having the ground plane 3-1-5 on the opposite side with the dielectric 3-1-1 therebetween.
- the grounded coplanar line 3-1-12 is divided into two in order to insert the DC block capacitor 3-1-10 in series.
- One electrode of the DC block capacitor 3-1-10 is soldered to one of the two divided sections of the third signal line (signal line 3-1-7a).
- the other electrode of the DC block capacitor 3-1-10 is soldered to the other part (signal line 3-1-7b) of the two divided sections of the third signal line.
- the DC block capacitor 3-1-10 is mounted on the high-frequency line substrate 3-1 and the DC block capacitor 3-1-10 is inserted in series into the grounded coplanar lines 3-1-11 and 3-1-12.
- Examples of a method for fixing the signal lead pins 3-1-3a and 3-1-3b to the signal lines 3-1-6a and 3-1-6b and a method for fixing the ground lead pins 3-1-2a and 3-1-2b to the ground planes 3-1-5 include brazing and soldering; needless to say, other fixing methods may be adopted.
- the high-frequency line substrate 3-1 and the printed circuit board 3-2 described above are individually prepared, the high-frequency line substrate 3-1 is mounted on the printed circuit board 3-2.
- the surface of the high-frequency line substrate 3-1 on which the signal lines 3-1-6a and 3-1-6b and the ground planes 3-1-5 are formed is placed face-down so the signal lines 3-1-6a, 3-1-6b, 3-1-7a, and 3-1-7b are positioned above the divided section of the signal lines 3-2-3a and 3-2-3b and the ground planes 3-1-5 and 3-1-4 are positioned on the divided section of the ground planes 3-2-2a and 3-2-2b, and then the high-frequency line substrate 3-1 is mounted on the printed circuit board 3-2.
- the high-frequency line substrate 3-1 is mounted on the printed circuit board 3-2 in such a manner that the signal lead pins 3-1-3a and 3-1-3b of the high-frequency line substrate 3-1 and the signal lines 3-2-3a and 3-2-3b of the printed circuit board 3-2 come into contact with each other, and that the ground lead pins 3-1-2a and 3-1-2b of the high-frequency line substrate 3-1 and the ground planes 3-2-2a and 3-2-2b of the printed circuit board 3-2 come into contact with each other.
- the signal lead pins 3-1-3a and 3-1-3b of the high-frequency line substrate 3-1 and the signal lines 3-2-3a and 3-2-3b of the printed circuit board 3-2 are connected by soldering or the like.
- the ground lead pins 3-1-2a and 3-1-2b of the high-frequency line substrate 3-1 and the ground planes 3-2-2a and 3-2-2b of the printed circuit board 3-2 are connected by soldering or the like.
- the signal line 3-2-3a of the printed circuit board 3-2 is electrically connected to the signal line 3-2-3b via the signal lead pin 3-1-3a, the signal line 3-1-6a, the via 3-1-9a, the signal line 3-1-7a, the DC block capacitor 3-1-10, the signal line 3-1-7b, the via 3-1-9b, the signal line 3-1-6b and the signal lead pin 3-1-3b of the high-frequency line substrate 3-1.
- the ground plane 3-2-2a of the printed circuit board 3-2 is electrically connected to the ground plane 3-2-2b via the ground lead pin 3-1-2a, the ground plane 3-1-5, and the ground lead pin 3-1-2b of the high-frequency line substrate 3-1.
- the high-frequency line substrate 3-1 on which the DC block capacitor 3-1-10 is mounted can be mounted on the printed circuit board 3-2, whereby the DC block capacitor 3-1-10 can be inserted in series into the grounded coplanar lines 3-2-7.
- the shapes of the ground lead pins 3-1-2a and 3-1-2b and of the signal lead pins 3-1-3a and 3-1-3b are determined in such a manner that the height of the ground lead pins 3-1-2a and 3-1-2b from the upper surface of the printed circuit board 3-2 is greater than that of the signal lead pins 3-1-3a and 3-1-3b at the contact portions between the signal lead pins 3-1-3a and 3-1-3b and the signal lines 3-2-3a and 3-2-3b, and the contact portions between the ground lead pins 3-1-2a and 3-1-2b and the ground planes 3-2-2a and 3-2-2b.
- the height of upper surfaces of the signal lead pins 3-1-3a and 3-1-3b at the connection portions between the signal lead pins 3-1-3a and 3-1-3b and the signal lines 3-1-6a and 3-1-6b is the same as the height of the upper surfaces of the ground lead pins 3-1-2a and 3-1-2b at the connection portions between the ground lead pins 3-1-2a and 3-1-2b and the ground planes 3-1-5.
- the signal lead pins 3-1-3a and 3-1-3b are shaped such that the upper surfaces thereof become lower in height from the high-frequency line substrate 3-1 toward the signal lines 3-2-3a and 3-2-3b.
- a high-frequency signal propagates from the printed circuit board 3-2 to the high-frequency line substrate 3-1 through the signal lead pin 3-1-3a. Furthermore, a high-frequency signal propagates from the high-frequency line substrate 3-1 to the printed circuit board 3-2 through the signal lead pin 3-1-3b. In such a case, since the signal lead pins 3-1-3a and 3-1-3b are exposed to the air, the capacitance between the signal lead pins 3-1-3a and 3-1-3b and the ground lead pins 3-1-2a and 3-1-2b decreases, and the characteristic impedance of the coplanar line tends to increase.
- the height of the ground lead pins 3-1-2a and 3-1-2b is made greater than that of the signal lead pins 3-1-3a and 3-1-3b.
- the ground lead pins 3-1-2a and 3-1-2b can enclose a line of electric force from the signal lead pins 3-1-3a and 3-1-3b so as not to leak the line of electric force to the adjacent signal lead pins 3-1-3a and 3-1-3b.
- crosstalk between the signal lead pins 3-1-3a and 3-1-3b and the adjacent signal lead pins 3-1-3a and 3-1-3b can be reduced.
- Fig. 16 is a diagram illustrating simulation results of reflection loss characteristics and passage loss characteristics of the grounded coplanar line in the high-frequency line connecting structure of the present embodiment
- Fig. 17 is a diagram showing simulation results of crosstalk characteristics between adjacent channels and passage loss characteristics of the grounded coplanar line in the high-frequency line connecting structure of the present embodiment.
- Reference numeral 600 in Figs. 16 and 17 indicates the reflection loss characteristics
- reference numeral 601 indicates the passage loss characteristics
- Reference numeral 602 of Fig. 17 indicates a crosstalk between adjacent channels occurring when the shape of the ground lead pins 3-1-2a and 3-1-2b is identical to that of the signal lead pins 3-1-3a and 3-1-3b
- reference numeral 603 indicates a crosstalk between adjacent channels in the present embodiment.
- the DC block capacitor 3-1-10 is inserted in series into the grounded coplanar line 3-2-7. Also in the present embodiment, by making the ground lead pins 3-1-2a and 3-1-2b at the connection portion with the printed circuit board 3-2 higher than the signal lead pins 3-1-3a and 3-1-3b, impedance matching can be achieved between the grounded coplanar line 3-2-7 of the printed circuit board 3-2 and the grounded coplanar lines 3-1-11 and 3-1-12 of the high-frequency line substrate 3-1.
- the high-frequency line connecting structure capable of achieving favorable effects as shown in Figs. 16 and 17 and realizing low reflection loss characteristics, low passage loss characteristics, and low crosstalk characteristics in a wide bandwidth, can be obtained.
- the DC block capacitor is described as an example of the electronic component to be inserted in series into the coplanar line, but an electronic component other than the DC block capacitor may be used.
- the dielectric 2-1-1, 2-1-7, 2-2-5, 3-1-1, and 3-2-5 constituting the grounded coplanar lines 2-1-9, 2-2-7, 3-1-11, 3-1-12, and 3-2-7 are low-loss ceramics such as alumina, but needless to say, liquid crystal polymer, polymide, quartz glass, or the like can be used instead.
- the connection portions between the signal lead pins 2-1-3a, 2-1-3b, 3-1-3a, and 3-1-3b and the signal lines 2-2-3a, 2-2-3b, 3-2-3a, and 3-2-3b, the connection portions between the ground lead pins 2-1-2a, 2-1-2b, 3-1-2a, and 3-1-2b and the ground planes 2-2-2a, 2-2-2b, 3-2-2a, and 3-2-2b, the connection portions between the signal lead pins 2-1-3a, 2-1-3b, 3-1-3a, and 3-1-3b and the signal lines 2-1-6, 3-1-6a, and 3-1-6b, and the connection portions between the ground lead pins 2-1-2a, 2-1-2b, 3-1-2a, and 3-1-2b and the ground planes 2-1-5 and 3-1-5 are typically gold-plated for the purpose of improving solder wettability.
- gold plating is not specified in particular because it is not the essence of the present invention.
- the present invention can be applied to a technique for three-dimensionally crossing high-frequency lines of a printed circuit board and inserting electronic components into the high-frequency lines of the printed circuit board.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Structure Of Printed Boards (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Combinations Of Printed Boards (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Waveguide Connection Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2019/042293 WO2021084601A1 (ja) | 2019-10-29 | 2019-10-29 | 高周波線路接続構造 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP4053992A1 EP4053992A1 (en) | 2022-09-07 |
EP4053992A4 EP4053992A4 (en) | 2023-08-02 |
EP4053992B1 true EP4053992B1 (en) | 2024-10-09 |
Family
ID=75715879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP19950886.2A Active EP4053992B1 (en) | 2019-10-29 | 2019-10-29 | High-frequency line connection structure |
Country Status (6)
Country | Link |
---|---|
US (1) | US12278413B2 (enrdf_load_stackoverflow) |
EP (1) | EP4053992B1 (enrdf_load_stackoverflow) |
JP (1) | JP7255702B2 (enrdf_load_stackoverflow) |
CN (1) | CN114631226B (enrdf_load_stackoverflow) |
CA (1) | CA3158938C (enrdf_load_stackoverflow) |
WO (1) | WO2021084601A1 (enrdf_load_stackoverflow) |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61259467A (ja) * | 1985-05-13 | 1986-11-17 | 富士通株式会社 | ジヤンパ−チツプ |
JPS6337082U (enrdf_load_stackoverflow) * | 1986-08-27 | 1988-03-10 | ||
JPH0714124B2 (ja) * | 1988-12-19 | 1995-02-15 | 三菱電機株式会社 | マイクロ波集積回路装置 |
US5270673A (en) * | 1992-07-24 | 1993-12-14 | Hewlett-Packard Company | Surface mount microcircuit hybrid |
JP3241139B2 (ja) * | 1993-02-04 | 2001-12-25 | 三菱電機株式会社 | フィルムキャリア信号伝送線路 |
KR20010095252A (ko) * | 2000-04-04 | 2001-11-03 | 도낀 가부시끼가이샤 | 고주파 전류 억제형 전자 부품 및 이를 위한 접합 와이어 |
CN100336218C (zh) * | 2003-08-25 | 2007-09-05 | 威盛电子股份有限公司 | 一种高频集成电路多排线打线结构及方法 |
CN1332445C (zh) * | 2003-10-09 | 2007-08-15 | 威盛电子股份有限公司 | 一种高频集成电路多排线打线结构 |
TWI360912B (en) * | 2008-04-25 | 2012-03-21 | Univ Nat Chiao Tung | Vertical transition structure |
CN102196657B (zh) * | 2010-03-09 | 2012-12-05 | 凌阳科技股份有限公司 | 线路基板 |
JP2012151365A (ja) * | 2011-01-20 | 2012-08-09 | Three M Innovative Properties Co | 基板及びそれを含む電子部品 |
JP2013012967A (ja) * | 2011-06-30 | 2013-01-17 | Hitachi Ltd | プリント基板伝送系 |
US9013891B2 (en) * | 2012-03-09 | 2015-04-21 | Finisar Corporation | 3-D integrated package |
US9627736B1 (en) * | 2013-10-23 | 2017-04-18 | Mark W. Ingalls | Multi-layer microwave crossover connected by vertical vias having partial arc shapes |
US9300092B1 (en) * | 2014-09-30 | 2016-03-29 | Optical Cable Corporation | High frequency RJ45 plug with non-continuous ground planes for cross talk control |
US9437558B2 (en) * | 2014-12-30 | 2016-09-06 | Analog Devices, Inc. | High frequency integrated circuit and packaging for same |
EP3477693A4 (en) * | 2016-06-27 | 2019-06-12 | NGK Electronics Devices, Inc. | HIGH FREQUENCY CERAMIC SUBSTRATE AND HIGH FREQUENCY SEMICONDUCTOR ELEMENTS |
-
2019
- 2019-10-29 JP JP2021553918A patent/JP7255702B2/ja active Active
- 2019-10-29 CN CN201980101823.4A patent/CN114631226B/zh active Active
- 2019-10-29 WO PCT/JP2019/042293 patent/WO2021084601A1/ja active IP Right Grant
- 2019-10-29 EP EP19950886.2A patent/EP4053992B1/en active Active
- 2019-10-29 CA CA3158938A patent/CA3158938C/en active Active
- 2019-10-29 US US17/772,446 patent/US12278413B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
CA3158938C (en) | 2023-08-29 |
EP4053992A4 (en) | 2023-08-02 |
WO2021084601A1 (ja) | 2021-05-06 |
US20220384928A1 (en) | 2022-12-01 |
US12278413B2 (en) | 2025-04-15 |
EP4053992A1 (en) | 2022-09-07 |
JPWO2021084601A1 (enrdf_load_stackoverflow) | 2021-05-06 |
JP7255702B2 (ja) | 2023-04-11 |
CA3158938A1 (en) | 2021-05-06 |
CN114631226A (zh) | 2022-06-14 |
CN114631226B (zh) | 2024-01-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20220416396A1 (en) | Vertical switched filter bank | |
US7212088B1 (en) | Electrical connecting element and a method of making such an element | |
US8491316B2 (en) | Connection terminal and transmission line | |
US11706851B2 (en) | RF circuit and enclosure having a micromachined interior using semiconductor fabrication | |
EP3477693A1 (en) | High-frequency ceramic substrate and high-frequency semiconductor element housing package | |
US20100259338A1 (en) | High frequency and wide band impedance matching via | |
WO1999062135A1 (en) | Wideband rf port structure using coplanar waveguide and bga i/o | |
US6803252B2 (en) | Single and multiple layer packaging of high-speed/high-density ICs | |
WO2011056842A1 (en) | Surface mount footprint with in-line capacitance | |
US20040051173A1 (en) | High frequency interconnect system using micromachined plugs and sockets | |
EP4053992B1 (en) | High-frequency line connection structure | |
EP2463961B1 (en) | System for forming electrical connections to conductive areas on a printed wiring board and method for forming such connections | |
KR100493090B1 (ko) | 배선접속장치 및 그 제조방법 | |
CN118215195A (zh) | 一种互联走线中的匹配结构 | |
WO2024177147A1 (ja) | 高周波接続線路 | |
US20210391633A1 (en) | Integrated circulator system | |
WO2025084976A1 (en) | Integrated circuit package | |
WO2002047172A1 (en) | A high frequency interconnect system using micromachined plugs and sockets | |
JP2002198712A (ja) | 導波管変換基板及び高周波モジュール | |
KR100634214B1 (ko) | 초고주파 통신회로에서의 와이어 본딩 방법 | |
JP2004186606A (ja) | 高周波用パッケージの実装構造 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE |
|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE |
|
17P | Request for examination filed |
Effective date: 20220422 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
DAV | Request for validation of the european patent (deleted) | ||
DAX | Request for extension of the european patent (deleted) | ||
A4 | Supplementary search report drawn up and despatched |
Effective date: 20230704 |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01P 1/20 20060101ALN20230628BHEP Ipc: H05K 3/34 20060101ALN20230628BHEP Ipc: H01R 12/52 20110101ALI20230628BHEP Ipc: H01P 5/02 20060101ALI20230628BHEP Ipc: H01P 3/00 20060101ALI20230628BHEP Ipc: H05K 1/02 20060101ALI20230628BHEP Ipc: H01P 1/04 20060101AFI20230628BHEP |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01P 1/20 20060101ALN20240318BHEP Ipc: H05K 3/34 20060101ALN20240318BHEP Ipc: H01R 12/52 20110101ALI20240318BHEP Ipc: H01P 5/02 20060101ALI20240318BHEP Ipc: H01P 3/00 20060101ALI20240318BHEP Ipc: H05K 1/02 20060101ALI20240318BHEP Ipc: H01P 1/04 20060101AFI20240318BHEP |
|
GRAP | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOSNIGR1 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: GRANT OF PATENT IS INTENDED |
|
RIC1 | Information provided on ipc code assigned before grant |
Ipc: H01P 1/20 20060101ALN20240418BHEP Ipc: H05K 3/34 20060101ALN20240418BHEP Ipc: H01P 5/02 20060101ALI20240418BHEP Ipc: H01P 3/00 20060101ALI20240418BHEP Ipc: H05K 1/02 20060101ALI20240418BHEP Ipc: H01P 1/04 20060101AFI20240418BHEP |
|
INTG | Intention to grant announced |
Effective date: 20240430 |
|
GRAS | Grant fee paid |
Free format text: ORIGINAL CODE: EPIDOSNIGR3 |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE PATENT HAS BEEN GRANTED |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: EP |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20240918 Year of fee payment: 6 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R096 Ref document number: 602019060359 Country of ref document: DE |
|
REG | Reference to a national code |
Ref country code: IE Ref legal event code: FG4D |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20241126 Year of fee payment: 6 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20241030 Year of fee payment: 6 |
|
REG | Reference to a national code |
Ref country code: LT Ref legal event code: MG9D |
|
REG | Reference to a national code |
Ref country code: NL Ref legal event code: MP Effective date: 20241009 |
|
REG | Reference to a national code |
Ref country code: AT Ref legal event code: MK05 Ref document number: 1731617 Country of ref document: AT Kind code of ref document: T Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20250209 Ref country code: PT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20250210 Ref country code: HR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FI Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: BG Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: ES Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: NO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20250109 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LV Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 Ref country code: AT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20250110 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: PL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: RS Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20250109 |
|
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SM Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: MC Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
REG | Reference to a national code |
Ref country code: DE Ref legal event code: R097 Ref document number: 602019060359 Country of ref document: DE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20241029 Ref country code: BE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20241031 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: EE Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CH Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20241031 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: RO Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SK Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: CZ Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 20241009 |
|
REG | Reference to a national code |
Ref country code: BE Ref legal event code: MM Effective date: 20241031 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |