EP4031954A1 - Pré-régulateur pour un ldo - Google Patents

Pré-régulateur pour un ldo

Info

Publication number
EP4031954A1
EP4031954A1 EP20865618.1A EP20865618A EP4031954A1 EP 4031954 A1 EP4031954 A1 EP 4031954A1 EP 20865618 A EP20865618 A EP 20865618A EP 4031954 A1 EP4031954 A1 EP 4031954A1
Authority
EP
European Patent Office
Prior art keywords
coupled
pfet
supply voltage
gate
nfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP20865618.1A
Other languages
German (de)
English (en)
Other versions
EP4031954A4 (fr
Inventor
Mehedi Hassan
Grant Evan FALKENBURG
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of EP4031954A1 publication Critical patent/EP4031954A1/fr
Publication of EP4031954A4 publication Critical patent/EP4031954A4/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/468—Regulating voltage or current wherein the variable actually regulated by the final control device is dc characterised by reference voltage circuitry, e.g. soft start, remote shutdown
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/563—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/59—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices including plural semiconductor devices as final control devices for a single load
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/18—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using Zener diodes
    • G05F3/185—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using Zener diodes and field-effect transistors

Definitions

  • a wide input voltage range is desirable to allow a variety of power sources.
  • a system powered using an alternating current (AC) with conversion to direct current (DC) and a battery backup requires that the device to be operational from a 15 V AC/DC supply as well as from a battery discharged to 2 V.
  • the power source is typically connected to an integrated circuit (IC) that manages the power for the various amplifiers and drivers in the device.
  • IC integrated circuit
  • Disclosed embodiments provide a pre-regulator circuit that regulates upper supply voltages that are above a regulation threshold voltage, e.g., 4.0 volts, using a simple clamp diode on the gate of the pass transistor. Clamping the gate ensures that the output voltage will not harm downstream circuits.
  • a bypass switch allows upper supply voltages below the regulation threshold voltage to bypass the regulator.
  • a comparison circuit receives the upper supply voltage and an internally generated reference voltage that are used to open and close the bypass switch.
  • the pre-regulator circuit is simple and may extend an LDO’s input voltage without the need for high voltage devices in the LDO.
  • an embodiment of an electronic device includes a voltage regulator circuit comprising a power N-type field effect transistor (NFET) coupled between an upper supply voltage and a pre-regulator output node and a current source coupled in series with a diode element between the upper supply voltage and a lower supply voltage, a gate of the power NFET being coupled to a first node between the current source and the diode element; a bypass circuit comprising a power P-type field effect transistor (PFET) coupled between the upper supply voltage and the pre-regulator output node; and a comparison circuit coupled to turn the bypass circuit off when the upper supply voltage is greater than a regulation threshold voltage.
  • NFET power N-type field effect transistor
  • an embodiment of a method of operating a pre-regulator circuit for a low dropout (LDO) regulator includes receiving, at an input node, an upper supply voltage having a range between a lower limit and an upper limit, the upper limit and the lower limit having a difference of at least ten volts; determining whether the upper supply voltage is greater than a regulation threshold voltage; when the upper supply voltage is not greater than the regulation threshold voltage, passing the upper supply voltage directly to a pre-regulator output node that is coupled to the LDO regulator; and when the upper supply voltage is greater than the regulation threshold voltage, regulating the upper supply voltage to provide a regulated output voltage to the pre-regulator output node.
  • LDO low dropout
  • FIG. 1 depicts a high-level block diagram of a pre-regulator circuit according to an embodiment of the disclosure
  • FIG. 2 depicts an implementation of a pre-regulator circuit according to an embodiment of the disclosure
  • FIG. 2A depicts an implementation of a pre-regulator circuit according to an embodiment of the disclosure
  • FIG. 3 depicts the input and output voltages as the pre-regulator circuit powers up with an input voltage of 4 V and a load is applied according to an embodiment of the disclosure
  • FIG. 4 depicts the input and output voltages as the pre-regulator circuit powers up with an input voltage of 15 V and a load is applied according to an embodiment of the disclosure;
  • FIG. 5 depicts the quiescent current of the pre-regulator circuit at both low and high temperatures when operating at an input voltage of 4 V according to an embodiment of the disclosure;
  • FIG. 6 depicts the quiescent current of the pre-regulator circuit at both low and high temperatures when operating at an input voltage of 15 V according to an embodiment of the disclosure
  • FIG. 7 depicts a block diagram of a smoke detector that utilizes a pre-regulator circuit according to an embodiment of the disclosure
  • FIG. 8 depicts a method of operating a pre-regulator circuit for an LDO regulator according to an embodiment of the disclosure
  • FIG. 9A depicts a smoke detector operating with an LDO according to the prior art
  • FIG. 9B depicts a smoke detector operating with a stepdown DC-DC converter according to the prior art.
  • the batteries When batteries are utilized, either as the main power supply or as a backup power supply, the batteries may be a 9 volt battery or alternatively, two AA batteries may be required to supply 3 volts.
  • An IC chip connected to the input power supply needs to be able to handle this wide range of supply voltages without enduring any reliability issues.
  • a smoke detector must be designed as a low power device.
  • UL Underwriters Laboratories
  • a non- AC powered smoke detector must have a 10-year lifetime using a 3.3 V lithium battery for household use. Additionally, the circuit must maintain high reliability, even with the potential variability in the input power supply.
  • FIGS. 9A and 9B depict two such prior art solutions.
  • prior art smoke detector 900A includes an LDO regulator 902 that is coupled to receive AC/DC power supply 904 and battery power supply 906 at input node 908 as alternative upper supply voltages.
  • LDO regulator 902 is also coupled to provide an internal supply voltage Vinternal at an output node 910 that is coupled to a smoke detector analog front end (AFE) 912, which can include internal circuits, amplifiers, drivers, etc.
  • AFE smoke detector analog front end
  • LDO regulator 902 includes a power P-type field effect transistor (PFET) Ma that is coupled between the input node 908 and the output node 910 to regulate the internal supply voltage Vinternal that is provided at an output node 910.
  • a differential amplifier 914 is coupled to the input supply voltage and is capacitively coupled to the output node 910.
  • the differential amplifier 914 has a non-inverting input that is coupled to receive a reference voltage Vref.
  • An inverting input of the differential amplifier 914 is coupled to receive feedback from output node 910 through a resistor divider 918 that is coupled between the output node 910 and the lower supply voltage, which can be a ground plane.
  • prior art smoke detector 900B includes a DC-DC converter 932 that is coupled to receive AC/DC power supply 934 and battery power supply 936 at input node 938 as alternative upper supply voltages.
  • DC-DC converter 932 is also coupled to provide an internal supply voltage Vinternal at an output node 940 that is coupled to a smoke detector AFE 942, which again can include internal circuits, amplifiers, drivers, etc.
  • DC-DC converter 932 includes a high-side power PFET Mhs coupled in series with a low-side power N-type field effect transistor (NFET) Mis between the input node 938 and the lower supply voltage, with a switch node SW positioned between high-side power PFET Mhs and low-side power NFET Mis.
  • An inductor Ll is coupled between switch-node SW and the output node 940, with a capacitor Cout coupled between output node 940 and a lower supply voltage, which can be a ground plane.
  • a logic circuit 944 is coupled to high-side drivers 946, which drive high-side power PFET Mhs and is also coupled to low-side drivers 948, which drive low-side power NFET Mis.
  • An LDO regulator or DC-DC converter circuit is a dedicated circuit that requires precision reference voltages and bias currents, as well as an amplifier. These requirements cause current consumption to go up. Designing either LDO regulator 902 or DC-DC converter 932 to handle the necessary wide voltage range requires additional silicon area, higher pin counts, and greater power consumption. Additionally, if the output of the LDO regulator 902 or DC-DC converter 932 is fixed to 2 V as a lowest potential power supply, converting an input supply voltage from 15 V to 2 V is highly inefficient. Even converting the input supply voltage from 3.6 V means losing headroom that could be otherwise used. As will be seen below, the disclosed pre-regulator circuit addresses this latter issue by providing a bypass circuit for lower values of the upper supply voltage while regulating the upper supply voltage once the upper supply voltage rises above a regulation threshold voltage.
  • FIG. 1 provides a high-level block diagram of a system 100 that includes a pre regulator circuit 102 that operates to receive the wide range of input voltages and provides an output voltage that operates within a much lower range.
  • Pre-regulator circuit 102 does not provide as great a precision at higher input voltages as either LDO regulator 902 or DC-DC converter 932, but instead utilizes a simple circuit that provides an output voltage that is low enough to prevent damage to the internal circuity 104, but does not starve the circuits for power.
  • An LDO circuit following pre-regulator circuit 102 does not require high voltage devices and can be designed for low voltages only.
  • Pre-regulator circuit 102 is coupled between a pre-regulator input node 110, which provides the upper supply voltage VCC, and the lower supply voltage and is also coupled to provide a pre-regulator output voltage Vprereg to internal circuity 104 for the system 100.
  • the internal circuitry 104 can again contain, e.g., an LDO, drivers, etc.
  • a voltage regulator circuit 101 that includes a power NFET MNOUT operates during a regulation mode to provide a regulated output current when the upper supply voltage VCC is greater than a regulation threshold voltage, which in one embodiment is about 4 V.
  • Voltage regulator circuit 101 also includes a current source CS1, a first capacitor Cl and a diode element 107.
  • Power NFET MNOUT is coupled between the upper supply voltage VCC and a pre-regulator output node 103.
  • Current source CS1 is coupled in series with first capacitor Cl between the upper supply voltage VCC and the lower supply voltage, e.g., the ground plane, with a gate of power NFET MNOUT being coupled to a first node 105 that is between current source CS1 and first capacitor Cl.
  • a diode element 107 is coupled between the gate of power NFET MNOUT and the lower supply voltage and during regulation mode will regulate the pre-regulator output voltage Vprereg to a value that is equal to the voltage drop across the diode element minus the gate/source voltage Vgs of power NFET MNOUT.
  • the power NFET MNOUT is a laterally-diffused metal-oxide semiconductor field-effect transistor (LDMOSFET).
  • a bypass circuit to avoid the voltage regulation of power NFET MNOUT is provided by power PFET MPOUT, which is also coupled between the upper supply voltage VCC and the pre-regulator output node 103.
  • the bypass circuit also includes a comparison circuit that can determine when to turn off the power PFET MPOUT and may further include a pullup circuit 108 to ensure that power PFET MPOUT is turned off quickly.
  • Comparison circuit 106 is powered by the upper supply voltage VCC and also receives an internal reference voltage Vintref.
  • a first output of comparison circuit 106 is coupled to a gate of output PFET MPOUT.
  • pullup circuit 108 is coupled between the upper supply voltage VCC and the gate of power PFET MPOUT and receives a second output of comparison circuit 106.
  • Comparison circuit 106 compares the upper supply voltage VCC to the internal reference voltage Vintref and may compare either voltages or associated currents.
  • the upper supply voltage VCC is less than or equal to a regulation threshold voltage
  • power PFET MPOUT is turned on and passes upper supply voltage VCC to pre-regulator output node 103 with very little voltage lost. This is accomplished by making power PFET MPOUT a large, low on-resistance transistor.
  • power PFET MPOUT is turned off so that pre-regulator output voltage Vprereg is regulated by power NFET MNOUT.
  • FIG. 2 depicts a pre-regulator circuit 200, which can be used as a specific implementation of pre-regulator circuit 102.
  • a power NFET MNOUT which in at least one embodiment is an LDMOSFET, is coupled between a pre regulator input node 201, which provides the upper supply voltage, and the pre-regulator output node 214 and will regulate the voltage in a regulation mode, as will be discussed below.
  • a power PFET MPOUT is also coupled between the pre-regulator input node 201 and the pre regulator output node 214 to provide a bypass circuit that bypasses regulation through power NFET MNOUT when the upper supply voltage is below a regulation threshold voltage.
  • a first resistor R1 is coupled in series with a second resistor R2 and a first NFET MN1 between the upper supply voltage VCC and the lower supply voltage.
  • the gate and drain of first NFET MN1 are coupled together so that first NFET MN1 acts as a diode.
  • second resistor R2 is sized to have a resistance that is 4.6 times the resistance of first resistor Rl.
  • a first PFET MPl is coupled in series with a second NFET MN2 between the upper supply voltage VCC and the lower supply voltage.
  • the gate of second NFET MN2 is coupled to the gate of first NFET MN1 and the gate and drain of first PFET MPl are coupled together.
  • Pre-regulator circuit 200 also includes a second PFET MP2 coupled in series with a diode element that consists of a first Zener diode Z1 between the upper supply voltage VCC and the lower supply voltage, with the gate of power NFET MNOUT coupled to a first node 202 that is between second PFET MP2 and first Zener diode Z1 to receive a gate voltage of Vz.
  • the current mirror formed by first PFET MPl and second PFET MP2 forms the current source CS1 of FIG. 1.
  • a first capacitor Cl is coupled between the gate of power NFET MNOUT and the lower supply voltage and a second capacitor C2 is coupled between the pre regulator output node 214 and the lower supply voltage.
  • a third PFET MP3 is coupled in series with a switching PFET MPSW and a third NFET MN3 between the upper supply voltage VCC and the lower supply voltage.
  • a gate of switching PFET MPSW is coupled to a second node 204 between first resistor Rl and second resistor R2 to receive a gate voltage Vb and the gate and drain of third NFET MN3 are coupled together.
  • the gate of second PFET MP2 and the gate of third PFET MP3 are each coupled to the gate of first PFET MPl.
  • a fourth PFET MP4 is coupled in series with a fourth NFET MN4 between the upper supply voltage and the lower supply voltage.
  • the gate of fourth PFET MP4 is coupled to the gate of first PFET MP1 and the gate of fourth NFET is coupled to the gate of third NFET MN3.
  • a fifth PFET MP5 is coupled in series with a fifth NFET MN5 between the upper supply voltage VCC and the lower supply voltage with a fourth node 208 lying between fifth PFET MP5 and fifth NFET MN5.
  • a gate of fifth PFET MP5 is coupled to the gate of first PFET MPl and the gate of fifth NFET MN5 is coupled to a third node 206 between fourth PFET MP4 and fourth NFET MN4 to receive a gate voltage Vpdn.
  • a second Zener diode Z2 is coupled between the gate of fifth NFET MN5 and the lower supply voltage.
  • the gate of power PFET MPOUT is coupled to a fourth node 208 between fifth PFET MP5 and fifth NFET MN5 to receive a gate voltage Vg.
  • a third Zener diode Z3 and a third resistor R3 are each coupled between the upper supply voltage and the gate of power PFET MPOUT.
  • Fifth current 15 will flow through fourth PFET MP4 and fourth NFET MN4 when switching transistor MPSW is turned on and a sixth current 16 will flow through fifth PFET MP5 when fifth NFET MN5 is turned on.
  • a sixth PFET MP6 and a seventh PFET MP7 are coupled in series with a sixth NFET MN6 between the upper supply voltage and the lower supply voltage.
  • a gate of the sixth PFET MP6 is coupled to the gate of the first PFET MPl and the gate of sixth NFET MN6 is coupled to the gate of third NFET MN3.
  • An eighth PFET MP8, a ninth PFET MP9 and a tenth PFET MP10 are each diode coupled and are further coupled in series with a seventh NFET MN7 between the upper supply voltage and the lower supply voltage.
  • the gate of seventh NFET MN7 is coupled to the gate of third NFET MN3 and the gate of seventh PFET MP7 is coupled to a fifth node 210 between the tenth PFET MP10 and the seventh NFET MN7.
  • a seventh current 17 flows through sixth PFET MP6, seventh PFET MP7 and sixth NFET MN6.
  • eighth current flows through eighth PFET MP8, ninth PFET MP9, tenth PFET MPIO and seventh NFET MN7.
  • an eleventh PFET MPll is coupled between the upper supply voltage and the fourth node 208, with a gate of the eleventh PFET MP11 being coupled to a sixth node 212 between sixth PFET MP6 and seventh PFET MP7.
  • the first current II is a function of the gate/source voltage Vgs of first NFET MN1, the resistance of resistors R1 and R2 and the upper supply voltage VCC. Consequently, in low voltage applications, the first current II is small and helps meet the low power requirement.
  • the second current 12 through eighth current 18 are also related to first current II through the various current mirrors and hence remain low when upper supply voltage VCC is low.
  • the circuit can be generally be divided into four sections: a first section 222 that includes first current II and second current 12, a second section 224 that includes third current 13, fourth current 14 and fifth current 15, a third section 226 that includes sixth current 16 and both output circuits, and a fourth section 228 that includes seventh current 17 and eighth current 18.
  • a first section 222 that includes first current II and second current 12
  • a second section 224 that includes third current 13, fourth current 14 and fifth current 15
  • a third section 226 that includes sixth current 16 and both output circuits
  • a fourth section 228 that includes seventh current 17 and eighth current 18.
  • the simple circuit that is active during low-voltage implementations may use less than 500 nA of power.
  • first current II and second current 12 flow through their respective circuits.
  • Fourth PFET MP4 is on and pulls up third node 206, turning on fifth NFET MN5, so that sixth current 16 flows through.
  • upper supply voltage VCC is less than the regulation threshold voltage
  • the difference between the voltage drop across third PFET MP3 and the voltage drop across resistor R1 is such that the gate/source voltage Vgs of switching PFET MPSW is not great enough to allow a substantial current to flow. This means that the current mirror of third NFET MN3 and fourth NFET MN4 is not turned on, and therefore fourth current 14 does not flow.
  • the gate voltage Vb is equal to (VCC-I1*R1), where R1 here represents the resistance of resistor Rl.
  • R1 here represents the resistance of resistor Rl.
  • the voltage across R1 that is required to turn on switching PFET MPSW is Vgsmpsw+Vdsatmp3, were Vgsmpsw is the gate/source voltage of switching PFET MPSW and Vdsatmp3 is the drain/source voltage in saturation of third PFET MP3.
  • VCC the gate/source voltage on switching PFET MPSW is not high enough to turn on switching PFET MPSW.
  • Third NFET MN3, fourth NFET MN4, sixth NFET MN6 and seventh NFET MN7 are all off, preventing fourth current 14, fifth current 15, seventh current 17 and eighth current 18 from flowing. While fourth NFET MN4 is off, the fourth PFET MP4 pulls up the third node 206 and fifth NFET MN5 turns on. Fifth NFET MN5 has a higher gate/source voltage than fifth PFET MP5, so fourth node 208 and the gate voltage Vg on power PFET MPOUT are pulled low, fully turning on power PFET MPOUT. [0039] As the voltage of VCC increases, first current II increases and I1*R1 increases accordingly.
  • Power NFET MNOUT is able to provide a pre regulator output voltage Vprereg that is equal to the voltage of Zener diode Z1 minus the gate/source voltage Vgs of power NFET MNOUT.
  • the Zener voltage is typically 5V and the gate/source voltage Vgs of power NFET MNOUT is about one volt, so that the pre-regulator output voltage Vprereg through power NFET MNOUT is regulated to about 4 V.
  • the pre-regulator output voltage Vprereg through power NFET MNOUT may in some instances be as high as about 5.4 V.
  • the maximum gate voltage allowed in the internal circuitry of the smoke alarm is about 6 V, so that the pre-regulator output voltage Vprereg does not need to be controlled quite as tightly as might otherwise be necessary.
  • the sixth NFET MN6 and seventh NFET MN7 are also turned on, activating a clamp circuit that includes sixth through eleventh PFETs MP6-MP11.
  • Each of eighth PFET MP8, ninth PFET MP9 and tenth PFET MPIO is diode-coupled, so that the voltage at fifth node 210 is equal to VCC-3*Vgs.
  • the voltage on fifth node 210 is provided to the gate of seventh PFET MP7, turning on seventh PFET MP7 to provide a voltage of VCC-2*Vgs at sixth node 212, which then turns on eleventh PFET MP11.
  • Turning on eleventh PFET MP11 assists in pulling up fourth node 208 so that gate voltage Vg goes high and ensures that power PFET MPOUT is turned off quickly.
  • Pre-regulator circuit 200A in FIG. 2A depicts one such variation.
  • Pre-regulator circuit 200A is the same as pre-regulator circuit 200 except that the use of Zener diode Z1 as the diode element 107 has been replaced by stacked diode-connected NFETs MN8-MN12 which provide approximately the same limitations to the gate-voltage as does Zener diode Zl, so that pre-regulator circuit 200 A provides the same benefits as does pre-regulator circuit 200.
  • the voltage necessary for the internal circuitry is very low.
  • Traditional LDOs are generally designed to work across a wide range of both input and output voltages. This is in contrast to the present application in which a wide input range and a low output range are needed.
  • the disclosed pre-regulator e.g., any of pre-regulator circuit 102, pre-regulator circuit 200, and pre-regulator 200A, is able to stepdown voltage with a simpler design.
  • the power PFET acts as a switch and transfers VCC directly to the pre-regulator output node
  • the pre- regulator output is controlled by the gate voltage Vz on power NFET MNOUT, which is limited by a Zener voltage; the pre-regulator output voltage Vprereg is equal to gate voltage Vz minus the gate/source voltage Vgs of power NFET MNOUT and once the output reaches this value, the regulated output remains constant for an upper supply voltage VCC as high as 15 V.
  • FIG. 3 depicts a graph 300 of the simulated values of upper supply voltage VCC and pre-regulator output voltage Vprereg as the circuit is turned on with an upper supply voltage of 4 V and then as a 30 mA load is applied.
  • the simulations include variations across temperature and transistor parameters. As the circuit is turned on, upper voltage supply VCC climbs steadily in all embodiments until VCC reaches 4 V. Different simulations require slightly different amounts of time for pre-regulator output voltage Vprereg to begin to rise, although all of the simulations quickly accomplish a steady rise to a pre-regulator output voltage Vprereg of 4 V. When a 30 mA load is applied, a small amount of separation of pre-regulator output voltage Vprereg is seen.
  • the pre-regulator output voltage Vprereg ranged between a minimum of 3.9348 V to a maximum of 3.956 V, with a typical voltage of 3.95 V.
  • the pre-regulator output voltage Vprereg ranged between a minimum of 3.999 V to a maximum of 4.0 V, with a typical voltage of 3.999 V.
  • FIG. 4 depicts a graph 400 of the simulated values of upper supply voltage VCC and pre-regulator output voltage Vprereg as the circuit is turned on with an upper supply voltage of 15 V and then again as a 30 mA load is applied.
  • the simulations again include variations across temperature and transistor parameters.
  • upper voltage supply VCC climbs steadily in all embodiments until VCC reaches 15 V.
  • the steady state of pre-regulator output voltage Vprereg shows greater variation at the maximum voltage than when the upper supply voltage is simply passed through, both before and after application of a 30 mA load.
  • the pre-regulator output voltage Vprereg ranged between a minimum of 3.935 V to a maximum of 3.956 V, with a typical voltage of 3.945 V.
  • the pre-regulator output voltage Vprereg ranged between a minimum of 3.999 V to a maximum of 4.0 V, with a typical voltage of 3.999 V.
  • FIG. 5 depicts graph 500 of the total quiescent current consumed by pre-regulator circuit 200 across variations in process and temperatures ranging from 0-85°C at an upper supply voltage VCC of 4 V.
  • the low temperature range is shown on the left-hand side of graph 500 where the quiescent current averaged 1.13 mA and the high temperature range is shown on the right-hand side, where the quiescent current averaged 2.62 mA.
  • a typical quiescent current is 1.66 pA.
  • FIG. 6 similarly depicts a graph 600 of the total quiescent current consumed by pre regulator circuit 200 across variations in process and temperatures ranging from 0-85°C at an upper supply voltage VCC of 15 V.
  • the low temperature range is shown on the left-hand side of graph 600 where the quiescent current averaged 5.88 pA and the high temperature range is shown on the right-hand side, where the quiescent current averaged 9.88 pA.
  • a typical quiescent current at an upper supply voltage VCC of 15 V is 7.63 pA. While the quiescent current at 15 V is not as favorable as the quiescent current at 4 V, when the circuit is receiving 15 V, the system is generally using mains power and the need to minimize the current is not as critical as when battery power is being employed.
  • FIG. 7 depicts a block diagram of an electronic device that is a smoke detector 700 incorporating a pre-regulator circuit (pre-LDO) 720 according to an embodiment of the disclosure.
  • Smoke detector 700 includes an IC chip 701 on which a number of circuits are implemented, including pre-regulator circuit 720, which can be implemented using the circuits shown in one of pre-regulator circuit 102 and the pre-regulator circuit 200 and the method(s) as will be discussed in FIG. 8.
  • IC chip 701 also includes a carbon monoxide detection circuit 704, a photo-detection circuit 706, an optional ion detection circuit 708, and a horn driver 721.
  • photo-detection circuit 706 also includes a first light-emitting diode (LED) driver 712 and a second LED driver 714.
  • Carbon monoxide detection circuit 704 is coupled to a first plurality of pins 705; photo-detection circuit 706 is coupled to a second plurality of pins 707; and horn driver 721 is coupled to a third plurality of pins 711.
  • Multiplexor 710 which is coupled to a fifth pin P5 that is part of a fourth plurality of pins 713, can receive input signals from each of carbon monoxide detection circuit 704 and photo-detection circuit 706.
  • ion detection circuit 708 When optional ion detection circuit 708 is provided, ion detection circuit 708 is coupled to a fifth plurality of pins 709 and multiplexor 710 is also coupled to receive input signals from ion detection circuit 708.
  • Horn driver 721 can be provided to drive a horn 729.
  • first pin PI second pin P2, third pin P3 and fourth pin P4.
  • a pre-regulator circuit 720 is coupled to first pin PI, which is also coupled to an AC/DC converter 732. Pre-regulator circuit 720 is also coupled to second pin P2 (coupling not specifically shown) to receive a lower supply voltage.
  • a DC/DC boost converter 702 is coupled to third pin P3 to receive power from battery BAT through an inductor L and is also coupled to fourth pin P4 to provide a boosted output voltage Vbst from the battery power.
  • Fourth pin P4 is also coupled to first pin PI, which provides the boosted output voltage Vbst to pre-regulator circuit 720 when battery power is relied on.
  • Second pin P2 is coupled to a ground plane, although the internal connections to the circuits are not specifically shown.
  • Pre-regulator circuit 720 provides a pre-regulator output voltage Vprereg, which will be used to provide the gate-driver supply voltage Vcc for internal circuits on IC chip 701.
  • the pre regulator output voltage Vprereg can be distributed to microcontroller (MCU) LDO regulator 716, internal LDO regulator 718 and Vcc divider 719.
  • MCU microcontroller
  • MCU LDO regulator 716 provides a supply voltage to MCU 730 and the I/O buffers (not specifically shown); internal LDO regulator 718 provides a supply voltage to internal circuits such as the data core and the analog blocks, e.g., the carbon monoxide detection circuit 704, photo-detection circuit 706 and ion detection circuit 708; and Vcc divider 719 provides a supply voltage to multiplexor 710.
  • carbon monoxide detection circuit 704 is coupled to carbon monoxide sensor 722 through the first plurality of pins 705; photo-detection circuit 706, which can include first LED driver 712 and second LED driver 714, is coupled to photo sensor 724 and LEDs 726 through the second plurality of pins 707; ion detection circuit 708 is coupled to ion sensor 728 through the fifth plurality of pins 709; and horn driver 721 is coupled to a horn 729 through the third plurality of pins 711.
  • the carbon monoxide sensor 722, photo sensor 724 and ion sensor 728 collect the information needed to detect smoke and carbon monoxide in the area, while horn 729 provides a loud audible alert when smoke or carbon monoxide are detected.
  • IC chip 701 is also coupled to microcontroller 730 though the fourth plurality of pins 713, with IC chip 701 supplying both power and information to microcontroller 730 and receiving instructions to control various aspects of operation of smoke detector 700.
  • the fifth pin P5 which is part of the fourth plurality of pins 713, provides a path for the multiplexor 710 to provide the outputs of the carbon monoxide detection circuit 704, photo-detection circuit 706, and ion detection circuit 708 to MCU 730.
  • FIG. 8 depicts a method 800 of operating a pre-regulator circuit for an LDO regulator.
  • the method begins with receiving 805, at a power input node, an upper supply voltage that has a range between a lower limit and an upper limit that have a difference of at least ten volts.
  • the lower limit is about 3.3 V and the upper limit is about 15 V, so that the difference is about 12 volts.
  • the method determines 810 whether the upper supply voltage is greater than a regulation threshold voltage. In one embodiment, the regulation threshold voltage is about 4 V.
  • the upper supply voltage is passed 815 directly to a power output node coupled to provide power to the LDO regulator.
  • the method regulates 820 the upper supply voltage to provide a regulated voltage to the power output node
  • Applicants have disclosed an electronic device and a method that extends an LDO regulator’s input voltage without the need for high voltage devices by providing a pre-regulator circuit.
  • the electronic device may be a circuit, an IC chip, or a system, e.g., a smoke detector.
  • the pre-regulator circuit consumes very little current when low-voltage battery input is provided, is very suitable for battery applications and provides maximum battery voltage to the LDO regulator.
  • the pre-regulator circuit does not require an external bias current or reference voltage to function.
  • the same resistor that generates the bias current can be used to switch from a PMOS pass FET to an LDMOSFET when VCC crosses a regulation threshold voltage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Dc-Dc Converters (AREA)

Abstract

La présente invention concerne un dispositif électronique comprenant un circuit régulateur de tension (102) présentant un NFET de puissance (MNOUT) couplé entre une tension d'alimentation supérieure (VCC) et un nœud de sortie de pré-régulateur (103) et une source de courant (CS1, MP1 avec MP2) couplée en série à un élément de diode (107, Zl) entre la tension d'alimentation supérieure et une tension d'alimentation inférieure (par exemple, un plan de masse). Une grille du NFET de puissance est couplée à un premier nœud (105) entre la source de courant et l'élément de diode. Un circuit de dérivation (106, 108, MPOUT) inclut un PFET de puissance (MPOUT) couplé entre la tension d'alimentation supérieure et le nœud de sortie de pré-régulateur. Un circuit de comparaison (106) est couplé pour désactiver le circuit de dérivation lorsque la tension d'alimentation supérieure est supérieure à une tension de seuil de régulation (par exemple d'environ 4 V).
EP20865618.1A 2019-09-20 2020-09-21 Pré-régulateur pour un ldo Pending EP4031954A4 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201962903632P 2019-09-20 2019-09-20
US16/674,577 US10942536B1 (en) 2019-09-20 2019-11-05 Pre-regulator for an LDO
PCT/US2020/051738 WO2021055923A1 (fr) 2019-09-20 2020-09-21 Pré-régulateur pour un ldo

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EP4031954A1 true EP4031954A1 (fr) 2022-07-27
EP4031954A4 EP4031954A4 (fr) 2022-11-16

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JP (1) JP2022549254A (fr)
KR (1) KR20220061134A (fr)
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WO (1) WO2021055923A1 (fr)

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CN114189148B (zh) * 2022-01-21 2022-10-21 钰泰半导体股份有限公司 功率转换器及其控制方法
TWI799145B (zh) * 2022-02-18 2023-04-11 瑞昱半導體股份有限公司 D類放大器驅動電路
US12001235B2 (en) * 2022-03-30 2024-06-04 Texas Instruments Incorporated Startup circuit for high voltage low power voltage regulator

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JPH03100814A (ja) * 1989-09-14 1991-04-25 Fukushima Nippon Denki Kk 定電圧回路
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KR100608112B1 (ko) * 2004-08-27 2006-08-02 삼성전자주식회사 과전류 보호회로를 구비한 전원 레귤레이터 및 전원레귤레이터의 과전류 보호방법
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JP6510828B2 (ja) * 2015-02-05 2019-05-08 ローム株式会社 リニア電源及びこれを用いた電子機器
JP6491520B2 (ja) * 2015-04-10 2019-03-27 ローム株式会社 リニア電源回路
RU2611021C2 (ru) * 2015-05-26 2017-02-17 Федеральное государственное образовательное бюджетное учреждение высшего профессионального образования "Сибирский государственный университет телекоммуникаций и информатики" (ФГОБУ ВПО "СибГУТИ") Стабилизатор постоянного напряжения
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GB2558877A (en) * 2016-12-16 2018-07-25 Nordic Semiconductor Asa Voltage regulator

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WO2021055923A1 (fr) 2021-03-25
US10942536B1 (en) 2021-03-09
CN114424139B (zh) 2024-05-14
EP4031954A4 (fr) 2022-11-16
KR20220061134A (ko) 2022-05-12
JP2022549254A (ja) 2022-11-24
CN114424139A (zh) 2022-04-29
US20210089067A1 (en) 2021-03-25

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