EP3987326A1 - Verfahren zum herstellen einer bauteilanordnung für ein package, verfahren zum herstellen eines packages mit einer bauteilanordnung, bauteilanordnung und package - Google Patents
Verfahren zum herstellen einer bauteilanordnung für ein package, verfahren zum herstellen eines packages mit einer bauteilanordnung, bauteilanordnung und packageInfo
- Publication number
- EP3987326A1 EP3987326A1 EP20737085.9A EP20737085A EP3987326A1 EP 3987326 A1 EP3987326 A1 EP 3987326A1 EP 20737085 A EP20737085 A EP 20737085A EP 3987326 A1 EP3987326 A1 EP 3987326A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- component
- wafer
- optical
- package
- produced
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 10
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- 229910052782 aluminium Inorganic materials 0.000 description 6
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- 238000000576 coating method Methods 0.000 description 6
- 239000011521 glass Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 5
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- 229910052709 silver Inorganic materials 0.000 description 5
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 4
- 238000000149 argon plasma sintering Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
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- 229910052732 germanium Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000031700 light absorption Effects 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
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- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- KYQCOXFCLRTKLS-UHFFFAOYSA-N Pyrazine Chemical compound C1=CN=CC=N1 KYQCOXFCLRTKLS-UHFFFAOYSA-N 0.000 description 2
- YCIMNLLNPGFGHC-UHFFFAOYSA-N catechol Chemical compound OC1=CC=CC=C1O YCIMNLLNPGFGHC-UHFFFAOYSA-N 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
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- QPLDLSVMHZLSFG-UHFFFAOYSA-N Copper oxide Chemical compound [Cu]=O QPLDLSVMHZLSFG-UHFFFAOYSA-N 0.000 description 1
- 239000005751 Copper oxide Substances 0.000 description 1
- 229910000599 Cr alloy Inorganic materials 0.000 description 1
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 1
- PIICEJLVQHRZGT-UHFFFAOYSA-N Ethylenediamine Chemical compound NCCN PIICEJLVQHRZGT-UHFFFAOYSA-N 0.000 description 1
- 241000511976 Hoya Species 0.000 description 1
- 229910018487 Ni—Cr Inorganic materials 0.000 description 1
- PCNDJXKNXGMECE-UHFFFAOYSA-N Phenazine Natural products C1=CC=CC2=NC3=CC=CC=C3N=C21 PCNDJXKNXGMECE-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- 239000003822 epoxy resin Substances 0.000 description 1
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- LNEPOXFFQSENCJ-UHFFFAOYSA-N haloperidol Chemical compound C1CC(O)(C=2C=CC(Cl)=CC=2)CCN1CCCC(=O)C1=CC=C(F)C=C1 LNEPOXFFQSENCJ-UHFFFAOYSA-N 0.000 description 1
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B5/00—Optical elements other than lenses
- G02B5/08—Mirrors
- G02B5/0808—Mirrors having a single reflecting layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0225—Out-coupling of light
- H01S5/02255—Out-coupling of light using beam deflecting elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02019—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/02208—Mountings; Housings characterised by the shape of the housings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/023—Mount members, e.g. sub-mount members
- H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/023—Mount members, e.g. sub-mount members
- H01S5/02325—Mechanically integrated components on mount members or optical micro-benches
- H01S5/02326—Arrangements for relative positioning of laser diodes and optical components, e.g. grooves in the mount to fix optical fibres or lenses
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0233—Mounting configuration of laser chips
- H01S5/02345—Wire-bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0239—Combinations of electrical or optical elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Definitions
- Method for producing a component arrangement for a package Method for producing a package with a component arrangement, component arrangement and package
- the invention relates to a method for producing a component arrangement for a package, a method for producing a package with a component arrangement, a component arrangement and package.
- the component arrangement can be used to produce a package, that is to say generally a casing or the formation of a housing which accommodates the component arrangement including the connection points.
- a method for producing such a component arrangement is known, for example, from document WO 201 1/035783 A1.
- a spacer is arranged on a carrier substrate in such a way that the spacer surrounds an installation space in which a component is arranged.
- the installation space is closed by placing a cover substrate on the spacer. With the cover substrate, a light-permeable exit opening can be provided through which light can be emitted or received.
- Wall surfaces of the spacer facing the installation space can be provided with a metallization in order to provide a light-reflecting mirror coating.
- Document WO 2016/055520 A1 describes the production of a package for a laser component with a housing which comprises a carrier which has a cavity with a bottom surface and a side wall. The cavity expands starting from the bottom surface.
- a laser chip is arranged on the bottom surface, the direction of emission of which is oriented parallel to the bottom surface.
- a reflective element is also arranged in the cavity, which element rests against an edge between the bottom surface and the side wall.
- a reflective surface of the reflective element forms an angle of 45 degrees with the bottom surface of the cavity.
- the direction of emission also includes an angle of 45 degrees with the reflective surface of the reflective element.
- Component arrangement is also known from the document WO 2017/149573 A1.
- the object of the invention is to provide a method for producing a component arrangement for a package and for producing a package as well as a component arrangement and a package in which an optical functional surface can be produced more efficiently and with improved quality with regard to the optical properties.
- a method for producing a component arrangement for a package and a method for producing a package with a component arrangement according to independent claims 1 and 11 are created. Furthermore, a component arrangement according to independent claim 12 and a package according to independent claim 13 are provided. Refinements are the subject of the dependent subclaims.
- a method for producing a component arrangement for a package comprising: providing a wafer made of a semiconductor material with a polished wafer surface, an anisotropically etched surface being produced in the region of the opening; Forming an opening in the wafer using an anisotropic etch; Separation of a component from the anisotropically etched wafer, the separated component having an optical surface which is formed in the region of a surface portion of the polished wafer surface, and a mounting surface is produced which is formed in the region of the anisotropically etched surface; and mounting the separated component on a substrate surface of a carrier substrate using the mounting surface so that the anisotropically etched surface is connected to the substrate surface, the optical surface being arranged as an inclined exposed surface.
- a method for producing a package with such a component arrangement is provided, a housing being produced by means of a housing component in which at least the individual component is received.
- a component arrangement is provided with a carrier substrate and a component arranged thereon, which component has been separated from a wafer made of a semiconductor material.
- the component has a mounting surface on an anisotropically etched surface and is mounted on a substrate surface of the carrier substrate using the mounting surface.
- the component has an optical surface which is cut in a surface section of a polished wafer surface of the wafer. The optical surface is arranged as an inclined exposed surface.
- a package with such a component arrangement is also provided, a housing being formed by means of a housing component, in which at least the component is received.
- the optical surface can be designed to be at least partially light-reflecting, light-scattering and / or light-absorbing in relation to incident light rays. In one embodiment, the optical surface can also be designed to polarize (light-polarize) incident light.
- the anisotropic etching can be carried out by means of wet-chemical etching, for example with the aid of etching with potassium hydroxide (KOH).
- KOH potassium hydroxide
- Other usable etching solutions for anisotropic etching are, for example, tetramethylammonium hydroxide (TMAH) or a mixture of ethylenediamine and water with additions of pyrocatechol and pyrazine (EDP, ethylenediamine-pyrocatechol), especially in connection with silicon.
- TMAH tetramethylammonium hydroxide
- EDP ethylenediamine-pyrocatechol
- dry etching can also be used.
- one or more additives for example salts, can be added to the etching solution.
- Alcohol-based additives can also be used here, for example isopropanol.
- the additives can also increase the selectivity of the etching rates of the crystal planes to be etched.
- the polished surface itself can be used to form the optical surface, that is to say without depositing or arranging layer material on it.
- the optical surface can be produced with an optical functional surface, in which case an optical functional layer is deposited in the surface section of the polished wafer surface. is brought in such a way that the optical properties of the polished wafer surface are changed in the surface portion.
- the optical functional layer with which the optical functional surface is formed in the area of the polished wafer surface, specifically changes the optical properties of the surface section compared to its optical properties without the optical functional layer, i.e. in the state of the polished wafer surface.
- different optical properties can be provided in the surface section, in particular the behavior with regard to light reflection, light absorption and / or light scattering.
- the optical functional surface can be designed to be at least partially light-reflecting, light-scattering and / or light-absorbing in relation to incident light rays.
- the production of the optical functional surface in the area of the polished wafer surface has the advantage that the optical functional layer is applied to a substrate, namely the polished wafer surface, which can be reproduced at the wafer level with the desired surface properties, in particular with regard to its smoothness.
- the optical functional surface with the optical functional layer can be applied at wafer level before the separation. At wafer level, several separate optical functional surfaces can be produced in the area of the polished wafer surface, which then serve as an optical functional surface for separate components when singled out. As an alternative to applying the optical functional surface (s) at the wafer level, the optical functional surface can be produced after the separation.
- the optical functional surface can be produced with a microstructured layer.
- the microstructured layer makes it possible to provide the optical functional surface or layer with the desired optical properties. For example, it can be provided that the microstructured layer reflects incident light beams in a focusing / expanding and / or scattering manner. In the area of the microstructured layer, Fresnel lenses can be provided at least in some areas.
- a layer material such as glass or plastic can be applied to the polished wafer surface.
- a micro-structuring of the optical functional layer can include processing using one or more methods from the following group: molding, embossing, molding, etching, 3D printing and plastering machining, for example to produce one or more lenses (for example trough (s)) in the layer material.
- the polished wafer surface can be processed at the wafer level, that is to say without applying the optical functional layer, for example to produce at least one lens.
- the microstructure produced can then be provided with a mirror coating in the various embodiments.
- the optical functional layer can be applied as a multilayer system.
- Multi-layer systems also support the formation of desired optical properties, which are provided in the area of the surface section of the polished wafer surface by means of the optical functional layer.
- a dielectric mirror can be applied in this way.
- the anisotropically etched surface can be produced with an inclination angle of about 45 degrees to the polished wafer surface.
- the optical functional surface can have an angle of inclination of approximately 45 degrees to the surface of the carrier substrate (and to the polished wafer surface). With appropriately manufactured crystals - for example tilting for 100% orientation of a silicon crystal - almost any angle of inclination can be precisely adjusted.
- the mounting surface can be formed with a mounting functional layer that is produced in the area of the mounting surface
- the assembly functional layer can be produced with a solderable metallization. When the separated component is mounted on the substrate surface of the carrier substrate, it is then soldered on using the solderable metallization.
- the assembly functional layer can be produced to have an adhesive layer.
- the assembly functional layer can be applied at the wafer level before the separation. In the area of the anisotropically etched surfaces, several separate assembly functional layers can be produced in different areas, so that these then serve as the respective assembly functional layer for different components after separation, which makes it possible to assemble each individual component. If assembly functional layers are produced in different sections of the anisotropically etched surfaces, this makes it possible to provide components with the respective optical functional surface after the separation, in which the optical functional surface has different angles of inclination in relation to the polished wafer surface. This makes use of different angles of inclination that arise during etching. As an alternative to applying the assembly functional layer (s) at the wafer level, the assembly functional layer can be produced after the separation.
- the optical functional surface can be used to deflect or reflect light rays emitted by an optical component, for example a light-emitting diode, out of the component arrangement or the package, so that the light rays are emitted.
- the optical functional surface on the individual component on the carrier substrate can be used to couple light rays incident onto the component arrangement or the package onto a light-receiving or light-sensitive component, for example a light-sensitive diode or a light-sensitive transistor.
- a housing component has an optical window through which light rays can be emitted and / or received.
- the optical component in the package can be designed as a light-emitting or light-absorbing component, for example as a light-emitting diode or light-absorbing photodiode, for example an avalanche photodiode, Si photomultiplier or laser diode.
- the light-emitting component can be designed to emit light beams in a directed and bundled form, for example in the form of essentially directed laser radiation with central emission of the intensity maximum with optionally available beam divergence (beam expansion).
- the proposed technology makes it possible to arrange the optical component in the installation space of the package in such a way that the emitted light rays or the entry of the light rays to be received can take place in the vertical direction.
- the optical component In order to emit light rays in a vertical direction (in relation to the surface of the carrier substrate), it is not necessary, in contrast to the prior art, to arrange the optical component in the installation space upright, as is provided in the prior art (see FIG Example US 7 177 331 B2).
- the overall height of the construction part arrangement and the package can be reduced and assembly can be simplified.
- Contact connections can have a plated through-hole through the carrier substrate, it being possible for external contacts to be arranged on the underside of the carrier substrate.
- a contact connection led laterally out of the installation space can be provided, for example on the surface of the carrier substrate facing the installation space, in particular such that the laterally extended contact connection between carrier substrate and spacer is formed through it.
- the contact connection can comprise several individual contact connections.
- the optical component can be arranged on a submount which is arranged on the Trä gersubstrat.
- the submount can be formed from silicon carbide, aluminum nitride, aluminum oxide or silicon, for example. To produce the package, it can be provided that the packaging is used for this purpose or at the wafer level.
- a single or multiple elements with an optical functional surface inclined by 45 degrees can be manufactured at wafer level.
- the advantage is that many elements can be produced at the same time at the wafer level.
- the individual components for example mirror elements, are then created after singulation, for example by sawing the substrate.
- the component can be housed by applying an isolated cap to a board on which a chip or component is preassembled, for example an optical component with a mirror element.
- the components can also be pre-assembled in a panel, i.e. that several components are already mounted on a carrier substrate, which are then housed by applying individual caps or cap arrays (individual panels with several cap structures from a cap substrate produced in the wafer level).
- Wafer-level packaging in the meaning used here refers to the packing of all components on a wafer in one step with a cover substrate in wafer form (“packaging”). For example, this can be the case if components are completely preassembled on a plated-through substrate, for example a silicon substrate in wafer form, and then all components are housed at the same time by bonding a cap wafer, for example an optical component with a mirror element. Individual packages are then created by subsequently separating the group.
- the cover substrate in particular in the area or to form an outlet and / or inlet opening, can, for example, be made of borosilicate glass such as Bofofloat33 or Mempax from Schott AG, quartz glass, sapphire glass or other glasses such as AF32, D263T, BK7 or B270 from Schott AG; Eagle XG or Pyrex from Corning; SD2 from Hoya or EN-A1 from Asahi exist.
- the cover substrate can also be made of silicon or germanium, for example for applications in the IR range.
- the cover substrate can additionally have a substrate coating, for example an anti-reflection coating.
- the coatings can be designed for different wavelength ranges and can be implemented on one or both sides. Filter coatings and / or opaque aperture structures for different wavelength ranges can also be provided.
- optical elements can be integrated, for example lenses on the cover substrate.
- convex lenses made of polymer, glass-like materials, silicon or germanium come into consideration here.
- microstructured Fresnel lenses is also possible.
- One or more plated-through holes for the electrical contact of the optical component are provided in the carrier substrate.
- the contacts on the back enable later assembly in the SMD design, for example using tin / silver wave soldering or assembling with electrically conductive adhesives.
- the carrier substrate can for example consist of silicon, ceramics such as aluminum nitride, silicon carbide, aluminum oxide, LTTC ceramic (Low Temperature Cofired Ceramics) or HTCC ceramic (High Temperature Cofired Ceramics), glass or DBC (Direct Bonded Copper) substrates.
- ceramics such as aluminum nitride, silicon carbide, aluminum oxide, LTTC ceramic (Low Temperature Cofired Ceramics) or HTCC ceramic (High Temperature Cofired Ceramics), glass or DBC (Direct Bonded Copper) substrates.
- metal substrates for example IMS (Insulated Metal Substrate) made of copper, aluminum or other metals, can be provided.
- the use of plastic carrier substrates such as FR4 is also conceivable.
- the carrier substrate can be a 3D structured ceramic. In this case, a spacer can not be formed in the cap, but in the carrier substrate.
- a plate for example by means of a glass plate. It is common here for a ceramic top and the plate to have a correspondingly solderable metallization. For certain applications, however, the use of an adhesive can also be seen here.
- the optical window can be designed with or as a® lens. This makes it possible to collimate or scatter electromagnetic radiation from the package.
- a connection between the cap or housing (or when inserting an optical window into the 3-D ceramic) and the carrier substrate in the package can be made, for example, via a solder bond, preferably via a eutectic bond.
- a metal combination in preferably eutectic composition is applied to the carrier substrate or the back of the spacer of a housing cap, for example gold and tin, copper and tin, gold and germanium, tin and silver, gold and indium, copper and silver or gold and silicon , which forms a eutectic connection phase in a soldering process and connects spacers with carrier substrate.
- the spacer and carrier substrate are provided with a corresponding base metallization for the soldering process.
- the metal combination for eutectic joining can be provided as a pre-form, for example. Alternatively, the metal combination can be applied to one of the joining partners as a paste or galvanically.
- alloy stop under the actual connection phase.
- layers of platinum or nickel or alloys of chromium and nickel are suitable for the eutectic joining of gold and tin.
- the metal combinations of the joining layer described here are also suitable as a version for the solderable assembly functional layer.
- the mirror and board can also be connected by means of a solder bond or a eutectic bond with the aforementioned metal combinations.
- Tin / silver solders, for example SAC305 can be used for a solder bond.
- a direct bonding process can also be used using very high surface qualities of Ra ⁇ 1 nm.
- This can be a direct fusion bond, which is hydrophobic or hydrophilic based on the surface character of the bond partners.
- the two bond partners are first connected to one another via a pre-bond using van der Waals bonds.
- a subsequent tempering step then forms covalent bonds in the bond interface.
- the fusion bond can also be made plasma-activated. This makes it possible to significantly reduce the temperature load during annealing.
- Anodic bonding can be provided as a further direct bonding method.
- a reactive bonding process can also be used. With a reactive bond, a metal stack made up of alternating layers is applied.
- This metal stack can be provided, for example, by deposition processes such as sputtering or in the form of foils.
- An electrical or laser-induced pulse leads to a short-term generation of a highly thermal reaction that "welds" the two bond partners together.
- the metal layers are bilayer periods, for example made of palladium and aluminum or made of copper oxide and aluminum.
- Solid-liquid interdiffusion bonding can also be used, for example made of metal combinations of gold and indium, gold and tin, or copper and tin.
- the bonding process during a tempering step is determined by the diffusion of one bonding partner into the other.
- the actual connection phase then withstands higher temperatures later.
- permanent connections can be produced by joining, for example, gold with gold, copper with copper or also aluminum with aluminum by means of (for example) thermal compression bonding. Glass-frit bonding can also be provided.
- a laser welding process can be used to connect the carrier substrate and spacer.
- the use of epoxy resins, silicones or other adhesives is also conceivable.
- a direct bonding process for example, can be used to connect the spacer and cover substrate (for example manufacturing a cap wafer). Such processes are, for example, the anodic bond or a fusion bond. Reactive bonding or an adhesive bond can also be used. Solid-liquid interdiffusion bonds or a eutectic solder bond are also possible here.
- Laser welding is also suitable for joining the spacer and cover substrate. Here, two substrates are brought into “optical contact” and then welded with a laser. It is conceivable to use all of the above-mentioned joining methods for spacers and carrier substrate likewise for joining spacers and cover substrate. Description of exemplary embodiments
- FIG. 1 shows a schematic illustration of a wafer in section
- FIG. 2 shows a schematic representation of the wafer from FIG. 1 in section, in which openings are now anisotropically etched at wafer level;
- FIG. 3 shows a schematic representation of the wafer from FIG. 2 in section, with an assembly functional layer being produced at wafer level in the region of anisotropically etched surfaces and optical functional surfaces in the region of surface sections of a polished wafer surface;
- FIG. 4 shows a separated component element which was produced by separating from the wafer in FIG. 3;
- FIG. 5 shows a schematic sectional illustration of a package in which the separated component from FIG. 4 is mounted on a carrier substrate;
- FIG. 6 shows a schematic representation of different embodiments for a single component
- FIG. 7 shows a schematic representation of an arrangement with an optical component whose emitted light is reflected on a flat surface
- FIG. 8 shows a schematic representation of an arrangement with an optical component, the emitted light of which is converted into a parallel beam
- FIG. 9 shows a schematic sectional illustration of a package in which an isolated component and an optical component are arranged in a recess of a submount.
- Fig. 10 is a schematic sectional illustration of a package in which an isolated component and an optical component are arranged on a submount.
- FIG. 1 shows a schematic illustration of a wafer 1 in section.
- FIG. 2 shows a schematic illustration of the wafer 1 from FIG. 1 in section, the wafer
- the wafer 1 in FIG. 2 has anisotropically etched surfaces 4, on which, as shown in FIG. 3, an assembly functional layer 5 is applied in each case, which is formed with a solderable metallization in the embodiment shown.
- an optical functional view 8 for example, a dielectric mirror can be provided.
- the optical properties of the polished wafer surface 6 are changed compared to the state without the optical functional layer 8, for example with regard to light reflection, light scattering and / or light absorption.
- the optical functional layer 8 can be microstructured, for example to provide Fresnel lenses in the optical functional surface 7. Such a microstructuring is made possible, since the polished wafer surface 6 provides a sufficiently smooth substrate.
- a component or component 9 is made by separating the wafer 1.
- the separated component 9 can then be mounted according to FIG. 5 in a package 10 on a sub stratthesis 11 of a carrier substrate 12 by means of soldering, the solderable metallization of the assembly functional layer 5 being used to the separated compo element 9 on the carrier substrate 12 assemble.
- the optical functional surface 7 is arranged as an exposed surface which has an angle of inclination with respect to the substrate surface 11, for example approximately 45 degrees.
- a housing component 13 which can be made in one or more pieces, a building space 14 is provided in which the separated component 9 and an optical component 15, which is also mounted on the substrate surface 11, for example by means of soldering or bonding, is arranged .
- the housing component 13 is formed, for example, with spacers 13a, 13b and a cover component or cover substrate 13c.
- Light beams 16 incident on the optical functional surface 7 are at least partially reflected.
- the formation of the optical functional surface 7 with a dielectric mirror enables such light deflection or guidance.
- FIG. 6 shows a schematic representation of the separated component or element 9 in various embodiments.
- an upper edge 9a has been produced, for example, by means of mechanical processing, for example sawing.
- the upper edge 9a is produced by means of etching.
- an inclination angle of 64 degrees is formed.
- the upper edge 9a is etched at an angle of 45 degrees. This can be achieved, for example, by anisotropic etching from both sides at the same time.
- an etching mask made of, for example, LPCVD nitride is structured on both sides aligned with one another and then the substrate is etched, for example in KOH.
- the upper edge 9a is formed parallel to the mounting surface. This enables the component 9 to be effectively handled in a later assembly process, since in this case the component can be processed with standardized pick & place machines.
- the optical functional layer 8 and / or the assembly functional layer 5 can be omitted.
- the optical functional surface 7 is then free of the optical functional layer 8.
- the optical properties for example the reflectivity, can correspond to those of the polished wafer surface 6.
- An adhesive applied at this point in time can serve as an alternative assembly functional layer 5 during assembly.
- 7 and 8 show different configurations for an arrangement with the optical component 15, which emits light, as well as the isolated component 9. The light emitted by the optical component 15 is reflected on a flat optical functional surface according to FIG. so that a light beam is emitted with an opening angle.
- the optical functional surface 7 is formed with a depression (lens), so that a parallel beam is emitted by means of beam shaping.
- FIG. 9 and 10 show schematic sectional illustrations of a package in which the individual component 9 and the optical component 15 are arranged on a carrier substrate 12 designed as a submount.
- the optical component 16 is connected via vias 30.
- the carrier substrate 12 has a recess 20.
- the cover substrate 13c is spaced apart from the carrier substrate 12 by means of the spacers 13a, 13b which are mounted on the carrier substrate 12.
- Such spacers are formed in the embodiment in FIG. 9 by means of lateral sections 12a, 12b of the carrier substrate (submount) itself 12, which laterally delimit the depression 20.
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Optics & Photonics (AREA)
- Electromagnetism (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Optical Couplings Of Light Guides (AREA)
- Led Device Packages (AREA)
- Semiconductor Lasers (AREA)
- Light Receiving Elements (AREA)
- Optical Elements Other Than Lenses (AREA)
Abstract
Description
Claims
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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DE102019116920 | 2019-06-24 | ||
DE102019118797.4A DE102019118797B4 (de) | 2019-06-24 | 2019-07-11 | Verfahren zum Herstellen einer Bauteilanordnung für ein Package, Verfahren zum Herstellen eines Packages mit einer Bauteilanordnung, Bauteilanordnung und Package |
PCT/DE2020/100529 WO2020259755A1 (de) | 2019-06-24 | 2020-06-22 | Verfahren zum herstellen einer bauteilanordnung für ein package, verfahren zum herstellen eines packages mit einer bauteilanordnung, bauteilanordnung und package |
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EP3987326A1 true EP3987326A1 (de) | 2022-04-27 |
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EP20737085.9A Pending EP3987326A1 (de) | 2019-06-24 | 2020-06-22 | Verfahren zum herstellen einer bauteilanordnung für ein package, verfahren zum herstellen eines packages mit einer bauteilanordnung, bauteilanordnung und package |
Country Status (8)
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US (1) | US20220415645A1 (de) |
EP (1) | EP3987326A1 (de) |
JP (1) | JP2022539450A (de) |
KR (1) | KR20220024776A (de) |
CN (1) | CN114008876A (de) |
DE (1) | DE102019118797B4 (de) |
TW (1) | TW202101619A (de) |
WO (1) | WO2020259755A1 (de) |
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DE102022100008B4 (de) | 2022-01-03 | 2024-01-18 | Schott Ag | Strukturierter Wafer und damit hergestelltes optoelektronisches Bauteil |
TWI822634B (zh) * | 2022-07-20 | 2023-11-11 | 強茂股份有限公司 | 晶圓級晶片尺寸封裝方法 |
DE102022121034A1 (de) * | 2022-08-19 | 2024-02-22 | Ams-Osram International Gmbh | Strahlungsemittierendes bauteil und verfahren zur herstellung eines strahlungsemittierenden bauteils |
Family Cites Families (14)
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US6271049B1 (en) * | 1998-09-14 | 2001-08-07 | Siemens Aktiengesellschaft | Method for producing an optoelectronic component |
US7177331B2 (en) | 2004-11-30 | 2007-02-13 | Arima Optoelectronics Corp. | Laser diode module with a built-in high-frequency modulation IC |
US7470622B2 (en) * | 2005-06-17 | 2008-12-30 | Hymite A/S | Fabrication and use of polished silicon micro-mirrors |
US7481545B2 (en) * | 2005-10-13 | 2009-01-27 | Avago Technologies Fiber Ip (Singapore) Pte. Ltd. | Method of forming and mounting an angled reflector |
US7538413B2 (en) * | 2006-12-28 | 2009-05-26 | Micron Technology, Inc. | Semiconductor components having through interconnects |
JP2010522349A (ja) * | 2007-03-19 | 2010-07-01 | ジョン・スー・キム | 自立型平行板ビームスプリッタ、その製作方法、およびそれを用いたレーザーダイオードパッケージ構造 |
TW201108332A (en) * | 2009-08-27 | 2011-03-01 | Univ Nat Central | Package base structure and related manufacturing method |
DE102009042479A1 (de) | 2009-09-24 | 2011-03-31 | Msg Lithoglas Ag | Verfahren zum Herstellen einer Anordnung mit einem Bauelement auf einem Trägersubstrat und Anordnung sowie Verfahren zum Herstellen eines Halbzeuges und Halbzeug |
EP3066727A4 (de) * | 2013-11-07 | 2017-05-17 | MACOM Technology Solutions Holdings, Inc. | Laser mit strahlform- und strahlrichtungsänderung |
DE102014114618A1 (de) | 2014-10-08 | 2016-04-14 | Osram Opto Semiconductors Gmbh | Laserbauelement und Verfahren zu seiner Herstellung |
JP6217706B2 (ja) * | 2015-07-29 | 2017-10-25 | 日亜化学工業株式会社 | 光学部材の製造方法、半導体レーザ装置の製造方法及び半導体レーザ装置 |
JP6354704B2 (ja) * | 2015-08-25 | 2018-07-11 | 日亜化学工業株式会社 | 光学部材の製造方法、半導体レーザ装置の製造方法及び半導体レーザ装置 |
WO2017149573A1 (ja) | 2016-03-02 | 2017-09-08 | ソニー株式会社 | 発光装置及び発光装置の製造方法 |
JP7007560B2 (ja) * | 2017-09-28 | 2022-01-24 | 日亜化学工業株式会社 | 光源装置 |
-
2019
- 2019-07-11 DE DE102019118797.4A patent/DE102019118797B4/de active Active
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2020
- 2020-06-22 US US17/618,920 patent/US20220415645A1/en active Pending
- 2020-06-22 CN CN202080045827.8A patent/CN114008876A/zh active Pending
- 2020-06-22 EP EP20737085.9A patent/EP3987326A1/de active Pending
- 2020-06-22 WO PCT/DE2020/100529 patent/WO2020259755A1/de unknown
- 2020-06-22 JP JP2021575462A patent/JP2022539450A/ja active Pending
- 2020-06-22 KR KR1020227002001A patent/KR20220024776A/ko unknown
- 2020-06-24 TW TW109121743A patent/TW202101619A/zh unknown
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DE102019118797B4 (de) | 2023-01-12 |
TW202101619A (zh) | 2021-01-01 |
JP2022539450A (ja) | 2022-09-09 |
WO2020259755A1 (de) | 2020-12-30 |
KR20220024776A (ko) | 2022-03-03 |
CN114008876A (zh) | 2022-02-01 |
DE102019118797A1 (de) | 2020-12-24 |
US20220415645A1 (en) | 2022-12-29 |
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