EP3893009B1 - Vorrichtung zur erkennung ungültiger konfigurationen in bi-direktionalen multiplex-schaltungen - Google Patents

Vorrichtung zur erkennung ungültiger konfigurationen in bi-direktionalen multiplex-schaltungen Download PDF

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Publication number
EP3893009B1
EP3893009B1 EP20208980.1A EP20208980A EP3893009B1 EP 3893009 B1 EP3893009 B1 EP 3893009B1 EP 20208980 A EP20208980 A EP 20208980A EP 3893009 B1 EP3893009 B1 EP 3893009B1
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EP
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Prior art keywords
source
infrastructure
directional multiplexing
sources
sinks
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EP20208980.1A
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English (en)
French (fr)
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EP3893009A1 (de
Inventor
Daniel Jakschik
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Priority to CN202180021518.1A priority Critical patent/CN115398255A/zh
Priority to PCT/EP2021/058373 priority patent/WO2021204612A1/en
Publication of EP3893009A1 publication Critical patent/EP3893009A1/de
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31926—Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Definitions

  • the invention relates to an apparatus for detecting invalid configurations in bi-directional multiplexing infrastructures.
  • a multiplexer is a circuitry which selectively drives an output signal Z from different sources A, B, C, ... depending on a control signal SZ.
  • Figure 1 shows the symbol of a multiplexer and a simplified circuitry.
  • the output Z is driven by input A as soon as the control signal SZ is 0; input B is forwarded as soon as SZ becomes 1, and so on.
  • the number of N identifies the size of the multiplexer.
  • the example multiplexer 1 of figure 1 has four inputs 2 and is there with a 4:1 multiplexer.
  • the width of the data signals Z, A, B, C ... is always identical; here they have the width 1. But any data width is supported.
  • Multiplexer can be used as switching elements, see for example EP 1 426 780 A2 and US 2004/0111657 A1 .
  • the multiplexer 1 is realized by two parts, the data path as one part and the control part 5 as another part, as shown in figure 2 .
  • the output Z is created by OR'ing all sources, which are gated by an AND-gate. Just one of the AND-gates gets a highlevel on its second input and therewith just one multiplexer input passes.
  • the control part 5 generates the secondary AND-gate input signals.
  • a one-hot decoder creates a high signal depending on the control signal SZ.
  • the forward multiplexers 7 are steered by the control signals SW, SX, SY and SZ 9.
  • the backward direction multiplexer control can be derived from SW, SX, SY and SZ 9. Due to the fact, that there are four sinks and four sources in the example of figure 3 , the width of the control signals Sm n is two. It is good to present the forward control signals SW, SX, SY and SZ to the end-user, as they are easy to understand, if the basic principle of a multiplexer is understood.
  • the object will be solved by an apparatus for detecting invalid configurations in a bi-directional multiplexing infrastructure according to independent claim 1.
  • the inventive apparatus that comprises the infrastructure, which comprises a multiplexer decoder logic configured to process control signals, multiple sources as inputs and multiple sinks as outputs, whereas the sources and sinks are connected via forward and backward multiplexers, wherein the multiplexer decoder logic is extended by a configuration error checker which monitors each source and all control signals of the backward multiplexers connected to the sources and creates error information which source is used more than once.
  • the configuration error detector is configured to detect invalid configurations.
  • the multiplexer decoder logic is configured to generate the backward multiplexer control signals Sm n , where m stands for the sink identifier and n stands for the source identifier.
  • the configuration error detector can be applied on bi-directional multiplexing infrastructures with any number of sources N and any number of sinks M and gives detailed information on the configuration error.
  • M and N are positive natural number greater than 0. It eases debugging and configuration of complex bi-directional multiplexers with larger numbers of N and M.
  • the configuration error detector evaluates all backward multiplexer control signals and creates error information which source is used more than once. The backward signals for instance might signal if the next data can be accepted or a pause needs to be inserted.
  • the multiplexer configuration is invalid as soon as more than one multiplexer selects the corresponding source.
  • the configuration error checker comprises an evaluation instance for each source n, whereas each evaluation instance outputs a logical equivalent E n to the control signals of the backward multiplexers for one source n.
  • the configuration error checker or an evaluation instance for a source is only needed, if a source has to handle backward signals. Sources without backward signals do not need any multiplexer configuration checking.
  • the evaluation instance for each source n comprises standard-cells with AND- and OR-gates.
  • the implementation of the inventive apparatus is very easy in chip design.
  • the logical equivalent E n for one source n is determined by connecting the control signals of two sinks for said source n by an AND- and by an OR-operation, the result of the OR-operation is combined with a control signal of a further sink for said source n by an AND- and by an OR-operation, whereas this is going on until the control signals of all sinks for said source n are processed such and finally all outputs of the processed AND-operations are connected by a final OR-operation.
  • the determination of the logical equivalent E n is realized by standard-cells.
  • the multiplexer decoder logic generates the internal control signals Sm n for the backward multiplexers, whereas each sink m contributes a control signal Sm n to a source n of the bi-directional multiplexing infrastructure if said source n can be reached by backward signals.
  • These control signals are further processed by the evaluation instance for each source in order to determine the logical equivalent E n for each source n and to evaluate if said source n is only used once, otherwise the configuration would be invalid, as it is not allowed to select an already allocated source more than once.
  • the bi-directional multiplexing infrastructure is invalid as soon as more than one multiplexer selects the corresponding source.
  • a sum E over all logical equivalents E n for all sources n is equal to zero the entire bi- directional multiplexing infrastructure is valid, otherwise it is invalid.
  • the number N of sources is equal or greater than two and in another variant the number M of sinks is equal or greater than two.
  • the inventive apparatus works for any bi-directional multiplexer complexity, hence of any number of sources N and sinks M.
  • a width of the multiplexed data signals is independent to the configuration error checker and can be any positive number.
  • the inventive apparatus works for any bi-directional multiplexer complexity. For any number of sources N and sinks M.
  • Figure 4 shows the inventive apparatus which can be seen as an extension to the multiplexer decoder logic 11 as the configuration error checker 14 uses the generated internal control signals Sm n for the backward multiplexers for evaluating if an error condition is fulfilled or not, hence if E n is equal to zero or one.
  • Figure 4 does not show the whole bi-directional multiplexer infrastructure.
  • the configuration error checker circuitry 14 based on standard-cells.
  • the lower part in figure 4 contains the multiplexer decoder logic 11 which generates the multiplexer internal control signals Sm n .
  • the upper part contains two evaluation instances 15 of the configuration error checker 14 for the sources A and B.
  • the circuitry can be repeated for all other source (i. e. C and D).
  • One application of the present invention is the multiplexing of bi-directional pads on a chip. Every pad (sink) has multiple control signals, like output, output-enable, pullup control and so on and feeds back the pad input level to the digital logic inside the chip.
  • the pad might be used for different purposes and therewith by different chip-internal blocks, i. e. UART, SPI, I2C.
  • the chip-internal blocks (sources) can be muxed to multiple pads (sinks).
  • the configuration error checker hence the evaluation instance per pad eases the handling of complex setups.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)

Claims (6)

  1. Vorrichtung zum Erkennen von ungültigen Konfigurationen in einer bidirektionalen Multiplexing-Infrastruktur, wobei die Vorrichtung die bidirektionale Multiplexing-Infrastruktur umfasst, wobei die bidirektionale Multiplexing-Infrastruktur eine Multiplexer-Decoder-Logik (11), mehrere Quellen als Eingänge (2) und mehrere Senken als Ausgänge (3) umfasst, wobei jede Quelle der mehreren Quellen (2) einer Quelle n (2) entspricht, wobei n für den Quellen-Identifikator steht, und wobei die Quellen (2) und Senken (3) über Vorwärts- (7) und Rückwärts-Multiplexer (8) verbunden sind, dadurch gekennzeichnet, dass die Multiplexer-Decoder-Logik (11) ferner einen Konfigurationsfehlerprüfer (14) umfasst, der dazu ausgelegt ist, ungültige Konfigurationen zu erkennen und jede Quelle n (2) und alle Steuersignale (10) der mit den Quellen (2) verbundenen Rückwärtsmultiplexer (8) zu überwachen, wobei der Konfigurationsfehlerprüfer (14) eine Auswertungsinstanz (15) für jede Quelle n (2) umfasst, wobei jede Auswertungsinstanz (15) dazu ausgelegt ist, ein logisches Äquivalent En (25, 26) zu den Steuersignalen (10) der Rückwärtsmultiplexer (8) für eine Quelle n (2) auszugeben, wobei das logische Äquivalent En (25, 26) für eine Quelle n (2) durch Verbinden der Steuersignale zweier Senken für die Quelle n (2) durch eine UND- und durch eine ODER-Operation über ein UND- bzw. ein ODER-Gatter bestimmt wird, das Ergebnis der ODER-Operation mit einem Steuersignal einer weiteren Senke für die Quelle n (2) durch eine weitere UND- und durch eine weitere ODER-Operation verknüpft wird, wobei dieser Schritt des Kombinierens des Ergebnisses der ODER-Operation mit einem Steuersignal einer weiteren Senke für die Quelle n (2) durch eine weitere UND- und durch eine weitere ODER-Operation wiederholt wird, bis die Steuersignale aller Senken für die Quelle n (2) so verarbeitet sind und schließlich alle Ausgänge der verarbeiteten UND-Operationen durch eine abschließende ODER-Operation über ein abschließendes ODER-Gatter verbunden sind, und wobei die ungültige Konfiguration in der bidirektionalen Multiplexing-Infrastruktur gemäß einer Fehlerinformation erkannt wird, die von dem Konfigurationsfehlerprüfer (14) erzeugt wird, der angibt, welche Quelle n (2) mehr als einmal verwendet wird.
  2. Vorrichtung zum Erkennen ungültiger Konfigurationen in einer bidirektionalen Multiplexing-Infrastruktur nach Anspruch 1, wobei, wenn das logische Äquivalent En für eine Quelle n (2) Null ist, eine Steuersignalkonfiguration für die Quelle n (2) gültig ist, andernfalls ist sie ungültig.
  3. Vorrichtung zum Erkennen ungültiger Konfigurationen in einer bidirektionalen Multiplexing-Infrastruktur nach einem der vorhergehenden Ansprüche, wobei, wenn eine Summe E über alle logischen Äquivalente En für alle Quellen (2) gleich null ist, die gesamte bidirektionale Multiplexing-Infrastruktur gültig ist, ansonsten ist sie ungültig.
  4. Vorrichtung zum Erkennen ungültiger Konfigurationen in einer bidirektionalen Multiplexing-Infrastruktur nach einem der vorhergehenden Ansprüche, wobei die Anzahl der Quellen (2) gleich oder größer als zwei ist.
  5. Vorrichtung zum Erkennen ungültiger Konfigurationen in einer bidirektionalen Multiplexing-Infrastruktur nach einem der vorhergehenden Ansprüche, wobei die Anzahl der Senken (3) gleich oder größer als zwei ist.
  6. Vorrichtung zum Erkennen ungültiger Konfigurationen in einer bidirektionalen Multiplexing-Infrastruktur nach Anspruch 1, wobei eine Breite der gemultiplexten Datensignale unabhängig von dem Konfigurationsfehlerprüfer (14) ist und eine beliebige positive Zahl sein kann.
EP20208980.1A 2020-04-07 2020-11-20 Vorrichtung zur erkennung ungültiger konfigurationen in bi-direktionalen multiplex-schaltungen Active EP3893009B1 (de)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180021518.1A CN115398255A (zh) 2020-04-07 2021-03-30 用于检测双向多路复用基础设施中的无效配置的装置
PCT/EP2021/058373 WO2021204612A1 (en) 2020-04-07 2021-03-30 Apparatus for detecting invalid configurations in bi-directional multiplexing infrastructures

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EP3893009B1 true EP3893009B1 (de) 2023-10-25

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US6145104A (en) * 1998-02-12 2000-11-07 Motorola, Inc. Data processing system external pin connectivity to complex functions
JP2000147069A (ja) * 1998-11-13 2000-05-26 Fuji Xerox Co Ltd 半導体集積回路及びその試験方法
JP4686124B2 (ja) * 2002-12-06 2011-05-18 三星電子株式会社 装置の構成をテストする方法および半導体装置
KR100510502B1 (ko) * 2002-12-06 2005-08-26 삼성전자주식회사 반도체 장치 및 상기 반도체 장치를 테스트하는 방법

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EP3893009A1 (de) 2021-10-13
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